forked from Github_Repos/cvw
Compare commits
1 Commits
| Author | SHA1 | Date | |
|---|---|---|---|
|
af2fc0041f |
@ -1,5 +0,0 @@
|
||||
root = true
|
||||
|
||||
[src/**.sv]
|
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indent_style = space
|
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indent_size = 2
|
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83
.gitignore
vendored
83
.gitignore
vendored
@ -9,13 +9,12 @@ __pycache__/
|
||||
#External repos
|
||||
addins/riscv-arch-test/Makefile.include
|
||||
addins/riscv-tests/target
|
||||
addins/TestFloat-3e/build/Linux-x86_64-GCC/*
|
||||
benchmarks/embench/wally*.json
|
||||
|
||||
#vsim work files to ignore
|
||||
transcript
|
||||
vsim.wlf
|
||||
wlft*
|
||||
pipelined/wlft*
|
||||
wlft*
|
||||
/imperas-riscv-tests/FunctionRadix_32.addr
|
||||
/imperas-riscv-tests/FunctionRadix_64.addr
|
||||
@ -42,8 +41,8 @@ tests/linux-testgen/buildroot-image-output
|
||||
tests/linux-testgen/buildroot-config-src/main.config.old
|
||||
tests/linux-testgen/buildroot-config-src/linux.config.old
|
||||
tests/linux-testgen/buildroot-config-src/busybox.config.old
|
||||
sim/slack-notifier/slack-webhook-url.txt
|
||||
sim/logs
|
||||
pipelined/regression/slack-notifier/slack-webhook-url.txt
|
||||
pipelined/regression/logs
|
||||
fpga/generator/IP
|
||||
fpga/generator/vivado.*
|
||||
fpga/generator/.Xil/*
|
||||
@ -59,7 +58,7 @@ examples/C/sum/sum
|
||||
examples/C/fir/fir
|
||||
examples/fp/softfloat_demo/softfloat_demo
|
||||
examples/fp/fpcalc/fpcalc
|
||||
src/fma/fma16_testgen
|
||||
pipelined/src/fma/fma16_testgen
|
||||
linux/devicetree/debug/*
|
||||
!linux/devicetree/debug/dump-dts.sh
|
||||
linux/testvector-generation/genCheckpoint.gdb
|
||||
@ -76,43 +75,45 @@ synthDC/runs/
|
||||
synthDC/newRuns
|
||||
synthDC/ppa/PPAruns
|
||||
synthDC/ppa/plots
|
||||
synthDC/wallyplots/
|
||||
synthDC/plots/
|
||||
synthDC/runArchive
|
||||
synthDC/hdl
|
||||
sim/power.saif
|
||||
/pipelined/regression/power.saif
|
||||
tests/fp/vectors/*.tv
|
||||
# Temporary configs produced for synthesis
|
||||
pipelined/config/rv32e_FPUoff
|
||||
pipelined/config/rv32e_PMP0
|
||||
pipelined/config/rv32e_PMP16
|
||||
pipelined/config/rv32e_noMulDiv
|
||||
pipelined/config/rv32e_noPriv
|
||||
pipelined/config/rv32e_orig
|
||||
pipelined/config/rv32gc_FPUoff
|
||||
pipelined/config/rv32gc_PMP0
|
||||
pipelined/config/rv32gc_PMP16
|
||||
pipelined/config/rv32gc_noMulDiv
|
||||
pipelined/config/rv32gc_noPriv
|
||||
pipelined/config/rv32gc_orig
|
||||
pipelined/config/rv32ic_FPUoff
|
||||
pipelined/config/rv32ic_PMP0
|
||||
pipelined/config/rv32ic_PMP16
|
||||
pipelined/config/rv32ic_noMulDiv
|
||||
pipelined/config/rv32ic_noPriv
|
||||
pipelined/config/rv32ic_orig
|
||||
pipelined/config/rv64gc_FPUoff
|
||||
pipelined/config/rv64gc_PMP0
|
||||
pipelined/config/rv64gc_PMP16
|
||||
pipelined/config/rv64gc_noMulDiv
|
||||
pipelined/config/rv64gc_noPriv
|
||||
pipelined/config/rv64gc_orig
|
||||
pipelined/config/rv64ic_FPUoff
|
||||
pipelined/config/rv64ic_PMP0
|
||||
pipelined/config/rv64ic_PMP16
|
||||
pipelined/config/rv64ic_noMulDiv
|
||||
pipelined/config/rv64ic_noPriv
|
||||
pipelined/config/rv64ic_orig
|
||||
synthDC/Summary.csv
|
||||
sim/wkdir
|
||||
tests/custom/work
|
||||
tests/custom/*/*/*.list
|
||||
tests/custom/*/*/*.elf
|
||||
tests/custom/*/*/*.map
|
||||
tests/custom/*/*/*.memfile
|
||||
tests/custom/crt0/*.a
|
||||
tests/custom/*/*.elf*
|
||||
sim/sd_model.log
|
||||
fpga/src/sdc/*
|
||||
fpga/src/sdc.tar.gz
|
||||
fpga/src/CopiedFiles_do_not_add_to_repo/*
|
||||
sim/branch.log
|
||||
/fpga/generator/sim/imp-funcsim.v
|
||||
/fpga/generator/sim/imp-timesim.sdf
|
||||
/fpga/generator/sim/imp-timesim.v
|
||||
/fpga/generator/sim/syn-funcsim.v
|
||||
external
|
||||
sim/results
|
||||
tests/wally-riscv-arch-test/riscv-test-suite/rv*i_m/I/src/*.S
|
||||
tests/wally-riscv-arch-test/riscv-test-suite/rv*i_m/I/Makefrag
|
||||
sim/branch_BP_GSHARE10.log
|
||||
sim/branch_BP_GSHARE16.log
|
||||
sim/cov/
|
||||
sim/covhtmlreport/
|
||||
sim/imperas.log
|
||||
sim/results-error/
|
||||
sim/test1.rep
|
||||
sim/vsim.log
|
||||
tests/coverage/*.elf
|
||||
*.elf.memfile
|
||||
sim/*Cache.log
|
||||
sim/branch
|
||||
tests/fp/combined_IF_vectors/IF_vectors/*.tv
|
||||
pipelined/srt/exptestgen
|
||||
pipelined/srt/testgen
|
||||
pipelined/srt/qslc_r4a2
|
||||
pipelined/srt/qslc_r4a2.sv
|
||||
pipelined/srt/testvectors
|
||||
|
||||
3
.gitmodules
vendored
3
.gitmodules
vendored
@ -21,6 +21,3 @@
|
||||
[submodule "addins/coremark"]
|
||||
path = addins/coremark
|
||||
url = https://github.com/eembc/coremark
|
||||
[submodule "addins/branch-predictor-simulator"]
|
||||
path = addins/branch-predictor-simulator
|
||||
url = https://github.com/synxlin/branch-predictor-simulator.git
|
||||
|
||||
@ -1,24 +0,0 @@
|
||||
<!---
|
||||
SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
--->
|
||||
# Contributing
|
||||
New Contributors are always welcome.
|
||||
|
||||
## Contributor Agreement
|
||||
Most Contributors are [members](https://www.openhwgroup.org/membership/) of the
|
||||
OpenHW Group and participate in one or more [Technical Task Groups](https://www.openhwgroup.org/working-groups/).
|
||||
Membership is strongly encouraged, but not required. Contributors must be
|
||||
covered by the terms of the [Eclipse Contributor Agreement](https://www.eclipse.org/legal/ECA.php)
|
||||
(for individuals) **or** the [Eclipse Member Committer and Contributor Agreement](https://www.eclipse.org/legal/committer_process/EclipseMemberCommitterAgreement.pdf)
|
||||
(for employees of Member companies). The ECA/MCCA provides a legal
|
||||
framework for a Contributor's technical contributions to the OpenHW Group,
|
||||
including provisions for grant of copyright license and a Developer
|
||||
Certificate of Origin on contributions merged into OpenHW Group repositories.
|
||||
|
||||
## The Mechanics
|
||||
1. [Fork](https://help.github.com/articles/fork-a-repo/) the [cvw](https://github.com/openhwgroup/cvw) repository
|
||||
2. Clone repository: `git clone https://github.com/[your_github_username]/cvw`
|
||||
3. Create your feature branch: `git checkout -b <my_branch>.`<br> Please uniquify your branch name. See the [Git Cheats](https://github.com/openhwgroup/core-v-verif/blob/master/GitCheats.md) for a useful nominclature.
|
||||
5. Commit your changes: `git commit -m 'Add some feature'`
|
||||
6. Push feature branch: `git push origin <my_branch>`
|
||||
7. Submit a [pull request](https://help.github.com/en/github/collaborating-with-issues-and-pull-requests/creating-a-pull-request-from-a-fork).
|
||||
36
LICENSE
36
LICENSE
@ -1,14 +1,22 @@
|
||||
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
//
|
||||
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||
// may obtain a copy of the License at
|
||||
//
|
||||
// https://solderpad.org/licenses/SHL-2.1/
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||
// either express or implied. See the License for the specific language governing permissions
|
||||
// and limitations under the License.
|
||||
MIT License
|
||||
|
||||
Copyright (c) 2021 Harvey Mudd College & Oklahoma State University
|
||||
Contact: Prof. David Harris David_Harris@hmc.edu
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in all
|
||||
copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
SOFTWARE.
|
||||
|
||||
24
Makefile
24
Makefile
@ -1,26 +1,22 @@
|
||||
# David_Harris@hmc.edu 2023
|
||||
# Top-level Makefile for CORE-V-Wally
|
||||
# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
|
||||
all:
|
||||
make install
|
||||
make regression
|
||||
|
||||
# install copies over the Makefile.include from riscv-isa-sim
|
||||
# And corrects the TARGETDIR path and the RISCV_PREFIX
|
||||
# And corrects the TARGETDIR path and the RISCV_PREFIXZ
|
||||
|
||||
install:
|
||||
# *** 1/15/23 dh: check if any of this is still needed
|
||||
#cp ${RISCV}/riscv-isa-sim/arch_test_target/spike/Makefile.include addins/riscv-arch-test/
|
||||
#sed -i '/export TARGETDIR ?=/c\export TARGETDIR ?= ${RISCV}/riscv-isa-sim/arch_test_target' addins/riscv-arch-test/Makefile.include
|
||||
#echo export RISCV_PREFIX = riscv64-unknown-elf- >> addins/riscv-arch-test/Makefile.include
|
||||
##cd tests/linux-testgen/linux-testvectors; source ./tvLinker.sh # needs to be run in local directory
|
||||
##rm tests/imperas-riscv-tests/riscv-ovpsim-plus/bin/Linux64/riscvOVPsimPlus.exe
|
||||
##ln -s ${RISCV}/imperas-riscv-tests/riscv-ovpsim-plus/bin/Linux64/riscvOVPsimPlus.exe tests/imperas-riscv-tests/riscv-ovpsim-plus/bin/Linux64/riscvOVPsimPlus.exe
|
||||
cp ${RISCV}/riscv-isa-sim/arch_test_target/spike/Makefile.include addins/riscv-arch-test/
|
||||
sed -i '/export TARGETDIR ?=/c\export TARGETDIR ?= ${RISCV}/riscv-isa-sim/arch_test_target' addins/riscv-arch-test/Makefile.include
|
||||
echo export RISCV_PREFIX = riscv64-unknown-elf- >> addins/riscv-arch-test/Makefile.include
|
||||
#cd tests/linux-testgen/linux-testvectors; source ./tvLinker.sh # needs to be run in local directory
|
||||
#rm tests/imperas-riscv-tests/riscv-ovpsim-plus/bin/Linux64/riscvOVPsimPlus.exe
|
||||
#ln -s ${RISCV}/imperas-riscv-tests/riscv-ovpsim-plus/bin/Linux64/riscvOVPsimPlus.exe tests/imperas-riscv-tests/riscv-ovpsim-plus/bin/Linux64/riscvOVPsimPlus.exe
|
||||
|
||||
regression:
|
||||
make -C sim
|
||||
make -C pipelined/regression
|
||||
|
||||
clean:
|
||||
make clean -C sim
|
||||
make clean -C pipelined/regression
|
||||
|
||||
|
||||
|
||||
134
README.md
134
README.md
@ -1,131 +1,33 @@
|
||||
# core-v-wally
|
||||
# riscv-wally
|
||||
Configurable RISC-V Processor
|
||||
|
||||
Wally is a 5-stage pipelined processor configurable to support all the standard RISC-V options, incluidng RV32/64, A, C, F, D, Q, M, and Zb* extensions, virtual memory, PMP, and the various privileged modes and CSRs. It provides optional caches, branch prediction, and standard RISC-V peripherals (CLINT, PLIC, UART, GPIO). Wally is written in SystemVerilog. It passes the RISC-V Arch Tests and boots Linux on an FPGA. Configurations range from a minimal RV32E core to a fully featured RV64GC application processor.
|
||||
Wally is a 5-stage pipelined processor configurable to support all the standard RISC-V options, incluidng RV32/64, A, C, F, D, and M extensions, FENCE.I, and the various privileged modes and CSRs. It is written in SystemVerilog. It passes the RISC-V Arch Tests and Imperas tests. As of October 2021, it boots the first 10 million instructions of Buildroot Linux.
|
||||
|
||||
|
||||
If you are new to using Linux and Github, follow the steps in the RISCV SoC Design textbook to:
|
||||
|
||||
Wally is described in an upcoming textbook, *RISC-V System-on-Chip Design*, by Harris, Stine, Thompson, and Harris. Users should follow the setup instructions below. A system administrator must install CAD tools using the directions further down.
|
||||
|
||||
# Verification
|
||||
See Chapter 2 of draft book of how to install and compile tests.
|
||||
|
||||
Wally is presently at Technology Readiness Level 4, passing the RISC-V compatibility test suite and custom tests, and booting Linux in simulation and on an FPGA. See the [Test Plan](docs/testplan.md) for details.
|
||||
|
||||
# New User Setup
|
||||
|
||||
New users may wish to do the following setup to access the server via a GUI and use a text editor.
|
||||
|
||||
Git started with Git configuration and authentication: B.1 (replace with your name and email)
|
||||
$ git config --global user.name "Ben Bitdiddle"
|
||||
$ git config --global user.email "ben_bitdiddle@wally.edu"
|
||||
$ git config --global pull.rebase false
|
||||
Optional: Download and install x2go - A.1.1
|
||||
Optional: Download and install VSCode - A.4.2
|
||||
Optional: Make sure you can log into your server via x2go and via a terminal
|
||||
Download and install x2go - A.1
|
||||
Download and install VSCode - A.4.2
|
||||
Make sure you can log into Tera acceptly via x2go and via a terminal
|
||||
Terminal on Mac, cmd on Windows, xterm on Linux
|
||||
See A.1 about ssh -Y login from a terminal
|
||||
Git started with Git configuration and authentication: B.1
|
||||
|
||||
Then clone the repo, source setup, make the tests and run regression
|
||||
|
||||
If you don't already have a Github account, create one
|
||||
In a web browser, visit https://github.com/openhwgroup/cvw
|
||||
In the upper right part of the screen, click on Fork
|
||||
Create a fork, choosing the owner as your github account and the repository as cvw.
|
||||
|
||||
On the Linux computer where you will be working, log in
|
||||
|
||||
Clone your fork of the repo and run the setup script. Change <yourgithubid> to your github id.
|
||||
Then follow Section 2.2.2 to clone the repo, source setup, make the tests and run regression
|
||||
|
||||
$ cd
|
||||
$ git clone --recurse-submodules https://github.com/<yourgithubid>/cvw
|
||||
$ cd cvw
|
||||
$ git remote add upstream https://github.com/openhwgroup/cvw
|
||||
$ export RISCV=/opt/riscv
|
||||
$ git clone --recurse-submodules https://github.com/davidharrishmc/riscv-wally
|
||||
$ cd riscv-wally
|
||||
$ source ./setup.sh
|
||||
|
||||
Add the following lines to your .bashrc or .bash_profile to run the setup script each time you log in.
|
||||
|
||||
if [ -f ~/cvw/setup.sh ]; then
|
||||
source ~/cvw/setup.sh
|
||||
fi
|
||||
|
||||
Edit setup.sh and change the following lines to point to the path and license server for your Siemens Questa and Synopsys Design Compiler installation and license server. If you only have Questa, you can still simulate but cannot run logic synthesis.
|
||||
|
||||
export MGLS_LICENSE_FILE=1717@solidworks.eng.hmc.edu # Change this to your Siemens license server
|
||||
export SNPSLMD_LICENSE_FILE=27020@zircon.eng.hmc.edu # Change this to your Synopsys license server
|
||||
export QUESTAPATH=/cad/mentor/questa_sim-2021.2_1/questasim/bin # Change this for your path to Questa
|
||||
export SNPSPATH=/cad/synopsys/SYN/bin # Change this for your path to Design Compiler
|
||||
|
||||
If the tools are not yet installed on your server, follow the Toolchain Installation instructions in the section below.
|
||||
|
||||
Build the tests and run a regression simulation with Questa to prove everything is installed. Building tests will take a while.
|
||||
|
||||
$ make
|
||||
$ cd sim
|
||||
$ cd pipelined/regression
|
||||
$ ./regression-wally (depends on having Questa installed)
|
||||
|
||||
# Toolchain Installation (Sys Admin)
|
||||
|
||||
This section describes the open source toolchain installation. The
|
||||
current version of the toolchain has been tested on Ubuntu and Red
|
||||
Hat/Rocky 8 Linux. Ubuntu works more smoothly and is recommended
|
||||
unless you have a compelling need for RedHat.
|
||||
|
||||
Ubuntu users can install the tools by running
|
||||
|
||||
$ sudo $WALLY/bin/wally-tool-chain-install.sh
|
||||
|
||||
See wally-tool-chain-install.sh for a detailed description of each component,
|
||||
or to issue the commands one at a time to install on the command line.
|
||||
## Installing EDA Tools
|
||||
|
||||
Electronic Design Automation (EDA) tools are vital to implementations of System on Chip architectures as well as validating different designs. Open-source and commercial tools exist for multiple strategies and although the one can spend a lifetime using combinations of different tools, only a small subset of tools is utilized for this text. The tools are chosen because of their ease in access as well as their repeatability for accomplishing many of the tasks utilized to design Wally. It is anticipated that additional tools may be documented later after this is text is published to improve use and access.
|
||||
|
||||
Siemens Quest is the primary tool utilized for simulating and validating Wally. For logic synthesis, you will need Synopsys Design Compiler. Questa and Design Compiler are commercial tools that require an educational or commercial license.
|
||||
|
||||
Note: Some EDA tools utilize LM_LICENSE_FILE for their environmental variable to point to their license server. Some operating systems may also utilize MGLS_LICENSE_FILE instead, therefore, it is important to read the user manual on the preferred environmental variable required to point to a user’s license file. Although there are different mechanisms to allow licenses to work, many companies commonly utilize the FlexLM (i.e., Flex-enabled) license server manager that runs off a node locked license.
|
||||
|
||||
Although most EDA tools are Linux-friendly, they tend to have issues when not installed on recommended OS flavors. Both Red Hat Enterprise Linux and SUSE Linux products typically tend to be recommended for installing commercial-based EDA tools and are recommended for utilizing complex simulation and architecture exploration. Questa can also be installed on Microsoft Windows as well as Mac OS with a Virtual Machine such as Parallels.
|
||||
|
||||
Siemens Questa
|
||||
|
||||
Siemens Questa simulates behavioral, RTL and gate-level HDL. To install Siemens Questa first go to a web browser and navigate to
|
||||
https://eda.sw.siemens.com/en-US/ic/questa/simulation/advanced-simulator/. Click Sign In and log in with your credentials and the product can easily be downloaded and installed. Some Windows-based installations also require gcc libraries that are typically provided as a compressed zip download through Siemens.
|
||||
|
||||
Synopsys Design Compiler (DC)
|
||||
|
||||
Many commercial synthesis and place and route tools require a common installer. These installers are provided by the EDA vendor and Synopsys has one called Synopsys Installer. To use Synopsys Installer, you will need to acquire a license through Synopsys that is typically Called Synopsys Common Licensing (SCL). Both the Synopsys Installer, license key file, and Design Compiler can all be downloaded through Synopsys Solvnet. First open a web browser, log into Synsopsy Solvnet, and download the installer and Design Compiler installation files. Then, install the Installer
|
||||
|
||||
$ firefox &
|
||||
Navigate to https://solvnet.synopsys.com
|
||||
Log in with your institution’s username and password
|
||||
Click on Downloads, then scroll down to Synopsys Installer
|
||||
Select the latest version (currently 5.4). Click Download Here, agree,
|
||||
Click on SynopsysInstaller_v5.4.run
|
||||
Return to downloads and also get Design Compiler (synthesis) latest version, and any others you want.
|
||||
Click on all parts and the .spf file, then click Download Files near the top
|
||||
move the SynopsysIntaller into /cad/synopsys/Installer_5.4 with 755 permission for cad,
|
||||
move other files into /cad/synopsys/downloads and work as user cad from here on
|
||||
|
||||
$ cd /cad/synopsys/installer_5.4
|
||||
$ ./SynopsysInstaller_v5.4.run
|
||||
Accept default installation directory
|
||||
$ ./installer
|
||||
Enter source path as /cad/synopsys/downloads, and installation path as /cad/synopsys
|
||||
When prompted, enter your site ID
|
||||
Follow prompts
|
||||
|
||||
Installer can be utilized in graphical or text-based modes. It is far easier to use the text-based installation tool. To install DC, navigate to the location where your downloaded DC files are and type installer. You should be prompted with questions related to where you wish to have your files installed.
|
||||
|
||||
The Synopsys Installer automatically installs all downloaded product files into a single top-level target directory. You do not need to specify the installation directory for each product. For example, if you specify /import/programs/synopsys as the target directory, your installation directory structure might look like this after installation:
|
||||
|
||||
/import/programs/synopsys/syn/S-2021.06-SP1
|
||||
|
||||
Note: Although most parts of Wally, including the software used in this chapter and Questa simulation, will work on most modern Linux platforms, as of 2022, the Synopsys CAD tools for SoC design are only supported on RedHat Enterprise Linux 7.4 or 8 or SUSE Linux Enterprise Server (SLES) 12 or 15. Moreover, the RISC-V formal specification (sail-riscv) does not build gracefully on RHEL7.
|
||||
|
||||
The Verilog simulation has been tested with Siemens Questa/ModelSim. This package is available to universities worldwide as part of the Design Verification Bundle through the Siemens Academic Partner Program members for $990/year.
|
||||
|
||||
If you want to implement your own version of the chip, your tool and license complexity rises significantly. Logic synthesis uses Synopsys Design Compiler. Placement and routing uses Cadence Innovus. Both Synopsys and Cadence offer their tools at a steep discount to their university program members, but the cost is still several thousand dollars per year. Most research universities with integrated circuit design programs have Siemens, Synopsys, and Cadence licenses. You also need a process design kit (PDK) for a specific integrated circuit technology and its libraries. The open-source Google Skywater 130 nm PDK is sufficient to synthesize the core but lacks memories. Google presently funds some fabrication runs for universities. IMEC and Muse Semiconductor offers full access to multiproject wafer fabrication on the TSMC 28 nm process including logic, I/O, and memory libraries; this involves three non-disclosure agreements. Fabrication costs on the order of $10,000 for a batch of 1 mm2 chips.
|
||||
|
||||
Startups can expect to spend more than $1 million on CAD tools to get a chip to market. Commercial CAD tools are not realistically available to individuals without a university or company connection.
|
||||
|
||||
|
||||
Add the following lines to your .bashrc or .bash_profile
|
||||
|
||||
if [ -f ~/riscv-wally/setup.sh ]; then
|
||||
source ~/riscv-wally/setup.sh
|
||||
fi
|
||||
|
||||
@ -1 +0,0 @@
|
||||
Subproject commit af0c6f8cb62f48ee43e74c21e799102e03951ce2
|
||||
1
addins/imperas-riscv-tests
Symbolic link
1
addins/imperas-riscv-tests
Symbolic link
@ -0,0 +1 @@
|
||||
/opt/riscv/imperas-riscv-tests/
|
||||
@ -1 +1 @@
|
||||
Subproject commit 873d16e748ad60023dcdda3926144957c096e31d
|
||||
Subproject commit e5020bf7b345f8efb96c6c939de3162525b7f545
|
||||
@ -1,6 +1,5 @@
|
||||
# Wally Coremark Makefile
|
||||
# Daniel Torres & David Harris 28 July 2022
|
||||
# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
|
||||
PORT_DIR = $(CURDIR)/riscv64-baremetal
|
||||
cmbase=../../addins/coremark
|
||||
@ -22,10 +21,8 @@ PORT_CFLAGS = -g -mabi=$(ABI) -march=$(ARCH) -static -falign-functions=16 \
|
||||
all: $(work_dir)/coremark.bare.riscv.elf.memfile
|
||||
|
||||
run:
|
||||
(cd ../../sim && (time vsim -c -do "do wally-batch.do rv$(XLEN)gc coremark" 2>&1 | tee $(work_dir)/coremark.sim.log))
|
||||
cd ../benchmarks/coremark/
|
||||
# KMG: added post processing script to give out branch miss proportion along with other stats to the coremark test
|
||||
python3 coremark-postprocess.py
|
||||
(cd ../../pipelined/regression && (time vsim -c -do "do wally-pipelined-batch.do rv$(XLEN)gc coremark" 2>&1 | tee $(work_dir)/coremark.sim.log))
|
||||
cd ../../benchmarks/coremark/
|
||||
|
||||
$(work_dir)/coremark.bare.riscv.elf.memfile: $(work_dir)/coremark.bare.riscv
|
||||
riscv64-unknown-elf-objdump -D $< > $<.elf.objdump
|
||||
|
||||
@ -1,58 +0,0 @@
|
||||
#!/usr/bin/env python
|
||||
#########################################################
|
||||
#
|
||||
# coremark postprocessing script
|
||||
#
|
||||
# Author: Kip Macsai-Goren <kmacsaigoren@g.hmc.edu>
|
||||
#
|
||||
# Created 2022-09-25
|
||||
#
|
||||
# Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
||||
#
|
||||
# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
##################################################
|
||||
|
||||
logFile = "../../benchmarks/coremark/work/coremark.sim.log"
|
||||
|
||||
with open(logFile, "r") as logRead:
|
||||
logLines = logRead.readlines()
|
||||
|
||||
for lineNum in range(len(logLines)):
|
||||
contents = logLines[lineNum].lower().split()
|
||||
if "branches" in contents and "miss" in contents:
|
||||
branchMisses = int(contents[-1])
|
||||
elif "branches" in contents:
|
||||
branchesTot = int(contents[-1])
|
||||
branchLineNum = lineNum + 2
|
||||
|
||||
if "d-cache" in contents and "misses" in contents:
|
||||
dCacheMisses = int(contents[-1])
|
||||
elif "d-cache" in contents:
|
||||
dCacheAccess = int(contents[-1])
|
||||
dCacheLineNum = lineNum + 2
|
||||
|
||||
if "i-cache" in contents and "misses" in contents:
|
||||
ICacheMisses = int(contents[-1])
|
||||
elif "i-cache" in contents:
|
||||
ICacheAccess = int(contents[-1])
|
||||
ICacheLineNum = lineNum + 2
|
||||
|
||||
# need to add the number of previously added lines to the line number so that they stay in the intedned order.
|
||||
logLines.insert(dCacheLineNum, "# D-cache Hits " + str(dCacheAccess - dCacheMisses) + "\n")
|
||||
logLines.insert(dCacheLineNum+1, "# D-cache Miss Rate " + str(dCacheMisses / dCacheAccess) + "\n")
|
||||
logLines.insert(dCacheLineNum+2, "# D-cache Hit Rate " + str((dCacheAccess - dCacheMisses) / dCacheAccess) + "\n")
|
||||
|
||||
logLines.insert(ICacheLineNum+3, "# I-cache Hits " + str(ICacheAccess - ICacheMisses) + "\n")
|
||||
logLines.insert(ICacheLineNum+4, "# I-cache Miss Rate " + str(ICacheMisses / ICacheAccess) + "\n")
|
||||
logLines.insert(ICacheLineNum+5, "# I-cache Hit Rate " + str((ICacheAccess - ICacheMisses) / ICacheAccess) + "\n")
|
||||
|
||||
logLines.insert(branchLineNum+6, "# Branches Miss/Total ratio " + str(branchMisses / branchesTot) + "\n")
|
||||
|
||||
|
||||
with open(logFile, "w") as logWrite:
|
||||
logWrite.writelines(logLines)
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
@ -164,15 +164,11 @@ void _init(int cid, int nc)
|
||||
counters[9] = read_csr(mhpmcounter9) - counters[9];
|
||||
counters[10] = read_csr(mhpmcounter10) - counters[10];
|
||||
counters[11] = read_csr(mhpmcounter11) - counters[11];
|
||||
counters[12] = read_csr(mhpmcounter12) - counters[12];
|
||||
counters[13] = read_csr(mhpmcounter13) - counters[13];
|
||||
counters[14] = read_csr(mhpmcounter14) - counters[14];
|
||||
counters[12] = read_csr(mhpmcounter12) - counters[12];
|
||||
|
||||
ee_printf("Load Stalls %d\n", counters[3]);
|
||||
ee_printf("D-Cache Accesses %d\n", counters[11]);
|
||||
ee_printf("D-Cache Misses %d\n", counters[12]);
|
||||
ee_printf("I-Cache Accesses %d\n", counters[13]);
|
||||
ee_printf("I-Cache Misses %d\n", counters[14]);
|
||||
ee_printf("D-Cache Misses %d\n", counters[12]);
|
||||
ee_printf("Branches %d\n", counters[5]);
|
||||
ee_printf("Branches Miss Predictions %d\n", counters[4]);
|
||||
ee_printf("BTB Misses %d\n", counters[6]);
|
||||
|
||||
@ -34,7 +34,7 @@ sim: modelsim_build_memfile modelsim_run speed
|
||||
|
||||
# launches modelsim to simulate tests on wally
|
||||
modelsim_run:
|
||||
(cd ../../sim/ && vsim -c -do "do wally-batch.do rv32gc embench")
|
||||
(cd ../../pipelined/regression/ && vsim -c -do "do wally-pipelined-batch.do rv32gc embench")
|
||||
cd ../../benchmarks/embench/
|
||||
|
||||
# builds the objdump based on the compiled c elf files
|
||||
|
||||
@ -1,7 +1,4 @@
|
||||
#!/usr/bin/env python
|
||||
# Daniel Torres 2022
|
||||
# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
|
||||
import subprocess
|
||||
import sys
|
||||
import json
|
||||
|
||||
@ -1,57 +0,0 @@
|
||||
#!/bin/bash
|
||||
|
||||
###########################################
|
||||
## Written: ross1728@gmail.com
|
||||
## Created: 12 March 2023
|
||||
## Modified:
|
||||
##
|
||||
## Purpose: Takes a directory of branch outcomes organized as 1 files per benchmark.
|
||||
## Computes the geometric mean.
|
||||
##
|
||||
## A component of the CORE-V-WALLY configurable RISC-V project.
|
||||
##
|
||||
## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
|
||||
##
|
||||
## SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
##
|
||||
## Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||
## except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||
## may obtain a copy of the License at
|
||||
##
|
||||
## https:##solderpad.org/licenses/SHL-2.1/
|
||||
##
|
||||
## Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||
## License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||
## either express or implied. See the License for the specific language governing permissions
|
||||
## and limitations under the License.
|
||||
################################################################################################
|
||||
|
||||
|
||||
Directory="$1"
|
||||
Files="$1/*.log"
|
||||
|
||||
for Pred in "bimodal" "gshare"
|
||||
do
|
||||
for Size in $(seq 6 2 16)
|
||||
do
|
||||
if [ $Pred = "gshare" ]; then
|
||||
SizeString="$Size $Size 18 1"
|
||||
elif [ $Pred = "bimodal" ]; then
|
||||
SizeString="$Size 18 1"
|
||||
fi
|
||||
|
||||
Product=1.0
|
||||
Count=0
|
||||
for File in $Files
|
||||
do
|
||||
#echo "sim_bp $Pred $Size $Size 18 1 $File | tail -1 | awk '{print $4}'"
|
||||
#echo "sim_bp $Pred $SizeString $File | tail -1 | awk '{print $4}'"
|
||||
BMDR=`sim_bp $Pred $SizeString $File | tail -1 | awk '{print $4}'`
|
||||
Product=`echo "$Product * $BMDR" | bc`
|
||||
Count=$((Count+1))
|
||||
done
|
||||
|
||||
GeoMean=`perl -E "say $Product**(1/$Count)"`
|
||||
echo "$Pred$Size $GeoMean"
|
||||
done
|
||||
done
|
||||
283
bin/CacheSim.py
283
bin/CacheSim.py
@ -1,283 +0,0 @@
|
||||
#!/usr/bin/env python3
|
||||
|
||||
###########################################
|
||||
## CacheSim.py
|
||||
##
|
||||
## Written: lserafini@hmc.edu
|
||||
## Created: 27 March 2023
|
||||
## Modified: 12 April 2023
|
||||
##
|
||||
## Purpose: Simulate a L1 D$ or I$ for comparison with Wally
|
||||
##
|
||||
## A component of the CORE-V-WALLY configurable RISC-V project.
|
||||
##
|
||||
## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
|
||||
##
|
||||
## SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
##
|
||||
## Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||
## except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||
## may obtain a copy of the License at
|
||||
##
|
||||
## https:##solderpad.org/licenses/SHL-2.1/
|
||||
##
|
||||
## Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||
## License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||
## either express or implied. See the License for the specific language governing permissions
|
||||
## and limitations under the License.
|
||||
################################################################################################
|
||||
|
||||
# how to invoke this simulator:
|
||||
# CacheSim.py <number of lines> <number of ways> <length of physical address> <length of tag> -f <log file> (-v)
|
||||
# so the default invocation for rv64gc is 'CacheSim.py 64 4 56 44 -f <log file>'
|
||||
# the log files to run this simulator on can be generated from testbench.sv
|
||||
# by setting I_CACHE_ADDR_LOGGER and/or D_CACHE_ADDR_LOGGER to 1 before running tests.
|
||||
# I (Lim) recommend logging a single set of tests (such as wally64priv) at a time.
|
||||
# This helps avoid unexpected logger behavior.
|
||||
# With verbose mode off, the simulator only reports mismatches between its and Wally's behavior.
|
||||
# With verbose mode on, the simulator logs each access into the cache.
|
||||
# Add -p or --perf to report the hit/miss ratio.
|
||||
# Add -d or --dist to report the distribution of loads, stores, and atomic ops.
|
||||
# These distributions may not add up to 100; this is because of flushes or invalidations.
|
||||
|
||||
import sys
|
||||
import math
|
||||
import argparse
|
||||
import os
|
||||
|
||||
class CacheLine:
|
||||
def __init__(self):
|
||||
self.tag = 0
|
||||
self.valid = False
|
||||
self.dirty = False
|
||||
|
||||
def __str__(self):
|
||||
string = "(V: " + str(self.valid) + ", D: " + str(self.dirty)
|
||||
string += ", Tag: " + str(hex(self.tag)) + ")"
|
||||
return string
|
||||
|
||||
def __repr__(self):
|
||||
return self.__str__()
|
||||
|
||||
class Cache:
|
||||
def __init__(self, numsets, numways, addrlen, taglen):
|
||||
self.numways = numways
|
||||
self.numsets = numsets
|
||||
|
||||
self.addrlen = addrlen
|
||||
self.taglen = taglen
|
||||
self.setlen = int(math.log(numsets, 2))
|
||||
self.offsetlen = self.addrlen - self.taglen - self.setlen
|
||||
|
||||
self.ways = []
|
||||
for i in range(numways):
|
||||
self.ways.append([])
|
||||
for j in range(numsets):
|
||||
self.ways[i].append(CacheLine())
|
||||
|
||||
self.pLRU = []
|
||||
for i in range(self.numsets):
|
||||
self.pLRU.append([0]*(self.numways-1))
|
||||
|
||||
# flushes the cache by setting all dirty bits to False
|
||||
def flush(self):
|
||||
for way in self.ways:
|
||||
for line in way:
|
||||
line.dirty = False
|
||||
|
||||
# invalidates the cache by setting all valid bits to False
|
||||
def invalidate(self):
|
||||
for way in self.ways:
|
||||
for line in way:
|
||||
line.valid = False
|
||||
|
||||
# resets the pLRU to a fresh 2-D array of 0s
|
||||
def clear_pLRU(self):
|
||||
self.pLRU = []
|
||||
for i in range(self.numsets):
|
||||
self.pLRU.append([0]*(self.numways-1))
|
||||
|
||||
# splits the given address into tag, set, and offset
|
||||
def splitaddr(self, addr):
|
||||
# no need for offset in the sim, but it's here for debug
|
||||
tag = addr >> (self.setlen + self.offsetlen) & int('1'*self.taglen, 2)
|
||||
setnum = (addr >> self.offsetlen) & int('1'*self.setlen, 2)
|
||||
offset = addr & int('1'*self.offsetlen, 2)
|
||||
return tag, setnum, offset
|
||||
|
||||
# performs a cache access with the given address.
|
||||
# returns a character representing the outcome:
|
||||
# H/M/E/D - hit, miss, eviction, or eviction with writeback
|
||||
def cacheaccess(self, addr, write=False):
|
||||
tag, setnum, _ = self.splitaddr(addr)
|
||||
|
||||
# check our ways to see if we have a hit
|
||||
for waynum in range(self.numways):
|
||||
line = self.ways[waynum][setnum]
|
||||
if line.tag == tag and line.valid:
|
||||
line.dirty = line.dirty or write
|
||||
self.update_pLRU(waynum, setnum)
|
||||
return 'H'
|
||||
|
||||
# we didn't hit, but we may not need to evict.
|
||||
# check for an empty way line.
|
||||
for waynum in range(self.numways):
|
||||
line = self.ways[waynum][setnum]
|
||||
if not line.valid:
|
||||
line.tag = tag
|
||||
line.valid = True
|
||||
line.dirty = write
|
||||
self.update_pLRU(waynum, setnum)
|
||||
return 'M'
|
||||
|
||||
# we need to evict. Select a victim and overwrite.
|
||||
victim = self.getvictimway(setnum)
|
||||
line = self.ways[victim][setnum]
|
||||
prevdirty = line.dirty
|
||||
line.tag = tag
|
||||
line.valid = True # technically redundant
|
||||
line.dirty = write
|
||||
self.update_pLRU(victim, setnum)
|
||||
return 'D' if prevdirty else 'E'
|
||||
|
||||
# updates the psuedo-LRU tree for the given set
|
||||
# with an access to the given way
|
||||
def update_pLRU(self, waynum, setnum):
|
||||
if self.numways == 1:
|
||||
return
|
||||
|
||||
tree = self.pLRU[setnum]
|
||||
bottomrow = (self.numways - 1)//2
|
||||
index = (waynum // 2) + bottomrow
|
||||
tree[index] = int(not (waynum % 2))
|
||||
while index > 0:
|
||||
parent = (index-1) // 2
|
||||
tree[parent] = index % 2
|
||||
index = parent
|
||||
|
||||
# uses the psuedo-LRU tree to select
|
||||
# a victim way from the given set
|
||||
# returns the victim way as an integer
|
||||
def getvictimway(self, setnum):
|
||||
if self.numways == 1:
|
||||
return 0
|
||||
|
||||
tree = self.pLRU[setnum]
|
||||
index = 0
|
||||
bottomrow = (self.numways - 1) // 2 #first index on the bottom row of the tree
|
||||
while index < bottomrow:
|
||||
if tree[index] == 0:
|
||||
# Go to the left child
|
||||
index = index*2 + 1
|
||||
else: #tree[index] == 1
|
||||
# Go to the right child
|
||||
index = index*2 + 2
|
||||
|
||||
victim = (index - bottomrow)*2
|
||||
if tree[index] == 1:
|
||||
victim += 1
|
||||
|
||||
return victim
|
||||
|
||||
def __str__(self):
|
||||
string = ""
|
||||
for i in range(self.numways):
|
||||
string += "Way " + str(i) + ": "
|
||||
for line in self.ways[i]:
|
||||
string += str(line) + ", "
|
||||
string += "\n\n"
|
||||
return string
|
||||
|
||||
def __repr__(self):
|
||||
return self.__str__()
|
||||
|
||||
|
||||
if __name__ == "__main__":
|
||||
parser = argparse.ArgumentParser(description="Simulates a L1 cache.")
|
||||
parser.add_argument('numlines', type=int, help="The number of lines per way (a power of 2)", metavar="L")
|
||||
parser.add_argument('numways', type=int, help="The number of ways (a power of 2)", metavar='W')
|
||||
parser.add_argument('addrlen', type=int, help="Length of the address in bits (a power of 2)", metavar="A")
|
||||
parser.add_argument('taglen', type=int, help="Length of the tag in bits", metavar="T")
|
||||
parser.add_argument('-f', "--file", required=True, help="Log file to simulate from")
|
||||
parser.add_argument('-v', "--verbose", action='store_true', help="verbose/full-trace mode")
|
||||
parser.add_argument('-p', "--perf", action='store_true', help="Report hit/miss ratio")
|
||||
parser.add_argument('-d', "--dist", action='store_true', help="Report distribution of operations")
|
||||
|
||||
args = parser.parse_args()
|
||||
cache = Cache(args.numlines, args.numways, args.addrlen, args.taglen)
|
||||
extfile = os.path.expanduser(args.file)
|
||||
nofails = True
|
||||
|
||||
if args.perf:
|
||||
hits = 0
|
||||
misses = 0
|
||||
|
||||
if args.dist:
|
||||
loads = 0
|
||||
stores = 0
|
||||
atoms = 0
|
||||
totalops = 0
|
||||
|
||||
with open(extfile, "r") as f:
|
||||
for ln in f:
|
||||
ln = ln.strip()
|
||||
lninfo = ln.split()
|
||||
if len(lninfo) < 3: #non-address line
|
||||
if len(lninfo) > 0 and (lninfo[0] == 'BEGIN' or lninfo[0] == 'TRAIN'):
|
||||
# currently BEGIN and END traces aren't being recorded correctly
|
||||
# trying TRAIN clears instead
|
||||
cache.invalidate() # a new test is starting, so 'empty' the cache
|
||||
cache.clear_pLRU()
|
||||
if args.verbose:
|
||||
print("New Test")
|
||||
|
||||
else:
|
||||
if args.dist:
|
||||
totalops += 1
|
||||
|
||||
if lninfo[1] == 'F':
|
||||
cache.flush()
|
||||
if args.verbose:
|
||||
print("F")
|
||||
elif lninfo[1] == 'I':
|
||||
cache.invalidate()
|
||||
if args.verbose:
|
||||
print("I")
|
||||
else:
|
||||
addr = int(lninfo[0], 16)
|
||||
iswrite = lninfo[1] == 'W' or lninfo[1] == 'A'
|
||||
result = cache.cacheaccess(addr, iswrite)
|
||||
|
||||
if args.verbose:
|
||||
tag, setnum, offset = cache.splitaddr(addr)
|
||||
print(hex(addr), hex(tag), hex(setnum), hex(offset), lninfo[2], result)
|
||||
|
||||
if args.perf:
|
||||
if result == 'H':
|
||||
hits += 1
|
||||
else:
|
||||
misses += 1
|
||||
|
||||
if args.dist:
|
||||
if lninfo[1] == 'R':
|
||||
loads += 1
|
||||
elif lninfo[1] == 'W':
|
||||
stores += 1
|
||||
elif lninfo[1] == 'A':
|
||||
atoms += 1
|
||||
|
||||
if not result == lninfo[2]:
|
||||
print("Result mismatch at address", lninfo[0]+ ". Wally:", lninfo[2]+", Sim:", result)
|
||||
nofails = False
|
||||
if args.dist:
|
||||
percent_loads = str(round(100*loads/totalops))
|
||||
percent_stores = str(round(100*stores/totalops))
|
||||
percent_atoms = str(round(100*atoms/totalops))
|
||||
print("This log had", percent_loads+"% loads,", percent_stores+"% stores, and", percent_atoms+"% atomic operations.")
|
||||
|
||||
if args.perf:
|
||||
ratio = round(hits/misses,3)
|
||||
print("There were", hits, "hits and", misses, "misses. The hit/miss ratio was", str(ratio)+".")
|
||||
|
||||
if nofails:
|
||||
print("SUCCESS! There were no mismatches between Wally and the sim.")
|
||||
@ -1,52 +0,0 @@
|
||||
#!/bin/bash
|
||||
|
||||
###########################################
|
||||
## Written: ross1728@gmail.com
|
||||
## Created: 12 March 2023
|
||||
## Modified:
|
||||
##
|
||||
## Purpose: Converts a single branch.log containing multiple benchmark branch outcomes into
|
||||
## separate files, one for each program.x4
|
||||
##
|
||||
## A component of the CORE-V-WALLY configurable RISC-V project.
|
||||
##
|
||||
## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
|
||||
##
|
||||
## SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
##
|
||||
## Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||
## except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||
## may obtain a copy of the License at
|
||||
##
|
||||
## https:##solderpad.org/licenses/SHL-2.1/
|
||||
##
|
||||
## Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||
## License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||
## either express or implied. See the License for the specific language governing permissions
|
||||
## and limitations under the License.
|
||||
################################################################################################
|
||||
|
||||
File="$1"
|
||||
TrainLineNumbers=`cat $File | grep -n "TRAIN" | awk -NF ':' '{print $1}'`
|
||||
BeginLineNumbers=`cat $File | grep -n "BEGIN" | awk -NF ':' '{print $1}'`
|
||||
Name=`cat $File | grep -n "BEGIN" | awk -NF '/' '{print $6_$4}'`
|
||||
EndLineNumbers=`cat $File | grep -n "END" | awk -NF ':' '{print $1}'`
|
||||
echo $Name
|
||||
echo $BeginLineNumbers
|
||||
echo $EndLineNumbers
|
||||
|
||||
NameArray=($Name)
|
||||
TrainLineNumberArray=($TrainLineNumbers)
|
||||
BeginLineNumberArray=($BeginLineNumbers)
|
||||
EndLineNumberArray=($EndLineNumbers)
|
||||
|
||||
mkdir -p branch
|
||||
Length=${#EndLineNumberArray[@]}
|
||||
for i in $(seq 0 1 $((Length-1)))
|
||||
do
|
||||
CurrName=${NameArray[$i]}
|
||||
CurrTrain=$((${TrainLineNumberArray[$i]}+1))
|
||||
CurrEnd=$((${EndLineNumberArray[$i]}-1))
|
||||
echo $CurrName, $CurrTrain, $CurrEnd
|
||||
sed -n "${CurrTrain},${CurrEnd}p" $File > branch/${CurrName}_branch.log
|
||||
done
|
||||
@ -1,30 +1,8 @@
|
||||
#!/bin/bash
|
||||
|
||||
###########################################
|
||||
## Written: james.stine@okstate.edu
|
||||
## Created: 4 Jan 2022
|
||||
## Modified:
|
||||
##
|
||||
## Purpose: Script to run elf2hex for memfile for
|
||||
## Imperas and riscv-arch-test benchmarks
|
||||
##
|
||||
## A component of the CORE-V-WALLY configurable RISC-V project.
|
||||
##
|
||||
## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
|
||||
##
|
||||
## SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
##
|
||||
## Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||
## except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||
## may obtain a copy of the License at
|
||||
##
|
||||
## https:##solderpad.org/licenses/SHL-2.1/
|
||||
##
|
||||
## Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||
## License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||
## either express or implied. See the License for the specific language governing permissions
|
||||
## and limitations under the License.
|
||||
################################################################################################
|
||||
# james.stine@okstate.edu 4 Jan 2022
|
||||
# Script to run elf2hex for memfile for
|
||||
# Imperas and riscv-arch-test benchmarks
|
||||
|
||||
for file in work/rv64i_m/*/*.elf ; do
|
||||
memfile=${file%.elf}.elf.memfile
|
||||
|
||||
@ -1,35 +1,9 @@
|
||||
#!/usr/bin/perl -w
|
||||
|
||||
###########################################
|
||||
## exe2memfile.pl
|
||||
##
|
||||
## Written: David_Harris@hmc.edu
|
||||
## Created: 26 November 2020
|
||||
## Modified:
|
||||
##
|
||||
## Purpose: Converts an executable file to a series of 32-bit hex instructions
|
||||
## to read into a Verilog simulation with $readmemh
|
||||
##
|
||||
## A component of the CORE-V-WALLY configurable RISC-V project.
|
||||
##
|
||||
## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
|
||||
##
|
||||
## SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
##
|
||||
## Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||
## except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||
## may obtain a copy of the License at
|
||||
##
|
||||
## https:##solderpad.org/licenses/SHL-2.1/
|
||||
##
|
||||
## Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||
## License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||
## either express or implied. See the License for the specific language governing permissions
|
||||
## and limitations under the License.
|
||||
################################################################################################
|
||||
|
||||
#
|
||||
#
|
||||
# exe2memfile.pl
|
||||
# David_Harris@hmc.edu 26 November 2020
|
||||
# Converts an executable file to a series of 32-bit hex instructions
|
||||
# to read into a Verilog simulation with $readmemh
|
||||
|
||||
use File::stat;
|
||||
use IO::Handle;
|
||||
@ -193,4 +167,4 @@ sub fixadr {
|
||||
my $adr = shift;
|
||||
if ($adr =~ s/^8/0/) { return hex($adr); }
|
||||
else { die("address $adr lacks leading 8\n"); }
|
||||
}
|
||||
}
|
||||
@ -1,33 +1,34 @@
|
||||
#!/bin/bash
|
||||
|
||||
######################
|
||||
## extractFunctionRadix.sh
|
||||
##
|
||||
## Written: Ross Thompson
|
||||
## email: ross1728@gmail.com
|
||||
## Created: March 1, 2021
|
||||
## Modified: March 10, 2021
|
||||
##
|
||||
## Purpose: Processes all compiled object files into 2 types of files which assist in debuging applications.
|
||||
## File 1: .addr: A sorted list of function starting addresses.
|
||||
## When a the PCE is greater than or equal to the function's starting address, the label will be associated with this address.
|
||||
## File 2: .lab: A sorted list of funciton labels. The names of functions. Modelsim will display these names rather than the function address.
|
||||
##
|
||||
## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
|
||||
##
|
||||
## SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
##
|
||||
## Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||
## except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||
## may obtain a copy of the License at
|
||||
##
|
||||
## https:##solderpad.org/licenses/SHL-2.1/
|
||||
##
|
||||
## Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||
## License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||
## either express or implied. See the License for the specific language governing permissions
|
||||
## and limitations under the License.
|
||||
################################################################################################
|
||||
# extractFunctionRadix.sh
|
||||
#
|
||||
# Written: Ross Thompson
|
||||
# email: ross1728@gmail.com
|
||||
# Created: March 1, 2021
|
||||
# Modified: March 10, 2021
|
||||
#
|
||||
# Purpose: Processes all compiled object files into 2 types of files which assist in debuging applications.
|
||||
# File 1: .addr: A sorted list of function starting addresses.
|
||||
# When a the PCE is greater than or equal to the function's starting address, the label will be associated with this address.
|
||||
# File 2: .lab: A sorted list of funciton labels. The names of functions. Modelsim will display these names rather than the function address.
|
||||
#
|
||||
# A component of the Wally configurable RISC-V project.
|
||||
#
|
||||
# Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
||||
#
|
||||
# Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
|
||||
# files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
|
||||
# modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
|
||||
# is furnished to do so, subject to the following conditions:
|
||||
#
|
||||
# The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
|
||||
#
|
||||
# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
# OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
|
||||
# BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
|
||||
# OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
######################
|
||||
|
||||
|
||||
function processProgram {
|
||||
|
||||
@ -1,54 +0,0 @@
|
||||
#!/bin/bash
|
||||
###########################################
|
||||
## imperas-one-time.sh
|
||||
##
|
||||
## Written: Ross Thompson (ross1728@gmail.com) and Lee Moore (moore@imperas.com)
|
||||
## Created: 31 January 2023
|
||||
## Modified: 31 January 2023
|
||||
##
|
||||
## Purpose: One time setup script for running imperas.
|
||||
##
|
||||
## A component of the CORE-V-WALLY configurable RISC-V project.
|
||||
##
|
||||
## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
|
||||
##
|
||||
## SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
##
|
||||
## Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||
## except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||
## may obtain a copy of the License at
|
||||
##
|
||||
## https://solderpad.org/licenses/SHL-2.1/
|
||||
##
|
||||
## Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||
## License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||
## either express or implied. See the License for the specific language governing permissions
|
||||
## and limitations under the License.
|
||||
################################################################################################
|
||||
|
||||
|
||||
IMP_HASH=355a055ff7e36bc897e942e41f06e1baf96e34d5
|
||||
|
||||
# clone the Imperas repo
|
||||
cd $WALY
|
||||
if [ ! -d external ]; then
|
||||
mkdir -p external
|
||||
fi
|
||||
pushd external
|
||||
if [ ! -d ImperasDV-HMC ]; then
|
||||
git clone git@github.com:Imperas/ImperasDV-HMC.git
|
||||
fi
|
||||
pushd ImperasDV-HMC
|
||||
git checkout $IMP_HASH
|
||||
popd
|
||||
popd
|
||||
|
||||
# Setup Imperas
|
||||
source ${WALLY}/external/ImperasDV-HMC/Imperas/bin/setup.sh
|
||||
setupImperas ${WALLY}/external/ImperasDV-HMC/Imperas
|
||||
export IMPERAS_PERSONALITY=CPUMAN_DV_ASYNC
|
||||
|
||||
# setup QUESTA (Imperas only command, YMMV)
|
||||
#svsetup -questa
|
||||
|
||||
|
||||
246
bin/libppa.pl
246
bin/libppa.pl
@ -1,246 +0,0 @@
|
||||
#!/bin/perl -W
|
||||
|
||||
###########################################
|
||||
## libppa.pl
|
||||
##
|
||||
## Written: David_Harris@hmc.edu
|
||||
## Created: 28 January 2023
|
||||
##
|
||||
## Purpose: Extract PPA information from Liberty files
|
||||
## presently characterizes Skywater 90 and TSMC28hpc+
|
||||
##
|
||||
## The user will need to change $libpath to point to the desired library in your local installation
|
||||
## and for TSMC change the $cellname to the actual name of the inverter.
|
||||
##
|
||||
## A component of the CORE-V-WALLY configurable RISC-V project.
|
||||
##
|
||||
## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
|
||||
##
|
||||
## SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
##
|
||||
## Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||
## except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||
## may obtain a copy of the License at
|
||||
##
|
||||
## https:##solderpad.org/licenses/SHL-2.1/
|
||||
##
|
||||
## Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||
## License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||
## either express or implied. See the License for the specific language governing permissions
|
||||
## and limitations under the License.
|
||||
################################################################################################
|
||||
|
||||
use strict;
|
||||
use warnings;
|
||||
|
||||
# global variables for simplicity
|
||||
my @index1; my @index2;
|
||||
my @values;
|
||||
my @cr; my @cf; my @rt; my @ft;
|
||||
|
||||
# cell and corners to analyze
|
||||
my $libpath; my $libbase; my $cellname; my @corners;
|
||||
|
||||
# Sky90
|
||||
$libpath ="/opt/riscv/cad/lib/sky90/sky90_sc/V1.7.4/lib";
|
||||
$libbase = "scc9gena_";
|
||||
$cellname = "scc9gena_inv_1";
|
||||
@corners = ("tt_1.2v_25C", "tt_1.08v_25C", "tt_1.32v_25C", "tt_1.2v_-40C", "tt_1.2v_85C", "tt_1.2v_125C", "ss_1.2v_25C", "ss_1.08v_-40C", "ss_1.08v_25C", "ss_1.08v_125C", "ff_1.2v_25C", "ff_1.32v_-40C", "ff_1.32v_25C", "ff_1.32v_125C");
|
||||
printf("Library $libbase Cell $cellname\n");
|
||||
foreach my $corner (@corners) {
|
||||
&analyzeCell($corner);
|
||||
}
|
||||
|
||||
# TSMC
|
||||
$libpath = "/proj/models/tsmc28/libraries/28nmtsmc/tcbn28hpcplusbwp30p140_190a/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tcbn28hpcplusbwp30p140_180a";
|
||||
$libbase = "tcbn28hpcplusbwp30p140";
|
||||
$cellname = "INVD1..."; // replace this with the full name of the library cell
|
||||
@corners = ("tt0p9v25c", "tt0p8v25c", "tt1v25c", "tt0p9v85c", "ssg0p9vm40c", "ssg0p9v125c", "ssg0p81vm40c", "ssg0p81v125c", "ffg0p88vm40c", "ffg0p88v125c", "ffg0p99vm40c", "ffg0p99v125c");
|
||||
printf("\nLibrary $libbase Cell $cellname\n");
|
||||
foreach my $corner (@corners) {
|
||||
&analyzeCell($corner);
|
||||
}
|
||||
|
||||
#############
|
||||
# subroutines
|
||||
#############
|
||||
|
||||
sub analyzeCell {
|
||||
my $corner = shift;
|
||||
my $fname = $libpath."/".$libbase.$corner.".lib";
|
||||
open (FILE, $fname) || die("Can't read $fname");
|
||||
my $incell = 0;
|
||||
my $inleakage = 0;
|
||||
my $inpin = 0;
|
||||
my $incellrise = 0;
|
||||
my $incellfall = 0;
|
||||
my $inrisetrans = 0;
|
||||
my $infalltrans = 0;
|
||||
my $inindex = 0;
|
||||
my $invalues = 0;
|
||||
my $searchstring = "cell (".$cellname.")";
|
||||
my $area; my $leakage; my $cap;
|
||||
while (<FILE>) {
|
||||
if (index($_, $searchstring) != -1) { $incell = 1;}
|
||||
elsif ($incell) {
|
||||
if (/cell \(/) {
|
||||
$incell = 0;
|
||||
close(FILE);
|
||||
last;
|
||||
}
|
||||
if (/area\s*:\s*(.*);/) { $area = $1; }
|
||||
if (/cell_leakage_power\s*:\s*(.*);/) { $leakage = $1; $inleakage = 2; }
|
||||
if ($inleakage == 0 && /leakage_power/) { $inleakage = 1; }
|
||||
if ($inleakage == 1 && /value\s*:\s*(.*);/) {
|
||||
$leakage = $1;
|
||||
$inleakage = 2;
|
||||
}
|
||||
if ($inpin == 0 && /pin/) { $inpin = 1; }
|
||||
if ($inpin == 1 && /\s+capacitance\s*:\s*(.*);/) {
|
||||
$cap = $1;
|
||||
$inpin = 2;
|
||||
}
|
||||
if ($inindex == 0 && /index_1/) { $inindex = 1; }
|
||||
if ($inindex == 1) {
|
||||
if (/index_1\s*\(\"(.*)\"\);/) { @index1 = split(/, /, $1); }
|
||||
if (/index_2\s*\(\"(.*)\"\);/) { @index2 = split(/, /, $1); $inindex = 2; }
|
||||
}
|
||||
if ($incellrise == 0 && /cell_rise/) { $incellrise = 1; $invalues = 0;}
|
||||
if ($incellfall == 0 && /cell_fall/) { $incellfall = 1; $invalues = 0; }
|
||||
if ($inrisetrans == 0 && /rise_trans/) { $inrisetrans = 1; $invalues = 0; }
|
||||
if ($infalltrans == 0 && /fall_trans/) { $infalltrans = 1; $invalues = 0; }
|
||||
if ($incellrise == 1 || $incellfall == 1 || $inrisetrans == 1 || $infalltrans == 1) {
|
||||
if (/values/) { $invalues = 1; @values = (); }
|
||||
elsif ($invalues == 1) {
|
||||
if (/\);/) {
|
||||
$invalues = 2;
|
||||
if ($incellrise == 1) { @cr = &parseVals(); $incellrise = 2; }
|
||||
if ($incellfall == 1) { @cf = &parseVals(); $incellfall = 2; }
|
||||
if ($inrisetrans == 1) { @rt = &parseVals(); $inrisetrans = 2; }
|
||||
if ($infalltrans == 1) { @ft = &parseVals(); $infalltrans = 2; }
|
||||
}
|
||||
elsif (/\"(.*)\"/) { push(@values, $1); }
|
||||
}
|
||||
}
|
||||
# print $_;
|
||||
}
|
||||
}
|
||||
|
||||
my $delay = &computeDelay($cap);
|
||||
my $cornerr = sprintf("%20s", $corner);
|
||||
my $delayr = sprintf("%2.1f", $delay*1000);
|
||||
my $leakager = sprintf("%3.1f", $leakage);
|
||||
|
||||
print("$cornerr: Delay $delayr Leakage: $leakager capacitance: $cap\n");
|
||||
#print("$cellname $corner: Area $area Leakage: $leakage capacitance: $cap delay $delay\n");
|
||||
#print(" index1: @index1\n");
|
||||
#print(" index2: @index2\n");
|
||||
#print("Cell Rise\n"); printMatrix(\@cr);
|
||||
#print("Cell Fall\n"); printMatrix(\@cf);
|
||||
#print("Rise Trans\n"); printMatrix(\@rt);
|
||||
#print("Fall Trans\n"); printMatrix(\@ft);
|
||||
}
|
||||
|
||||
sub computeDelay {
|
||||
# relies on cr, cf, rt, ft, index1, index2
|
||||
# index1 for rows of matrix (different trans times, units of ns)
|
||||
# index2 for cols of matrix (different load capacitances, units of pF)
|
||||
|
||||
# first, given true load, create a rise/fall delay and transition
|
||||
# as a function of trans time, interpolated
|
||||
my $cap = shift;
|
||||
my $fo4cap = 4*$cap;
|
||||
my @cri = &interp2(\@cr, $fo4cap);
|
||||
my @cfi = &interp2(\@cf, $fo4cap);
|
||||
my @rti = &interp2(\@rt, $fo4cap);
|
||||
my @fti = &interp2(\@ft, $fo4cap);
|
||||
|
||||
# initially guess second smallest transition time
|
||||
my $tt = $index1[1];
|
||||
# assume falling input with this transition, compute rise delay & trans
|
||||
my $cr0 = &interp1(\@cri, \@index1, $tt);
|
||||
my $rt0 = &interp1(\@rti, \@index1, $tt);
|
||||
# now assuming rising input with rt0, compute fall delay & trans
|
||||
my $cf1 = &interp1(\@cfi, \@index1, $rt0);
|
||||
my $ft1 = &interp1(\@fti, \@index1, $rt0);
|
||||
# now assuming falling input with ft1, compute rise delay & trans
|
||||
my $cr2 = &interp1(\@cri, \@index1, $ft1);
|
||||
my $rt2 = &interp1(\@rti, \@index1, $ft1);
|
||||
# now assuming rising input with rt2, compute fall delay & trans
|
||||
my $cf3 = &interp1(\@cfi, \@index1, $rt2);
|
||||
my $ft3 = &interp1(\@fti, \@index1, $rt2);
|
||||
|
||||
# delay is average of rising and falling
|
||||
my $delay = ($cr2 + $cf3)/2;
|
||||
return $delay;
|
||||
|
||||
# print("tt $tt cr0 $cr0 rt0 $rt0\n");
|
||||
# print("cf1 $cf1 ft1 $ft1 cr2 $cr2 rt2 $rt2 cf3 $cf3 ft3 $ft3 delay $delay\n");
|
||||
}
|
||||
|
||||
sub interp2 {
|
||||
my $matref = shift;
|
||||
my @matrix = @$matref;
|
||||
my $fo4cap = shift;
|
||||
my @interp = ();
|
||||
|
||||
my $i;
|
||||
# interpolate row by row
|
||||
for ($i=0; $i <= $#index1; $i++) {
|
||||
my @row = @{$matrix[$i]};
|
||||
#print ("Extracted row $i = @row\n");
|
||||
$interp[$i] = &interp1(\@row, \@index2, $fo4cap);
|
||||
}
|
||||
return @interp;
|
||||
}
|
||||
|
||||
sub interp1 {
|
||||
my $vecref = shift;
|
||||
my @vec = @$vecref;
|
||||
my $indexref = shift;
|
||||
my @index = @$indexref;
|
||||
my $x = shift;
|
||||
|
||||
# find entry i containing the first index greater than x
|
||||
my $i = 0;
|
||||
while ($index[$i] < $x) {$i++}
|
||||
my $start = $index[$i-1];
|
||||
my $end = $index[$i];
|
||||
my $fract = ($x-$start)/($end-$start);
|
||||
my $interp = $vec[$i-1] + ($vec[$i] - $vec[$i-1])*$fract;
|
||||
|
||||
# print ("Interpolating $x as $interp from i $i start $start end $end based on index @index and vec @vec\n");
|
||||
|
||||
return $interp;
|
||||
}
|
||||
|
||||
sub parseVals {
|
||||
# relies on global variables @values, @index1, @index2
|
||||
my @vals;
|
||||
my $i; my $j;
|
||||
for ($i=0; $i <= $#index1; $i++) {
|
||||
my @row = split(/, /,$values[$i]);
|
||||
for ($j = 0; $j <= $#index2; $j++) {
|
||||
$vals[$i][$j] = $row[$j];
|
||||
}
|
||||
}
|
||||
return @vals;
|
||||
}
|
||||
|
||||
sub printMatrix {
|
||||
my $mat = shift;
|
||||
my @matrix = @$mat;
|
||||
my $i; my $j;
|
||||
for ($i=0; $i <= $#index1; $i++) {
|
||||
for ($j = 0; $j <= $#index2; $j++) {
|
||||
print($matrix[$i][$j]." ");
|
||||
}
|
||||
print("\n");
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
318
bin/parseHPMC.py
318
bin/parseHPMC.py
@ -1,318 +0,0 @@
|
||||
#!/usr/bin/python3
|
||||
|
||||
###########################################
|
||||
## Written: Ross Thompson ross1728@gmail.com
|
||||
## Created: 4 Jan 2022
|
||||
## Modified:
|
||||
##
|
||||
## Purpose: Parses the performance counters from a modelsim trace.
|
||||
##
|
||||
## A component of the CORE-V-WALLY configurable RISC-V project.
|
||||
##
|
||||
## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
|
||||
##
|
||||
## SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
##
|
||||
## Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||
## except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||
## may obtain a copy of the License at
|
||||
##
|
||||
## https:##solderpad.org/licenses/SHL-2.1/
|
||||
##
|
||||
## Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||
## License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||
## either express or implied. See the License for the specific language governing permissions
|
||||
## and limitations under the License.
|
||||
################################################################################################
|
||||
|
||||
import os
|
||||
import sys
|
||||
import matplotlib.pyplot as plt
|
||||
import re
|
||||
|
||||
#RefData={'twobitCModel' :(['6', '8', '10', '12', '14', '16'],
|
||||
# [11.0680836450622, 8.53864970807778, 7.59565430177984, 6.38741598498948, 5.83662961500838, 5.83662961500838]),
|
||||
# 'gshareCModel' : (['6', '8', '10', '12', '14', '16'],
|
||||
# [14.5859173702079, 12.3634674403619, 10.5806018170154, 8.38831266973592, 6.37097544620762, 3.52638362703015])
|
||||
#}
|
||||
|
||||
RefData = [('twobitCModel6', 11.0501534891674), ('twobitCModel8', 8.51829052266352), ('twobitCModel10', 7.56775222626483),
|
||||
('twobitCModel12', 6.31366834586515), ('twobitCModel14', 5.72699936834177), ('twobitCModel16', 5.72699936834177),
|
||||
('gshareCModel6', 14.5731555979574), ('gshareCModel8', 12.3155658100497), ('gshareCModel10', 10.4589596630561),
|
||||
('gshareCModel12', 8.25796055444401), ('gshareCModel14', 6.23093702707613), ('gshareCModel16', 3.34001125650374)]
|
||||
|
||||
|
||||
def ComputeCPI(benchmark):
|
||||
'Computes and inserts CPI into benchmark stats.'
|
||||
(nameString, opt, dataDict) = benchmark
|
||||
CPI = 1.0 * int(dataDict['Mcycle']) / int(dataDict['InstRet'])
|
||||
dataDict['CPI'] = CPI
|
||||
|
||||
def ComputeBranchDirMissRate(benchmark):
|
||||
'Computes and inserts branch direction miss prediction rate.'
|
||||
(nameString, opt, dataDict) = benchmark
|
||||
branchDirMissRate = 100.0 * int(dataDict['BP Dir Wrong']) / int(dataDict['Br Count'])
|
||||
dataDict['BDMR'] = branchDirMissRate
|
||||
|
||||
def ComputeBranchTargetMissRate(benchmark):
|
||||
'Computes and inserts branch target miss prediction rate.'
|
||||
# *** this is wrong in the verilog test bench
|
||||
(nameString, opt, dataDict) = benchmark
|
||||
branchTargetMissRate = 100.0 * int(dataDict['BP Target Wrong']) / (int(dataDict['Br Count']) + int(dataDict['Jump Not Return']))
|
||||
dataDict['BTMR'] = branchTargetMissRate
|
||||
|
||||
def ComputeRASMissRate(benchmark):
|
||||
'Computes and inserts return address stack miss prediction rate.'
|
||||
(nameString, opt, dataDict) = benchmark
|
||||
RASMPR = 100.0 * int(dataDict['RAS Wrong']) / int(dataDict['Return'])
|
||||
dataDict['RASMPR'] = RASMPR
|
||||
|
||||
def ComputeInstrClassMissRate(benchmark):
|
||||
'Computes and inserts instruction class miss prediction rate.'
|
||||
(nameString, opt, dataDict) = benchmark
|
||||
ClassMPR = 100.0 * int(dataDict['Instr Class Wrong']) / int(dataDict['InstRet'])
|
||||
dataDict['ClassMPR'] = ClassMPR
|
||||
|
||||
def ComputeICacheMissRate(benchmark):
|
||||
'Computes and inserts instruction class miss prediction rate.'
|
||||
(nameString, opt, dataDict) = benchmark
|
||||
ICacheMR = 100.0 * int(dataDict['I Cache Miss']) / int(dataDict['I Cache Access'])
|
||||
dataDict['ICacheMR'] = ICacheMR
|
||||
|
||||
def ComputeICacheMissTime(benchmark):
|
||||
'Computes and inserts instruction class miss prediction rate.'
|
||||
(nameString, opt, dataDict) = benchmark
|
||||
cycles = int(dataDict['I Cache Miss'])
|
||||
if(cycles == 0): ICacheMR = 0
|
||||
else: ICacheMR = 100.0 * int(dataDict['I Cache Cycles']) / cycles
|
||||
dataDict['ICacheMT'] = ICacheMR
|
||||
|
||||
def ComputeDCacheMissRate(benchmark):
|
||||
'Computes and inserts instruction class miss prediction rate.'
|
||||
(nameString, opt, dataDict) = benchmark
|
||||
DCacheMR = 100.0 * int(dataDict['D Cache Miss']) / int(dataDict['D Cache Access'])
|
||||
dataDict['DCacheMR'] = DCacheMR
|
||||
|
||||
def ComputeDCacheMissTime(benchmark):
|
||||
'Computes and inserts instruction class miss prediction rate.'
|
||||
(nameString, opt, dataDict) = benchmark
|
||||
cycles = int(dataDict['D Cache Miss'])
|
||||
if(cycles == 0): DCacheMR = 0
|
||||
else: DCacheMR = 100.0 * int(dataDict['D Cache Cycles']) / cycles
|
||||
dataDict['DCacheMT'] = DCacheMR
|
||||
|
||||
def ComputeAll(benchmarks):
|
||||
for benchmark in benchmarks:
|
||||
ComputeCPI(benchmark)
|
||||
ComputeBranchDirMissRate(benchmark)
|
||||
ComputeBranchTargetMissRate(benchmark)
|
||||
ComputeRASMissRate(benchmark)
|
||||
ComputeInstrClassMissRate(benchmark)
|
||||
ComputeICacheMissRate(benchmark)
|
||||
ComputeICacheMissTime(benchmark)
|
||||
ComputeDCacheMissRate(benchmark)
|
||||
ComputeDCacheMissTime(benchmark)
|
||||
|
||||
def printStats(benchmark):
|
||||
(nameString, opt, dataDict) = benchmark
|
||||
print('Test', nameString)
|
||||
print('Compile configuration', opt)
|
||||
print('CPI \t\t\t %1.2f' % dataDict['CPI'])
|
||||
print('Branch Dir Pred Miss Rate %2.2f' % dataDict['BDMR'])
|
||||
print('Branch Target Pred Miss Rate %2.2f' % dataDict['BTMR'])
|
||||
print('RAS Miss Rate \t\t %1.2f' % dataDict['RASMPR'])
|
||||
print('Instr Class Miss Rate %1.2f' % dataDict['ClassMPR'])
|
||||
print('I Cache Miss Rate %1.4f' % dataDict['ICacheMR'])
|
||||
print('I Cache Miss Ave Cycles %1.4f' % dataDict['ICacheMT'])
|
||||
print('D Cache Miss Rate %1.4f' % dataDict['DCacheMR'])
|
||||
print('D Cache Miss Ave Cycles %1.4f' % dataDict['DCacheMT'])
|
||||
print()
|
||||
|
||||
def ProcessFile(fileName):
|
||||
'''Extract preformance counters from a modelsim log. Outputs a list of tuples for each test/benchmark.
|
||||
The tuple contains the test name, optimization characteristics, and dictionary of performance counters.'''
|
||||
# 1 find lines with Read memfile and extract test name
|
||||
# 2 parse counters into a list of (name, value) tuples (dictionary maybe?)
|
||||
benchmarks = []
|
||||
transcript = open(fileName, 'r')
|
||||
HPMClist = { }
|
||||
testName = ''
|
||||
for line in transcript.readlines():
|
||||
lineToken = line.split()
|
||||
if(len(lineToken) > 3 and lineToken[1] == 'Read' and lineToken[2] == 'memfile'):
|
||||
opt = lineToken[3].split('/')[-4]
|
||||
testName = lineToken[3].split('/')[-1].split('.')[0]
|
||||
HPMClist = { }
|
||||
elif(len(lineToken) > 4 and lineToken[1][0:3] == 'Cnt'):
|
||||
countToken = line.split('=')[1].split()
|
||||
value = int(countToken[0])
|
||||
name = ' '.join(countToken[1:])
|
||||
HPMClist[name] = value
|
||||
elif ('is done' in line):
|
||||
benchmarks.append((testName, opt, HPMClist))
|
||||
return benchmarks
|
||||
|
||||
def ComputeArithmeticAverage(benchmarks):
|
||||
average = {}
|
||||
index = 0
|
||||
for (testName, opt, HPMClist) in benchmarks:
|
||||
for field in HPMClist:
|
||||
value = HPMClist[field]
|
||||
if field not in average:
|
||||
average[field] = value
|
||||
else:
|
||||
average[field] += value
|
||||
index += 1
|
||||
benchmarks.append(('All', '', average))
|
||||
|
||||
def FormatToPlot(currBenchmark):
|
||||
names = []
|
||||
values = []
|
||||
for config in currBenchmark:
|
||||
#print ('config' , config)
|
||||
names.append(config[0])
|
||||
values.append(config[1])
|
||||
return (names, values)
|
||||
|
||||
def GeometricAverage(benchmarks, field):
|
||||
Product = 1
|
||||
index = 0
|
||||
for (testName, opt, HPMCList) in benchmarks:
|
||||
#print(HPMCList)
|
||||
Product *= HPMCList[field]
|
||||
index += 1
|
||||
return Product ** (1.0/index)
|
||||
|
||||
def ComputeGeometricAverage(benchmarks):
|
||||
fields = ['BDMR', 'BTMR', 'RASMPR', 'ClassMPR', 'ICacheMR', 'DCacheMR', 'CPI', 'ICacheMT', 'DCacheMT']
|
||||
AllAve = {}
|
||||
for field in fields:
|
||||
Product = 1
|
||||
index = 0
|
||||
for (testName, opt, HPMCList) in benchmarks:
|
||||
#print(HPMCList)
|
||||
Product *= HPMCList[field]
|
||||
index += 1
|
||||
AllAve[field] = Product ** (1.0/index)
|
||||
benchmarks.append(('All', '', AllAve))
|
||||
|
||||
if(sys.argv[1] == '-b'):
|
||||
configList = []
|
||||
summery = 0
|
||||
if(sys.argv[2] == '-s'):
|
||||
summery = 1
|
||||
sys.argv = sys.argv[1::]
|
||||
for config in sys.argv[2::]:
|
||||
benchmarks = ProcessFile(config)
|
||||
#ComputeArithmeticAverage(benchmarks)
|
||||
ComputeAll(benchmarks)
|
||||
ComputeGeometricAverage(benchmarks)
|
||||
#print('CONFIG: %s GEO MEAN: %f' % (config, GeometricAverage(benchmarks, 'BDMR')))
|
||||
configList.append((config.split('.')[0], benchmarks))
|
||||
|
||||
# Merge all configruations into a single list
|
||||
benchmarkAll = []
|
||||
for (config, benchmarks) in configList:
|
||||
#print(config)
|
||||
for benchmark in benchmarks:
|
||||
(nameString, opt, dataDict) = benchmark
|
||||
#print("BENCHMARK")
|
||||
#print(nameString)
|
||||
#print(opt)
|
||||
#print(dataDict)
|
||||
benchmarkAll.append((nameString, opt, config, dataDict))
|
||||
#print('ALL!!!!!!!!!!')
|
||||
#for bench in benchmarkAll:
|
||||
# print('BENCHMARK')
|
||||
# print(bench)
|
||||
#print('ALL!!!!!!!!!!')
|
||||
|
||||
# now extract all branch prediction direction miss rates for each
|
||||
# namestring + opt, config
|
||||
benchmarkDict = { }
|
||||
for benchmark in benchmarkAll:
|
||||
(name, opt, config, dataDict) = benchmark
|
||||
if name+'_'+opt in benchmarkDict:
|
||||
benchmarkDict[name+'_'+opt].append((config, dataDict['BDMR']))
|
||||
else:
|
||||
benchmarkDict[name+'_'+opt] = [(config, dataDict['BDMR'])]
|
||||
|
||||
size = len(benchmarkDict)
|
||||
index = 1
|
||||
if(summery == 0):
|
||||
#print('Number of plots', size)
|
||||
|
||||
for benchmarkName in benchmarkDict:
|
||||
currBenchmark = benchmarkDict[benchmarkName]
|
||||
(names, values) = FormatToPlot(currBenchmark)
|
||||
print(names, values)
|
||||
plt.subplot(6, 7, index)
|
||||
plt.bar(names, values)
|
||||
plt.title(benchmarkName)
|
||||
plt.ylabel('BR Dir Miss Rate (%)')
|
||||
#plt.xlabel('Predictor')
|
||||
index += 1
|
||||
else:
|
||||
combined = benchmarkDict['All_']
|
||||
# merge the reference data into rtl data
|
||||
combined.extend(RefData)
|
||||
(name, value) = FormatToPlot(combined)
|
||||
lst = []
|
||||
dct = {}
|
||||
category = []
|
||||
length = []
|
||||
accuracy = []
|
||||
for index in range(0, len(name)):
|
||||
match = re.match(r"([a-z]+)([0-9]+)", name[index], re.I)
|
||||
percent = 100 -value[index]
|
||||
if match:
|
||||
(PredType, size) = match.groups()
|
||||
category.append(PredType)
|
||||
length.append(size)
|
||||
accuracy.append(percent)
|
||||
if(PredType not in dct):
|
||||
dct[PredType] = ([size], [percent])
|
||||
else:
|
||||
(currSize, currPercent) = dct[PredType]
|
||||
currSize.append(size)
|
||||
currPercent.append(percent)
|
||||
dct[PredType] = (currSize, currPercent)
|
||||
print(dct)
|
||||
fig, axes = plt.subplots()
|
||||
marker={'twobit' : '^', 'gshare' : 'o', 'global' : 's', 'gshareBasic' : '*', 'globalBasic' : 'x', 'btb': 'x', 'twobitCModel' : 'x', 'gshareCModel' : '*'}
|
||||
colors={'twobit' : 'black', 'gshare' : 'blue', 'global' : 'dodgerblue', 'gshareBasic' : 'turquoise', 'globalBasic' : 'lightsteelblue', 'btb' : 'blue', 'twobitCModel' : 'gray', 'gshareCModel' : 'dodgerblue'}
|
||||
for cat in dct:
|
||||
(x, y) = dct[cat]
|
||||
x=[int(2**int(v)) for v in x]
|
||||
print(x, y)
|
||||
axes.plot(x,y, color=colors[cat])
|
||||
axes.scatter(x,y, label=cat, marker=marker[cat], color=colors[cat])
|
||||
#plt.scatter(x, y, label=cat)
|
||||
#plt.plot(x, y)
|
||||
#axes.set_xticks([4, 6, 8, 10, 12, 14])
|
||||
axes.legend(loc='upper left')
|
||||
axes.set_xscale("log")
|
||||
axes.set_ylabel('Prediction Accuracy')
|
||||
axes.set_xlabel('Entries')
|
||||
axes.set_xticks([64, 256, 1024, 4096, 16384, 65536])
|
||||
axes.set_xticklabels([64, 256, 1024, 4096, 16384, 65536])
|
||||
axes.grid(color='b', alpha=0.5, linestyle='dashed', linewidth=0.5)
|
||||
plt.show()
|
||||
|
||||
|
||||
else:
|
||||
# steps 1 and 2
|
||||
benchmarks = ProcessFile(sys.argv[1])
|
||||
print(benchmarks[0])
|
||||
ComputeAll(benchmarks)
|
||||
ComputeGeometricAverage(benchmarks)
|
||||
# 3 process into useful data
|
||||
# cache hit rates
|
||||
# cache fill time
|
||||
# branch predictor status
|
||||
# hazard counts
|
||||
# CPI
|
||||
# instruction distribution
|
||||
for benchmark in benchmarks:
|
||||
printStats(benchmark)
|
||||
|
||||
@ -1,50 +0,0 @@
|
||||
#!/bin/bash
|
||||
# Alessandro Maiuolo 2022
|
||||
# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
|
||||
configFile=config/shared/wally-shared.vh
|
||||
|
||||
searchRadix="define RADIX 32'"..
|
||||
searchCopies="define DIVCOPIES 32'"..
|
||||
|
||||
currRadix="define RADIX 32'h2"
|
||||
currCopies="define DIVCOPIES 32'h1"
|
||||
sed -i "s/$searchRadix/$currRadix/" $configFile
|
||||
sed -i "s/$searchCopies/$currCopies/" $configFile
|
||||
echo regression on Radix :$currRadix: and Copies :$currCopies:
|
||||
./sim/regression-wally
|
||||
|
||||
currRadix="define RADIX 32'h2"
|
||||
currCopies="define DIVCOPIES 32'h2"
|
||||
sed -i "s/$searchRadix/$currRadix/" $configFile
|
||||
sed -i "s/$searchCopies/$currCopies/" $configFile
|
||||
echo regression on Radix :$currRadix: and Copies :$currCopies:
|
||||
./sim/regression-wally
|
||||
|
||||
currRadix="define RADIX 32'h2"
|
||||
currCopies="define DIVCOPIES 32'h4"
|
||||
sed -i "s/$searchRadix/$currRadix/" $configFile
|
||||
sed -i "s/$searchCopies/$currCopies/" $configFile
|
||||
echo regression on Radix :$currRadix: and Copies :$currCopies:
|
||||
./sim/regression-wally
|
||||
|
||||
currRadix="define RADIX 32'h4"
|
||||
currCopies="define DIVCOPIES 32'h1"
|
||||
sed -i "s/$searchRadix/$currRadix/" $configFile
|
||||
sed -i "s/$searchCopies/$currCopies/" $configFile
|
||||
echo regression on Radix :$currRadix: and Copies :$currCopies:
|
||||
./sim/regression-wally
|
||||
|
||||
currRadix="define RADIX 32'h4"
|
||||
currCopies="define DIVCOPIES 32'h2"
|
||||
sed -i "s/$searchRadix/$currRadix/" $configFile
|
||||
sed -i "s/$searchCopies/$currCopies/" $configFile
|
||||
echo regression on Radix :$currRadix: and Copies :$currCopies:
|
||||
./sim/regression-wally
|
||||
|
||||
currRadix="define RADIX 32'h4"
|
||||
currCopies="define DIVCOPIES 32'h4"
|
||||
sed -i "s/$searchRadix/$currRadix/" $configFile
|
||||
sed -i "s/$searchCopies/$currCopies/" $configFile
|
||||
echo regression on Radix :$currRadix: and Copies :$currCopies:
|
||||
./sim/regression-wally
|
||||
@ -1 +0,0 @@
|
||||
../addins/branch-predictor-simulator/src/sim_bp
|
||||
@ -1,44 +0,0 @@
|
||||
#!/bin/bash
|
||||
|
||||
###########################################
|
||||
## testcount.pl
|
||||
##
|
||||
## Written: David_Harris@hmc.edu
|
||||
## Created: 25 December 2022
|
||||
## Modified: Read the riscv-test-suite directories from riscv-arch-test
|
||||
## and count how many tests are in each
|
||||
##
|
||||
## Purpose: Read the riscv-test-suite directories from riscv-arch-test
|
||||
## and count how many tests are in each
|
||||
##
|
||||
## A component of the CORE-V-WALLY configurable RISC-V project.
|
||||
##
|
||||
## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
|
||||
##
|
||||
## SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
##
|
||||
## Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||
## except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||
## may obtain a copy of the License at
|
||||
##
|
||||
## https:##solderpad.org/licenses/SHL-2.1/
|
||||
##
|
||||
## Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||
## License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||
## either express or implied. See the License for the specific language governing permissions
|
||||
## and limitations under the License.
|
||||
################################################################################################
|
||||
|
||||
for dir in `ls ${WALLY}/addins/riscv-arch-test/riscv-test-suite/rv*/*`
|
||||
do
|
||||
dir=$(echo $dir | cut -d':' -f1)
|
||||
echo $dir
|
||||
for fn in `ls $dir/src/*.S`
|
||||
do
|
||||
result=`grep 'inst_' $fn | tail -n 1`
|
||||
num=$(echo $result| cut -d'_' -f 2 | cut -d':' -f 1)
|
||||
((num++))
|
||||
fnbase=`basename $fn`
|
||||
echo "$fnbase: $num"
|
||||
done
|
||||
done
|
||||
@ -1,33 +1,8 @@
|
||||
#!/bin/perl -W
|
||||
|
||||
###########################################
|
||||
## testlist.pl
|
||||
##
|
||||
## Written: David_Harris@hmc.edu
|
||||
## Created: 25 December 2021
|
||||
## Modified:
|
||||
##
|
||||
## Purpose: Read the work directories from riscv-arch-test or imperas-riscv-tests
|
||||
## and generate a list of tests and signature addresses for tests.vh
|
||||
##
|
||||
## A component of the CORE-V-WALLY configurable RISC-V project.
|
||||
##
|
||||
## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
|
||||
##
|
||||
## SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
##
|
||||
## Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||
## except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||
## may obtain a copy of the License at
|
||||
##
|
||||
## https:##solderpad.org/licenses/SHL-2.1/
|
||||
##
|
||||
## Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||
## License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||
## either express or implied. See the License for the specific language governing permissions
|
||||
## and limitations under the License.
|
||||
################################################################################################
|
||||
|
||||
# testlist.pl
|
||||
# David_Harris@hmc.edu 25 December 2021
|
||||
# Read the work directories from riscv-arch-test or imperas-riscv-tests
|
||||
# and generate a list of tests and signature addresses for tests.vh
|
||||
|
||||
use strict;
|
||||
use warnings;
|
||||
|
||||
@ -1,69 +0,0 @@
|
||||
#!/usr/bin/perl -w
|
||||
|
||||
###########################################
|
||||
## vclean.pl
|
||||
##
|
||||
## Written: David_Harris@hmc.edu
|
||||
## Created: 7 December 2023
|
||||
## Modified:
|
||||
##
|
||||
## Purpose: Identifies unused signals in Verilog files
|
||||
## verilator should do this, but it also reports partially used signals
|
||||
##
|
||||
## A component of the CORE-V-WALLY configurable RISC-V project.
|
||||
##
|
||||
## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
|
||||
##
|
||||
## SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
##
|
||||
## Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||
## except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||
## may obtain a copy of the License at
|
||||
##
|
||||
## https:##solderpad.org/licenses/SHL-2.1/
|
||||
##
|
||||
## Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||
## License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||
## either express or implied. See the License for the specific language governing permissions
|
||||
## and limitations under the License.
|
||||
################################################################################################
|
||||
|
||||
use strict;
|
||||
|
||||
for (my $i=0; $i<=$#ARGV; $i++) {
|
||||
my $fname = $ARGV[$i];
|
||||
&clean($fname);
|
||||
}
|
||||
|
||||
sub clean {
|
||||
my $fname = shift;
|
||||
|
||||
# printf ("Cleaning $fname\n");
|
||||
open(FILE, $fname) || die("Can't read $fname");
|
||||
# my $incomment = 0;
|
||||
my @allsigs;
|
||||
while (<FILE>) {
|
||||
if (/typedef/) { } # skip typedefs
|
||||
elsif (/logic (.*)/) { # found signal declarations
|
||||
my $siglist = $1;
|
||||
$siglist =~ s/\/\/.*//; # trim off everything after //
|
||||
# print ("Logic: $siglist\n");
|
||||
$siglist =~ s/\[[^\]]*\]//g; # trim off everything in brackets
|
||||
$siglist =~ s/\s//g; # trim off white space
|
||||
# print ("Logic Trimmed: $siglist\n");
|
||||
my @sigs = split(/[,;)]/, $siglist);
|
||||
# print ("Logic parsed: @sigs\n");
|
||||
push(@allsigs, @sigs);
|
||||
}
|
||||
}
|
||||
# print("Signals: @allsigs\n");
|
||||
foreach my $sig (@allsigs) {
|
||||
if ($sig eq "") { last }; # skip empty signals
|
||||
# print("Searching for '$sig'\n");
|
||||
my $hits = `grep -c $sig $fname`;
|
||||
# print(" Signal $sig appears $hits times\n");
|
||||
if ($hits < 2) {
|
||||
printf("$sig not used in $fname\n");
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -1,156 +0,0 @@
|
||||
#!/bin/bash
|
||||
###########################################
|
||||
## Tool chain install script.
|
||||
##
|
||||
## Written: Ross Thompson ross1728@gmail.com
|
||||
## Created: 18 January 2023
|
||||
## Modified: 22 January 2023
|
||||
## Modified: 23 March 2023
|
||||
##
|
||||
## Purpose: Open source tool chain installation script
|
||||
##
|
||||
## A component of the CORE-V-WALLY configurable RISC-V project.
|
||||
##
|
||||
## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
|
||||
##
|
||||
## SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
##
|
||||
## Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||
## except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||
## may obtain a copy of the License at
|
||||
##
|
||||
## https:##solderpad.org/licenses/SHL-2.1/
|
||||
##
|
||||
## Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||
## License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||
## either express or implied. See the License for the specific language governing permissions
|
||||
## and limitations under the License.
|
||||
################################################################################################
|
||||
|
||||
# Use /opt/riscv for installation - may require running script with sudo
|
||||
export RISCV="${1:-/opt/riscv}"
|
||||
export PATH=$PATH:$RISCV/bin:/usr/bin
|
||||
|
||||
set -e # break on error
|
||||
|
||||
# Modify accordingly for your machine
|
||||
# Increasing NUM_THREADS will speed up parallel compilation of the tools
|
||||
#NUM_THREADS=2 # for low memory machines > 16GiB
|
||||
NUM_THREADS=8 # for >= 32GiB
|
||||
#NUM_THREADS=16 # for >= 64GiB
|
||||
|
||||
sudo mkdir -p $RISCV
|
||||
# *** need to update permissions to local user
|
||||
|
||||
# Update and Upgrade tools (see https://itsfoss.com/apt-update-vs-upgrade/)
|
||||
sudo apt update -y
|
||||
sudo apt upgrade -y
|
||||
sudo apt install -y git gawk make texinfo bison flex build-essential python3 libz-dev libexpat-dev autoconf device-tree-compiler ninja-build libpixman-1-dev ncurses-base ncurses-bin libncurses5-dev dialog curl wget ftp libgmp-dev libglib2.0-dev python3-pip pkg-config opam z3 zlib1g-dev verilator automake autotools-dev libmpc-dev libmpfr-dev gperf libtool patchutils bc
|
||||
# Other python libraries used through the book.
|
||||
sudo pip3 install matplotlib scipy scikit-learn adjustText lief
|
||||
|
||||
# needed for Ubuntu 22.04, gcc cross compiler expects python not python2 or python3.
|
||||
if ! command -v python &> /dev/null
|
||||
then
|
||||
echo "WARNING: python3 was installed as python3 rather than python. Creating symlink."
|
||||
sudo ln -sf /usr/bin/python3 /usr/bin/python
|
||||
fi
|
||||
|
||||
# gcc cross-compiler (https://github.com/riscv-collab/riscv-gnu-toolchain)
|
||||
# To install GCC from source can take hours to compile.
|
||||
#This configuration enables multilib to target many flavors of RISC-V.
|
||||
# This book is tested with GCC 12.2 (tagged 2023.01.31), but will likely work with newer versions as well.
|
||||
# Note that GCC12.2 has binutils 2.39, which has a known performance bug that causes
|
||||
# objdump to run 100x slower than in previous versions, causing riscof to make versy slowly.
|
||||
# However GCC12.x is needed for bit manipulation instructions. There is an open issue to fix this:
|
||||
# https://github.com/riscv-collab/riscv-gnu-toolchain/issues/1188
|
||||
|
||||
cd $RISCV
|
||||
git clone https://github.com/riscv/riscv-gnu-toolchain
|
||||
cd riscv-gnu-toolchain
|
||||
#git checkout 2023.01.31 #for 12.2.0; 2023.04.29 for 13.1
|
||||
# Temporarily use the following commands until gcc-13 is part of riscv-gnu-toolchain (issue #1249)
|
||||
git clone https://github.com/gcc-mirror/gcc -b releases/gcc-13 gcc-13
|
||||
./configure --prefix=/opt/riscv --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;" --with-gcc-src=`pwd`/gcc-13
|
||||
#./configure --prefix=${RISCV} --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;"
|
||||
make -j ${NUM_THREADS}
|
||||
|
||||
# elf2hex (https://github.com/sifive/elf2hex)
|
||||
#The elf2hex utility to converts executable files into hexadecimal files for Verilog simulation.
|
||||
# Note: The exe2hex utility that comes with Spike doesn’t work for our purposes because it doesn’t
|
||||
# handle programs that start at 0x80000000. The SiFive version above is touchy to install.
|
||||
# For example, if Python version 2.x is in your path, it won’t install correctly.
|
||||
# Also, be sure riscv64-unknown-elf-objcopy shows up in your path in $RISCV/riscv-gnu-toolchain/bin
|
||||
# at the time of compilation, or elf2hex won’t work properly.
|
||||
cd $RISCV
|
||||
export PATH=$RISCV/bin:$PATH
|
||||
git clone https://github.com/sifive/elf2hex.git
|
||||
cd elf2hex
|
||||
autoreconf -i
|
||||
./configure --target=riscv64-unknown-elf --prefix=$RISCV
|
||||
make
|
||||
make install
|
||||
|
||||
|
||||
# QEMU (https://www.qemu.org/docs/master/system/target-riscv.html)
|
||||
cd $RISCV
|
||||
git clone --recurse-submodules https://github.com/qemu/qemu
|
||||
cd qemu
|
||||
./configure --target-list=riscv64-softmmu --prefix=$RISCV
|
||||
make -j ${NUM_THREADS}
|
||||
make install
|
||||
|
||||
# Spike (https://github.com/riscv-software-src/riscv-isa-sim)
|
||||
# Spike also takes a while to install and compile, but this can be done concurrently
|
||||
#with the GCC installation. After the build, we need to change two Makefiles to support atomic instructions.
|
||||
cd $RISCV
|
||||
git clone https://github.com/riscv-software-src/riscv-isa-sim
|
||||
mkdir -p riscv-isa-sim/build
|
||||
cd riscv-isa-sim/build
|
||||
../configure --prefix=$RISCV
|
||||
make -j ${NUM_THREADS}
|
||||
make install
|
||||
cd ../arch_test_target/spike/device
|
||||
sed -i 's/--isa=rv32ic/--isa=rv32iac/' rv32i_m/privilege/Makefile.include
|
||||
sed -i 's/--isa=rv64ic/--isa=rv64iac/' rv64i_m/privilege/Makefile.include
|
||||
|
||||
# Sail (https://github.com/riscv/sail-riscv)
|
||||
# Sail is the new golden reference model for RISC-V. Sail is written in OCaml, which
|
||||
# is an object-oriented extension of ML, which in turn is a functional programming
|
||||
# language suited to formal verification. OCaml is installed with the opam OCcaml
|
||||
# package manager. Sail has so many dependencies that it can be difficult to install.
|
||||
# This script works for Ubuntu.
|
||||
|
||||
# Do these commands only for RedHat / Rocky 8 to build from source.
|
||||
#cd $RISCV
|
||||
#git clone https://github.com/Z3Prover/z3.git
|
||||
#cd z3
|
||||
#python scripts/mk_make.py
|
||||
#cd build
|
||||
#make -j ${NUM_THREADS}
|
||||
#make install
|
||||
#cd ../..
|
||||
#pip3 install chardet==3.0.4
|
||||
#pip3 install urllib3==1.22
|
||||
|
||||
cd $RISCV
|
||||
opam init -y --disable-sandboxing
|
||||
opam switch create ocaml-base-compiler.4.08.0
|
||||
opam install sail -y
|
||||
|
||||
eval $(opam config env)
|
||||
git clone https://github.com/riscv/sail-riscv.git
|
||||
cd sail-riscv
|
||||
# Current bug in Sail - use hash that works for Wally
|
||||
# (may remove later if Sail is ever fixed)
|
||||
#git checkout 4d05aa1698a0003a4f6f99e1380c743711c32052
|
||||
make -j ${NUM_THREADS}
|
||||
ARCH=RV32 make -j ${NUM_THREADS}
|
||||
# next line seems redundant
|
||||
#ARCH=RV64 make -j ${NUM_THREADS}
|
||||
sudo ln -sf $RISCV/sail-riscv/c_emulator/riscv_sim_RV64 /usr/bin/riscv_sim_RV64
|
||||
sudo ln -sf $RISCV/sail-riscv/c_emulator/riscv_sim_RV32 /usr/bin/riscv_sim_RV32
|
||||
|
||||
sudo pip3 install testresources
|
||||
pip3 install git+https://github.com/riscv/riscof.git
|
||||
|
||||
4
bugs.txt
4
bugs.txt
@ -1,2 +1,2 @@
|
||||
1. [ ] AMO should always generate store faults never load faults. We are generating both.
|
||||
|
||||
1. [X] Cache is suppressing d cache flush if there is a dtlb miss.
|
||||
1. Fixed by disabling mmu's address translation on flush.
|
||||
|
||||
@ -1,152 +0,0 @@
|
||||
//////////////////////////////////////////
|
||||
// wally-config.vh
|
||||
//
|
||||
// Written: David_Harris@hmc.edu 4 January 2021
|
||||
// Modified:
|
||||
//
|
||||
// Purpose: Specify which features are configured
|
||||
// Macros to determine which modes are supported based on MISA
|
||||
//
|
||||
// A component of the Wally configurable RISC-V project.
|
||||
//
|
||||
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
//
|
||||
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||
// may obtain a copy of the License at
|
||||
//
|
||||
// https://solderpad.org/licenses/SHL-2.1/
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||
// either express or implied. See the License for the specific language governing permissions
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// include shared configuration
|
||||
`include "wally-shared.vh"
|
||||
|
||||
`define FPGA 1
|
||||
`define QEMU 0
|
||||
// RV32 or RV64: XLEN = 32 or 64
|
||||
`define XLEN 64
|
||||
|
||||
// IEEE 754 compliance
|
||||
`define IEEE754 0
|
||||
|
||||
`define MISA (32'h0014112D)
|
||||
`define ZICSR_SUPPORTED 1
|
||||
`define ZIFENCEI_SUPPORTED 1
|
||||
`define ZICOUNTERS_SUPPORTED 1
|
||||
`define COUNTERS 32
|
||||
`define ZFH_SUPPORTED 0
|
||||
`define SSTC_SUPPORTED 0
|
||||
|
||||
// LSU microarchitectural Features
|
||||
`define BUS_SUPPORTED 1
|
||||
`define DCACHE_SUPPORTED 1
|
||||
`define ICACHE_SUPPORTED 1
|
||||
`define VIRTMEM_SUPPORTED 1
|
||||
`define VECTORED_INTERRUPTS_SUPPORTED 1
|
||||
`define BIGENDIAN_SUPPORTED 1
|
||||
|
||||
// TLB configuration. Entries should be a power of 2
|
||||
`define ITLB_ENTRIES 32
|
||||
`define DTLB_ENTRIES 32
|
||||
|
||||
// Cache configuration. Sizes should be a power of two
|
||||
// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
|
||||
`define DCACHE_NUMWAYS 4
|
||||
`define DCACHE_WAYSIZEINBYTES 4096
|
||||
`define DCACHE_LINELENINBITS 512
|
||||
`define ICACHE_NUMWAYS 4
|
||||
`define ICACHE_WAYSIZEINBYTES 4096
|
||||
`define ICACHE_LINELENINBITS 512
|
||||
|
||||
// Integer Divider Configuration
|
||||
// IDIV_BITSPERCYCLE must be 1, 2, or 4
|
||||
`define IDIV_BITSPERCYCLE 4
|
||||
`define IDIV_ON_FPU 1
|
||||
|
||||
// Legal number of PMP entries are 0, 16, or 64
|
||||
`define PMP_ENTRIES 16
|
||||
|
||||
// Address space
|
||||
`define RESET_VECTOR 64'h0000000000001000
|
||||
|
||||
// WFI Timeout Wait
|
||||
`define WFI_TIMEOUT_BIT 16
|
||||
|
||||
// Peripheral Addresses
|
||||
// Peripheral memory space extends from BASE to BASE+RANGE
|
||||
// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
|
||||
`define DTIM_SUPPORTED 1'b0
|
||||
`define DTIM_BASE 56'h80000000
|
||||
`define DTIM_RANGE 56'h00001FFF
|
||||
`define IROM_SUPPORTED 1'b0
|
||||
`define IROM_BASE 56'h80000000
|
||||
`define IROM_RANGE 56'h00001FFF
|
||||
`define BOOTROM_SUPPORTED 1'b1
|
||||
`define BOOTROM_BASE 56'h00001000
|
||||
`define BOOTROM_RANGE 56'h00000FFF
|
||||
`define UNCORE_RAM_SUPPORTED 1'b1
|
||||
`define UNCORE_RAM_BASE 56'h80000000
|
||||
`define UNCORE_RAM_RANGE 56'h07FFFFFF
|
||||
`define EXT_MEM_SUPPORTED 1'b0
|
||||
`define EXT_MEM_BASE 56'h80000000
|
||||
`define EXT_MEM_RANGE 56'h07FFFFFF
|
||||
`define CLINT_SUPPORTED 1'b1
|
||||
`define CLINT_BASE 56'h02000000
|
||||
`define CLINT_RANGE 56'h0000FFFF
|
||||
`define GPIO_SUPPORTED 1'b1
|
||||
`define GPIO_BASE 56'h10060000
|
||||
`define GPIO_RANGE 56'h000000FF
|
||||
`define UART_SUPPORTED 1'b1
|
||||
`define UART_BASE 56'h10000000
|
||||
`define UART_RANGE 56'h00000007
|
||||
`define PLIC_SUPPORTED 1'b1
|
||||
`define PLIC_BASE 56'h0C000000
|
||||
`define PLIC_RANGE 56'h03FFFFFF
|
||||
`define SDC_SUPPORTED 1'b0
|
||||
`define SDC_BASE 56'h00012100
|
||||
`define SDC_RANGE 56'h0000001F
|
||||
|
||||
// Bus Interface width
|
||||
`define AHBW 64
|
||||
|
||||
// Test modes
|
||||
|
||||
// Tie GPIO outputs back to inputs
|
||||
`define GPIO_LOOPBACK_TEST 0
|
||||
|
||||
// Hardware configuration
|
||||
`define UART_PRESCALE 0
|
||||
|
||||
// Interrupt configuration
|
||||
`define PLIC_NUM_SRC 53
|
||||
`define PLIC_UART_ID 10
|
||||
`define PLIC_GPIO_ID 3
|
||||
|
||||
`define BPRED_SUPPORTED 1
|
||||
`define BPRED_TYPE "BP_GSHARE" // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
|
||||
`define BPRED_SIZE 10
|
||||
`define BTB_SIZE 10
|
||||
|
||||
|
||||
`define SVADU_SUPPORTED 1
|
||||
`define ZMMUL_SUPPORTED 0
|
||||
|
||||
// FPU division architecture
|
||||
`define RADIX 32'h4
|
||||
`define DIVCOPIES 32'h4
|
||||
|
||||
// bit manipulation
|
||||
`define ZBA_SUPPORTED 0
|
||||
`define ZBB_SUPPORTED 0
|
||||
`define ZBC_SUPPORTED 0
|
||||
`define ZBS_SUPPORTED 0
|
||||
|
||||
// Memory synthesis configuration
|
||||
`define USE_SRAM 0
|
||||
@ -1,161 +0,0 @@
|
||||
//////////////////////////////////////////
|
||||
// wally-config.vh
|
||||
//
|
||||
// Written: David_Harris@hmc.edu 4 January 2021
|
||||
// Modified:
|
||||
//
|
||||
// Purpose: Specify which features are configured
|
||||
// Macros to determine which modes are supported based on MISA
|
||||
//
|
||||
// A component of the Wally configurable RISC-V project.
|
||||
//
|
||||
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
//
|
||||
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||
// may obtain a copy of the License at
|
||||
//
|
||||
// https://solderpad.org/licenses/SHL-2.1/
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||
// either express or implied. See the License for the specific language governing permissions
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// include shared configuration
|
||||
`include "wally-shared.vh"
|
||||
|
||||
`define FPGA 1
|
||||
`define QEMU 0
|
||||
|
||||
// RV32 or RV64: XLEN = 32 or 64
|
||||
`define XLEN 64
|
||||
|
||||
// IEEE 754 compliance
|
||||
`define IEEE754 0
|
||||
|
||||
`define MISA (32'h0014112D)
|
||||
`define ZICSR_SUPPORTED 1
|
||||
`define ZIFENCEI_SUPPORTED 1
|
||||
`define ZICOUNTERS_SUPPORTED 1
|
||||
`define ZFH_SUPPORTED 0
|
||||
`define COUNTERS 32
|
||||
`define SSTC_SUPPORTED 0
|
||||
|
||||
// LSU microarchitectural Features
|
||||
`define BUS_SUPPORTED 1
|
||||
`define DCACHE_SUPPORTED 1
|
||||
`define ICACHE_SUPPORTED 1
|
||||
`define VIRTMEM_SUPPORTED 1
|
||||
`define VECTORED_INTERRUPTS_SUPPORTED 1
|
||||
`define BIGENDIAN_SUPPORTED 1
|
||||
|
||||
// TLB configuration. Entries should be a power of 2
|
||||
`define ITLB_ENTRIES 32
|
||||
`define DTLB_ENTRIES 32
|
||||
|
||||
// Cache configuration. Sizes should be a power of two
|
||||
// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
|
||||
`define DCACHE_NUMWAYS 4
|
||||
`define DCACHE_WAYSIZEINBYTES 4096
|
||||
`define DCACHE_LINELENINBITS 512
|
||||
`define ICACHE_NUMWAYS 4
|
||||
`define ICACHE_WAYSIZEINBYTES 4096
|
||||
`define ICACHE_LINELENINBITS 512
|
||||
|
||||
// Integer Divider Configuration
|
||||
// IDIV_BITSPERCYCLE must be 1, 2, or 4
|
||||
`define IDIV_BITSPERCYCLE 4
|
||||
`define IDIV_ON_FPU 1
|
||||
|
||||
// Legal number of PMP entries are 0, 16, or 64
|
||||
`define PMP_ENTRIES 16
|
||||
|
||||
// Address space
|
||||
`define RESET_VECTOR 64'h0000000000001000
|
||||
|
||||
// WFI Timeout Wait
|
||||
`define WFI_TIMEOUT_BIT 16
|
||||
|
||||
// Peripheral Addresses
|
||||
// Peripheral memory space extends from BASE to BASE+RANGE
|
||||
// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
|
||||
`define DTIM_SUPPORTED 1'b0
|
||||
`define DTIM_BASE 56'h80000000
|
||||
`define DTIM_RANGE 56'h00001FFF
|
||||
`define IROM_SUPPORTED 1'b0
|
||||
`define IROM_BASE 56'h80000000
|
||||
`define IROM_RANGE 56'h00001FFF
|
||||
|
||||
`define BOOTROM_SUPPORTED 1'b1
|
||||
`define BOOTROM_BASE 56'h00001000
|
||||
`define BOOTROM_RANGE 56'h00000FFF
|
||||
|
||||
`define UNCORE_RAM_SUPPORTED 1'b0
|
||||
`define UNCORE_RAM_BASE 56'h100000000
|
||||
`define UNCORE_RAM_RANGE 56'h07FFFFFF
|
||||
|
||||
`define EXT_MEM_SUPPORTED 1'b1
|
||||
`define EXT_MEM_BASE 56'h80000000
|
||||
`define EXT_MEM_RANGE 56'h07FFFFFF
|
||||
|
||||
`define EXT_SUPPORTED 1'b0
|
||||
`define EXT_BASE 56'h80000000
|
||||
`define EXT_RANGE 56'h07FFFFFF
|
||||
|
||||
`define CLINT_SUPPORTED 1'b1
|
||||
`define CLINT_BASE 56'h02000000
|
||||
`define CLINT_RANGE 56'h0000FFFF
|
||||
`define GPIO_SUPPORTED 1'b1
|
||||
`define GPIO_BASE 56'h10060000
|
||||
`define GPIO_RANGE 56'h000000FF
|
||||
`define UART_SUPPORTED 1'b1
|
||||
`define UART_BASE 56'h10000000
|
||||
`define UART_RANGE 56'h00000007
|
||||
`define PLIC_SUPPORTED 1'b1
|
||||
`define PLIC_BASE 56'h0C000000
|
||||
`define PLIC_RANGE 56'h03FFFFFF
|
||||
`define SDC_SUPPORTED 1'b1
|
||||
`define SDC_BASE 56'h00012100
|
||||
`define SDC_RANGE 56'h0000001F
|
||||
|
||||
// Bus Interface width
|
||||
`define AHBW 64
|
||||
|
||||
// Test modes
|
||||
|
||||
// Tie GPIO outputs back to inputs
|
||||
`define GPIO_LOOPBACK_TEST 0
|
||||
|
||||
// Hardware configuration
|
||||
`define UART_PRESCALE 0
|
||||
|
||||
// Interrupt configuration
|
||||
`define PLIC_NUM_SRC 53
|
||||
`define PLIC_UART_ID 10
|
||||
`define PLIC_GPIO_ID 3
|
||||
|
||||
`define BPRED_SUPPORTED 1
|
||||
`define BPRED_TYPE "BP_GSHARE" // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
|
||||
`define BPRED_SIZE 12
|
||||
`define BTB_SIZE 10
|
||||
|
||||
|
||||
`define SVADU_SUPPORTED 1
|
||||
`define ZMMUL_SUPPORTED 0
|
||||
|
||||
// FPU division architecture
|
||||
`define RADIX 32'h4
|
||||
`define DIVCOPIES 32'h4
|
||||
|
||||
// bit manipulation
|
||||
`define ZBA_SUPPORTED 0
|
||||
`define ZBB_SUPPORTED 0
|
||||
`define ZBC_SUPPORTED 0
|
||||
`define ZBS_SUPPORTED 0
|
||||
|
||||
// Memory synthesis configuration
|
||||
`define USE_SRAM 0
|
||||
@ -1,155 +0,0 @@
|
||||
//////////////////////////////////////////
|
||||
// wally-config.vh
|
||||
//
|
||||
// Written: David_Harris@hmc.edu 4 January 2021
|
||||
// Modified:
|
||||
//
|
||||
// Purpose: Specify which features are configured
|
||||
// Macros to determine which modes are supported based on MISA
|
||||
//
|
||||
// A component of the Wally configurable RISC-V project.
|
||||
//
|
||||
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
//
|
||||
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||
// may obtain a copy of the License at
|
||||
//
|
||||
// https://solderpad.org/licenses/SHL-2.1/
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||
// either express or implied. See the License for the specific language governing permissions
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// include shared configuration
|
||||
`include "wally-shared.vh"
|
||||
|
||||
`define FPGA 0
|
||||
`define QEMU 0
|
||||
|
||||
// RV32 or RV64: XLEN = 32 or 64
|
||||
`define XLEN 32
|
||||
|
||||
// IEEE 754 compliance
|
||||
`define IEEE754 0
|
||||
|
||||
// E
|
||||
`define MISA (32'h00000010)
|
||||
`define ZICSR_SUPPORTED 0
|
||||
`define ZIFENCEI_SUPPORTED 0
|
||||
`define COUNTERS 0
|
||||
`define ZICOUNTERS_SUPPORTED 0
|
||||
`define ZFH_SUPPORTED 0
|
||||
`define SSTC_SUPPORTED 0
|
||||
|
||||
// LSU microarchitectural Features
|
||||
`define BUS_SUPPORTED 1
|
||||
`define DCACHE_SUPPORTED 0
|
||||
`define ICACHE_SUPPORTED 0
|
||||
`define VIRTMEM_SUPPORTED 0
|
||||
`define VECTORED_INTERRUPTS_SUPPORTED 0
|
||||
`define BIGENDIAN_SUPPORTED 0
|
||||
|
||||
// TLB configuration. Entries should be a power of 2
|
||||
`define ITLB_ENTRIES 0
|
||||
`define DTLB_ENTRIES 0
|
||||
|
||||
// Cache configuration. Sizes should be a power of two
|
||||
// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
|
||||
`define DCACHE_NUMWAYS 4
|
||||
`define DCACHE_WAYSIZEINBYTES 4096
|
||||
`define DCACHE_LINELENINBITS 512
|
||||
`define ICACHE_NUMWAYS 4
|
||||
`define ICACHE_WAYSIZEINBYTES 4096
|
||||
`define ICACHE_LINELENINBITS 512
|
||||
|
||||
// Integer Divider Configuration
|
||||
// IDIV_BITSPERCYCLE must be 1, 2, or 4
|
||||
`define IDIV_BITSPERCYCLE 1
|
||||
`define IDIV_ON_FPU 0
|
||||
|
||||
// Legal number of PMP entries are 0, 16, or 64
|
||||
`define PMP_ENTRIES 0
|
||||
|
||||
// Address space
|
||||
`define RESET_VECTOR 32'h80000000
|
||||
|
||||
// WFI Timeout Wait
|
||||
`define WFI_TIMEOUT_BIT 16
|
||||
|
||||
// Peripheral Addresses
|
||||
// Peripheral memory space extends from BASE to BASE+RANGE
|
||||
// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
|
||||
`define DTIM_SUPPORTED 1'b0
|
||||
`define DTIM_BASE 34'h80000000
|
||||
`define DTIM_RANGE 34'h007FFFFF
|
||||
`define IROM_SUPPORTED 1'b0
|
||||
`define IROM_BASE 34'h80000000
|
||||
`define IROM_RANGE 34'h007FFFFF
|
||||
`define BOOTROM_SUPPORTED 1'b1
|
||||
`define BOOTROM_BASE 34'h00001000
|
||||
`define BOOTROM_RANGE 34'h00000FFF
|
||||
`define UNCORE_RAM_SUPPORTED 1'b1
|
||||
`define UNCORE_RAM_BASE 34'h80000000
|
||||
`define UNCORE_RAM_RANGE 34'h07FFFFFF
|
||||
`define EXT_MEM_SUPPORTED 1'b0
|
||||
`define EXT_MEM_BASE 34'h80000000
|
||||
`define EXT_MEM_RANGE 34'h07FFFFFF
|
||||
`define CLINT_SUPPORTED 1'b0
|
||||
`define CLINT_BASE 34'h02000000
|
||||
`define CLINT_RANGE 34'h0000FFFF
|
||||
`define GPIO_SUPPORTED 1'b0
|
||||
`define GPIO_BASE 34'h10060000
|
||||
`define GPIO_RANGE 34'h000000FF
|
||||
`define UART_SUPPORTED 1'b0
|
||||
`define UART_BASE 34'h10000000
|
||||
`define UART_RANGE 34'h00000007
|
||||
`define PLIC_SUPPORTED 1'b0
|
||||
`define PLIC_BASE 34'h0C000000
|
||||
`define PLIC_RANGE 34'h03FFFFFF
|
||||
`define SDC_SUPPORTED 1'b0
|
||||
`define SDC_BASE 34'h00012100
|
||||
`define SDC_RANGE 34'h0000001F
|
||||
|
||||
// Bus Interface width
|
||||
`define AHBW 32
|
||||
|
||||
// Test modes
|
||||
|
||||
// Tie GPIO outputs back to inputs
|
||||
`define GPIO_LOOPBACK_TEST 1
|
||||
|
||||
// Hardware configuration
|
||||
`define UART_PRESCALE 1
|
||||
|
||||
// Interrupt configuration
|
||||
`define PLIC_NUM_SRC 10
|
||||
// comment out the following if >=32 sources
|
||||
`define PLIC_NUM_SRC_LT_32
|
||||
`define PLIC_GPIO_ID 3
|
||||
`define PLIC_UART_ID 10
|
||||
|
||||
`define BPRED_SUPPORTED 0
|
||||
`define BPRED_TYPE "BP_GSHARE" // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
|
||||
`define BPRED_SIZE 10
|
||||
`define BTB_SIZE 10
|
||||
|
||||
`define SVADU_SUPPORTED 0
|
||||
`define ZMMUL_SUPPORTED 0
|
||||
|
||||
// FPU division architecture
|
||||
`define RADIX 32'h4
|
||||
`define DIVCOPIES 32'h4
|
||||
|
||||
// bit manipulation
|
||||
`define ZBA_SUPPORTED 0
|
||||
`define ZBB_SUPPORTED 0
|
||||
`define ZBC_SUPPORTED 0
|
||||
`define ZBS_SUPPORTED 0
|
||||
|
||||
// Memory synthesis configuration
|
||||
`define USE_SRAM 0
|
||||
@ -1,154 +0,0 @@
|
||||
//////////////////////////////////////////
|
||||
// wally-config.vh
|
||||
//
|
||||
// Written: David_Harris@hmc.edu 4 January 2021
|
||||
// Modified:
|
||||
//
|
||||
// Purpose: Specify which features are configured
|
||||
// Macros to determine which modes are supported based on MISA
|
||||
//
|
||||
// A component of the Wally configurable RISC-V project.
|
||||
//
|
||||
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
//
|
||||
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||
// may obtain a copy of the License at
|
||||
//
|
||||
// https://solderpad.org/licenses/SHL-2.1/
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||
// either express or implied. See the License for the specific language governing permissions
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// include shared configuration
|
||||
`include "wally-shared.vh"
|
||||
|
||||
`define FPGA 0
|
||||
`define QEMU 0
|
||||
|
||||
// RV32 or RV64: XLEN = 32 or 64
|
||||
`define XLEN 32
|
||||
|
||||
// IEEE 754 compliance
|
||||
`define IEEE754 0
|
||||
|
||||
`define MISA (32'h00000104 | 1 << 20 | 1 << 18 | 1 << 12 | 1 << 0 | 1 <<3 | 1 << 5)
|
||||
`define ZICSR_SUPPORTED 1
|
||||
`define ZIFENCEI_SUPPORTED 1
|
||||
`define COUNTERS 32
|
||||
`define ZICOUNTERS_SUPPORTED 1
|
||||
`define ZFH_SUPPORTED 0
|
||||
`define SSTC_SUPPORTED 1
|
||||
|
||||
// LSU microarchitectural Features
|
||||
`define BUS_SUPPORTED 1
|
||||
`define DCACHE_SUPPORTED 1
|
||||
`define ICACHE_SUPPORTED 1
|
||||
`define VIRTMEM_SUPPORTED 1
|
||||
`define VECTORED_INTERRUPTS_SUPPORTED 1
|
||||
`define BIGENDIAN_SUPPORTED 1
|
||||
|
||||
// TLB configuration. Entries should be a power of 2
|
||||
`define ITLB_ENTRIES 32
|
||||
`define DTLB_ENTRIES 32
|
||||
|
||||
// Cache configuration. Sizes should be a power of two
|
||||
// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
|
||||
`define DCACHE_NUMWAYS 4
|
||||
`define DCACHE_WAYSIZEINBYTES 4096
|
||||
`define DCACHE_LINELENINBITS 512
|
||||
`define ICACHE_NUMWAYS 4
|
||||
`define ICACHE_WAYSIZEINBYTES 4096
|
||||
`define ICACHE_LINELENINBITS 512
|
||||
|
||||
// Integer Divider Configuration
|
||||
// IDIV_BITSPERCYCLE must be 1, 2, or 4
|
||||
`define IDIV_BITSPERCYCLE 4
|
||||
`define IDIV_ON_FPU 1
|
||||
|
||||
// Legal number of PMP entries are 0, 16, or 64
|
||||
`define PMP_ENTRIES 16
|
||||
|
||||
// Address space
|
||||
`define RESET_VECTOR 32'h80000000
|
||||
|
||||
// WFI Timeout Wait
|
||||
`define WFI_TIMEOUT_BIT 16
|
||||
|
||||
// Peripheral Addresses
|
||||
// Peripheral memory space extends from BASE to BASE+RANGE
|
||||
// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
|
||||
`define DTIM_SUPPORTED 1'b0
|
||||
`define DTIM_BASE 34'h80000000
|
||||
`define DTIM_RANGE 34'h007FFFFF
|
||||
`define IROM_SUPPORTED 1'b0
|
||||
`define IROM_BASE 34'h80000000
|
||||
`define IROM_RANGE 34'h007FFFFF
|
||||
`define BOOTROM_SUPPORTED 1'b1
|
||||
`define BOOTROM_BASE 34'h00001000
|
||||
`define BOOTROM_RANGE 34'h00000FFF
|
||||
`define UNCORE_RAM_SUPPORTED 1'b1
|
||||
`define UNCORE_RAM_BASE 34'h80000000
|
||||
`define UNCORE_RAM_RANGE 34'h07FFFFFF
|
||||
`define EXT_MEM_SUPPORTED 1'b0
|
||||
`define EXT_MEM_BASE 34'h80000000
|
||||
`define EXT_MEM_RANGE 34'h07FFFFFF
|
||||
`define CLINT_SUPPORTED 1'b1
|
||||
`define CLINT_BASE 34'h02000000
|
||||
`define CLINT_RANGE 34'h0000FFFF
|
||||
`define GPIO_SUPPORTED 1'b1
|
||||
`define GPIO_BASE 34'h10060000
|
||||
`define GPIO_RANGE 34'h000000FF
|
||||
`define UART_SUPPORTED 1'b1
|
||||
`define UART_BASE 34'h10000000
|
||||
`define UART_RANGE 34'h00000007
|
||||
`define PLIC_SUPPORTED 1'b1
|
||||
`define PLIC_BASE 34'h0C000000
|
||||
`define PLIC_RANGE 34'h03FFFFFF
|
||||
`define SDC_SUPPORTED 1'b0
|
||||
`define SDC_BASE 34'h00012100
|
||||
`define SDC_RANGE 34'h0000001F
|
||||
|
||||
// Bus Interface width
|
||||
`define AHBW 32
|
||||
|
||||
// Test modes
|
||||
|
||||
// Tie GPIO outputs back to inputs
|
||||
`define GPIO_LOOPBACK_TEST 1
|
||||
|
||||
// Hardware configuration
|
||||
`define UART_PRESCALE 1
|
||||
|
||||
// Interrupt configuration
|
||||
`define PLIC_NUM_SRC 10
|
||||
// comment out the following if >=32 sources
|
||||
`define PLIC_NUM_SRC_LT_32
|
||||
`define PLIC_GPIO_ID 3
|
||||
`define PLIC_UART_ID 10
|
||||
|
||||
`define BPRED_SUPPORTED 1
|
||||
`define BPRED_TYPE "BP_GSHARE" // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
|
||||
`define BPRED_SIZE 16
|
||||
`define BTB_SIZE 10
|
||||
|
||||
`define SVADU_SUPPORTED 1
|
||||
`define ZMMUL_SUPPORTED 0
|
||||
|
||||
// FPU division architecture
|
||||
`define RADIX 32'h4
|
||||
`define DIVCOPIES 32'h4
|
||||
|
||||
// bit manipulation
|
||||
`define ZBA_SUPPORTED 1
|
||||
`define ZBB_SUPPORTED 1
|
||||
`define ZBC_SUPPORTED 1
|
||||
`define ZBS_SUPPORTED 1
|
||||
|
||||
// Memory synthesis configuration
|
||||
`define USE_SRAM 0
|
||||
@ -1,155 +0,0 @@
|
||||
//////////////////////////////////////////
|
||||
// wally-config.vh
|
||||
//
|
||||
// Written: David_Harris@hmc.edu 4 January 2021
|
||||
// Modified:
|
||||
//
|
||||
// Purpose: Specify which features are configured
|
||||
// Macros to determine which modes are supported based on MISA
|
||||
//
|
||||
// A component of the Wally configurable RISC-V project.
|
||||
//
|
||||
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
//
|
||||
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||
// may obtain a copy of the License at
|
||||
//
|
||||
// https://solderpad.org/licenses/SHL-2.1/
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||
// either express or implied. See the License for the specific language governing permissions
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// include shared configuration
|
||||
`include "wally-shared.vh"
|
||||
|
||||
`define FPGA 0
|
||||
`define QEMU 0
|
||||
|
||||
// RV32 or RV64: XLEN = 32 or 64
|
||||
`define XLEN 32
|
||||
|
||||
// IEEE 754 compliance
|
||||
`define IEEE754 0
|
||||
|
||||
// I
|
||||
`define MISA (32'h00000104)
|
||||
`define ZICSR_SUPPORTED 0
|
||||
`define ZIFENCEI_SUPPORTED 0
|
||||
`define COUNTERS 32
|
||||
`define ZICOUNTERS_SUPPORTED 0
|
||||
`define ZFH_SUPPORTED 0
|
||||
`define SSTC_SUPPORTED 0
|
||||
|
||||
// LSU microarchitectural Features
|
||||
`define BUS_SUPPORTED 0
|
||||
`define DCACHE_SUPPORTED 0
|
||||
`define ICACHE_SUPPORTED 0
|
||||
`define VIRTMEM_SUPPORTED 0
|
||||
`define VECTORED_INTERRUPTS_SUPPORTED 1
|
||||
`define BIGENDIAN_SUPPORTED 0
|
||||
|
||||
// TLB configuration. Entries should be a power of 2
|
||||
`define ITLB_ENTRIES 32
|
||||
`define DTLB_ENTRIES 32
|
||||
|
||||
// Cache configuration. Sizes should be a power of two
|
||||
// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
|
||||
`define DCACHE_NUMWAYS 4
|
||||
`define DCACHE_WAYSIZEINBYTES 4096
|
||||
`define DCACHE_LINELENINBITS 512
|
||||
`define ICACHE_NUMWAYS 4
|
||||
`define ICACHE_WAYSIZEINBYTES 4096
|
||||
`define ICACHE_LINELENINBITS 512
|
||||
|
||||
// Integer Divider Configuration
|
||||
// IDIV_BITSPERCYCLE must be 1, 2, or 4
|
||||
`define IDIV_BITSPERCYCLE 4
|
||||
`define IDIV_ON_FPU 0
|
||||
|
||||
// Legal number of PMP entries are 0, 16, or 64
|
||||
`define PMP_ENTRIES 0
|
||||
|
||||
// Address space
|
||||
`define RESET_VECTOR 32'h80000000
|
||||
|
||||
// WFI Timeout Wait
|
||||
`define WFI_TIMEOUT_BIT 16
|
||||
|
||||
// Peripheral Addresses
|
||||
// Peripheral memory space extends from BASE to BASE+RANGE
|
||||
// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
|
||||
`define DTIM_SUPPORTED 1'b1
|
||||
`define DTIM_BASE 34'h80000000
|
||||
`define DTIM_RANGE 34'h007FFFFF
|
||||
`define IROM_SUPPORTED 1'b1
|
||||
`define IROM_BASE 34'h80000000
|
||||
`define IROM_RANGE 34'h007FFFFF
|
||||
`define BOOTROM_SUPPORTED 1'b0
|
||||
`define BOOTROM_BASE 34'h00001000
|
||||
`define BOOTROM_RANGE 34'h00000FFF
|
||||
`define UNCORE_RAM_SUPPORTED 1'b0
|
||||
`define UNCORE_RAM_BASE 34'h80000000
|
||||
`define UNCORE_RAM_RANGE 34'h07FFFFFF
|
||||
`define EXT_MEM_SUPPORTED 1'b0
|
||||
`define EXT_MEM_BASE 34'h80000000
|
||||
`define EXT_MEM_RANGE 34'h07FFFFFF
|
||||
`define CLINT_SUPPORTED 1'b0
|
||||
`define CLINT_BASE 34'h02000000
|
||||
`define CLINT_RANGE 34'h0000FFFF
|
||||
`define GPIO_SUPPORTED 1'b0
|
||||
`define GPIO_BASE 34'h10060000
|
||||
`define GPIO_RANGE 34'h000000FF
|
||||
`define UART_SUPPORTED 1'b0
|
||||
`define UART_BASE 34'h10000000
|
||||
`define UART_RANGE 34'h00000007
|
||||
`define PLIC_SUPPORTED 1'b0
|
||||
`define PLIC_BASE 34'h0C000000
|
||||
`define PLIC_RANGE 34'h03FFFFFF
|
||||
`define SDC_SUPPORTED 1'b0
|
||||
`define SDC_BASE 34'h00012100
|
||||
`define SDC_RANGE 34'h0000001F
|
||||
|
||||
// Bus Interface width
|
||||
`define AHBW 32
|
||||
|
||||
// Test modes
|
||||
|
||||
// Tie GPIO outputs back to inputs
|
||||
`define GPIO_LOOPBACK_TEST 1
|
||||
|
||||
// Hardware configuration
|
||||
`define UART_PRESCALE 1
|
||||
|
||||
// Interrupt configuration
|
||||
`define PLIC_NUM_SRC 10
|
||||
// comment out the following if >=32 sources
|
||||
`define PLIC_NUM_SRC_LT_32
|
||||
`define PLIC_GPIO_ID 3
|
||||
`define PLIC_UART_ID 10
|
||||
|
||||
`define BPRED_SUPPORTED 0
|
||||
`define BPRED_TYPE "BP_GSHARE" // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
|
||||
`define BPRED_SIZE 10
|
||||
`define BTB_SIZE 10
|
||||
|
||||
`define SVADU_SUPPORTED 0
|
||||
`define ZMMUL_SUPPORTED 0
|
||||
|
||||
// FPU division architecture
|
||||
`define RADIX 32'h4
|
||||
`define DIVCOPIES 32'h4
|
||||
|
||||
// bit manipulation
|
||||
`define ZBA_SUPPORTED 0
|
||||
`define ZBB_SUPPORTED 0
|
||||
`define ZBC_SUPPORTED 0
|
||||
`define ZBS_SUPPORTED 0
|
||||
|
||||
// Memory synthesis configuration
|
||||
`define USE_SRAM 0
|
||||
@ -1,154 +0,0 @@
|
||||
//////////////////////////////////////////
|
||||
// wally-config.vh
|
||||
//
|
||||
// Written: David_Harris@hmc.edu 4 January 2021
|
||||
// Modified:
|
||||
//
|
||||
// Purpose: Specify which features are configured
|
||||
// Macros to determine which modes are supported based on MISA
|
||||
//
|
||||
// A component of the Wally configurable RISC-V project.
|
||||
//
|
||||
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
//
|
||||
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||
// may obtain a copy of the License at
|
||||
//
|
||||
// https://solderpad.org/licenses/SHL-2.1/
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||
// either express or implied. See the License for the specific language governing permissions
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// include shared configuration
|
||||
`include "wally-shared.vh"
|
||||
|
||||
`define FPGA 0
|
||||
`define QEMU 0
|
||||
|
||||
// RV32 or RV64: XLEN = 32 or 64
|
||||
`define XLEN 32
|
||||
|
||||
// IEEE 754 compliance
|
||||
`define IEEE754 0
|
||||
|
||||
`define MISA (32'h00000104 | 1 << 20 | 1 << 18 | 1 << 12)
|
||||
`define ZICSR_SUPPORTED 1
|
||||
`define ZIFENCEI_SUPPORTED 1
|
||||
`define COUNTERS 32
|
||||
`define ZICOUNTERS_SUPPORTED 1
|
||||
`define ZFH_SUPPORTED 0
|
||||
`define SSTC_SUPPORTED 0
|
||||
|
||||
// LSU microarchitectural Features
|
||||
`define BUS_SUPPORTED 1
|
||||
`define DCACHE_SUPPORTED 0
|
||||
`define ICACHE_SUPPORTED 0
|
||||
`define VIRTMEM_SUPPORTED 0
|
||||
`define VECTORED_INTERRUPTS_SUPPORTED 1
|
||||
`define BIGENDIAN_SUPPORTED 0
|
||||
|
||||
// TLB configuration. Entries should be a power of 2
|
||||
`define ITLB_ENTRIES 0
|
||||
`define DTLB_ENTRIES 0
|
||||
|
||||
// Cache configuration. Sizes should be a power of two
|
||||
// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
|
||||
`define DCACHE_NUMWAYS 4
|
||||
`define DCACHE_WAYSIZEINBYTES 4096
|
||||
`define DCACHE_LINELENINBITS 512
|
||||
`define ICACHE_NUMWAYS 4
|
||||
`define ICACHE_WAYSIZEINBYTES 4096
|
||||
`define ICACHE_LINELENINBITS 512
|
||||
|
||||
// Integer Divider Configuration
|
||||
// IDIV_BITSPERCYCLE must be 1, 2, or 4
|
||||
`define IDIV_BITSPERCYCLE 2
|
||||
`define IDIV_ON_FPU 0
|
||||
|
||||
// Legal number of PMP entries are 0, 16, or 64
|
||||
`define PMP_ENTRIES 0
|
||||
|
||||
// Address space
|
||||
`define RESET_VECTOR 32'h80000000
|
||||
|
||||
// WFI Timeout Wait
|
||||
`define WFI_TIMEOUT_BIT 16
|
||||
|
||||
// Peripheral Addresses
|
||||
// Peripheral memory space extends from BASE to BASE+RANGE
|
||||
// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
|
||||
`define DTIM_SUPPORTED 1'b1
|
||||
`define DTIM_BASE 34'h80000000
|
||||
`define DTIM_RANGE 34'h007FFFFF
|
||||
`define IROM_SUPPORTED 1'b1
|
||||
`define IROM_BASE 34'h80000000
|
||||
`define IROM_RANGE 34'h007FFFFF
|
||||
`define BOOTROM_SUPPORTED 1'b0
|
||||
`define BOOTROM_BASE 34'h00001000
|
||||
`define BOOTROM_RANGE 34'h00000FFF
|
||||
`define UNCORE_RAM_SUPPORTED 1'b0
|
||||
`define UNCORE_RAM_BASE 34'h80000000
|
||||
`define UNCORE_RAM_RANGE 34'h07FFFFFF
|
||||
`define EXT_MEM_SUPPORTED 1'b0
|
||||
`define EXT_MEM_BASE 34'h80000000
|
||||
`define EXT_MEM_RANGE 34'h07FFFFFF
|
||||
`define CLINT_SUPPORTED 1'b1
|
||||
`define CLINT_BASE 34'h02000000
|
||||
`define CLINT_RANGE 34'h0000FFFF
|
||||
`define GPIO_SUPPORTED 1'b1
|
||||
`define GPIO_BASE 34'h10060000
|
||||
`define GPIO_RANGE 34'h000000FF
|
||||
`define UART_SUPPORTED 1'b1
|
||||
`define UART_BASE 34'h10000000
|
||||
`define UART_RANGE 34'h00000007
|
||||
`define PLIC_SUPPORTED 1'b1
|
||||
`define PLIC_BASE 34'h0C000000
|
||||
`define PLIC_RANGE 34'h03FFFFFF
|
||||
`define SDC_SUPPORTED 1'b0
|
||||
`define SDC_BASE 34'h00012100
|
||||
`define SDC_RANGE 34'h0000001F
|
||||
|
||||
// Bus Interface width
|
||||
`define AHBW 32
|
||||
|
||||
// Test modes
|
||||
|
||||
// Tie GPIO outputs back to inputs
|
||||
`define GPIO_LOOPBACK_TEST 1
|
||||
|
||||
// Hardware configuration
|
||||
`define UART_PRESCALE 1
|
||||
|
||||
// Interrupt configuration
|
||||
`define PLIC_NUM_SRC 10
|
||||
// comment out the following if >=32 sources
|
||||
`define PLIC_NUM_SRC_LT_32
|
||||
`define PLIC_GPIO_ID 3
|
||||
`define PLIC_UART_ID 10
|
||||
|
||||
`define BPRED_SUPPORTED 0
|
||||
`define BPRED_TYPE "BP_GSHARE" // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
|
||||
`define BPRED_SIZE 10
|
||||
`define BTB_SIZE 10
|
||||
|
||||
`define SVADU_SUPPORTED 0
|
||||
`define ZMMUL_SUPPORTED 0
|
||||
|
||||
// FPU division architecture
|
||||
`define RADIX 32'h4
|
||||
`define DIVCOPIES 32'h4
|
||||
|
||||
// bit manipulation
|
||||
`define ZBA_SUPPORTED 0
|
||||
`define ZBB_SUPPORTED 0
|
||||
`define ZBC_SUPPORTED 0
|
||||
`define ZBS_SUPPORTED 0
|
||||
|
||||
// Memory synthesis configuration
|
||||
`define USE_SRAM 0
|
||||
@ -1,157 +0,0 @@
|
||||
//////////////////////////////////////////
|
||||
// wally-config.vh
|
||||
//
|
||||
// Written: David_Harris@hmc.edu 4 January 2021
|
||||
// Modified:
|
||||
//
|
||||
// Purpose: Specify which features are configured
|
||||
// Macros to determine which modes are supported based on MISA
|
||||
//
|
||||
// A component of the Wally configurable RISC-V project.
|
||||
//
|
||||
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
//
|
||||
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||
// may obtain a copy of the License at
|
||||
//
|
||||
// https://solderpad.org/licenses/SHL-2.1/
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||
// either express or implied. See the License for the specific language governing permissions
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// include shared configuration
|
||||
`include "wally-shared.vh"
|
||||
|
||||
`define FPGA 0
|
||||
`define QEMU 0
|
||||
|
||||
// RV32 or RV64: XLEN = 32 or 64
|
||||
`define XLEN 64
|
||||
|
||||
// IEEE 754 compliance
|
||||
`define IEEE754 0
|
||||
|
||||
// MISA RISC-V configuration per specification
|
||||
`define MISA (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 16 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0 )
|
||||
`define ZICSR_SUPPORTED 1
|
||||
`define ZIFENCEI_SUPPORTED 1
|
||||
`define COUNTERS 32
|
||||
`define ZICOUNTERS_SUPPORTED 1
|
||||
`define ZFH_SUPPORTED 1
|
||||
`define SSTC_SUPPORTED 0
|
||||
|
||||
// LSU microarchitectural Features
|
||||
`define BUS_SUPPORTED 1
|
||||
`define DCACHE_SUPPORTED 1
|
||||
`define ICACHE_SUPPORTED 1
|
||||
`define VIRTMEM_SUPPORTED 1
|
||||
`define VECTORED_INTERRUPTS_SUPPORTED 1
|
||||
`define BIGENDIAN_SUPPORTED 1
|
||||
|
||||
// TLB configuration. Entries should be a power of 2
|
||||
`define ITLB_ENTRIES 32
|
||||
`define DTLB_ENTRIES 32
|
||||
|
||||
// Cache configuration. Sizes should be a power of two
|
||||
// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
|
||||
`define DCACHE_NUMWAYS 4
|
||||
`define DCACHE_WAYSIZEINBYTES 4096
|
||||
`define DCACHE_LINELENINBITS 512
|
||||
`define ICACHE_NUMWAYS 4
|
||||
`define ICACHE_WAYSIZEINBYTES 4096
|
||||
`define ICACHE_LINELENINBITS 512
|
||||
|
||||
// Integer Divider Configuration
|
||||
// IDIV_BITSPERCYCLE must be 1, 2, or 4
|
||||
`define IDIV_BITSPERCYCLE 4
|
||||
`define IDIV_ON_FPU 1
|
||||
|
||||
// Legal number of PMP entries are 0, 16, or 64
|
||||
`define PMP_ENTRIES 16
|
||||
|
||||
// Address space
|
||||
`define RESET_VECTOR 64'h0000000080000000
|
||||
|
||||
// Bus Interface width
|
||||
`define AHBW 64
|
||||
|
||||
// WFI Timeout Wait
|
||||
`define WFI_TIMEOUT_BIT 16
|
||||
|
||||
// Peripheral Physiccal Addresses
|
||||
// Peripheral memory space extends from BASE to BASE+RANGE
|
||||
// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
|
||||
|
||||
// *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file?
|
||||
`define DTIM_SUPPORTED 1'b0
|
||||
`define DTIM_BASE 56'h80000000
|
||||
`define DTIM_RANGE 56'h007FFFFF
|
||||
`define IROM_SUPPORTED 1'b0
|
||||
`define IROM_BASE 56'h80000000
|
||||
`define IROM_RANGE 56'h007FFFFF
|
||||
`define BOOTROM_SUPPORTED 1'b1
|
||||
`define BOOTROM_BASE 56'h00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder
|
||||
`define BOOTROM_RANGE 56'h00000FFF
|
||||
`define UNCORE_RAM_SUPPORTED 1'b1
|
||||
`define UNCORE_RAM_BASE 56'h80000000
|
||||
`define UNCORE_RAM_RANGE 56'h7FFFFFFF
|
||||
`define EXT_MEM_SUPPORTED 1'b0
|
||||
`define EXT_MEM_BASE 56'h80000000
|
||||
`define EXT_MEM_RANGE 56'h07FFFFFF
|
||||
`define CLINT_SUPPORTED 1'b1
|
||||
`define CLINT_BASE 56'h02000000
|
||||
`define CLINT_RANGE 56'h0000FFFF
|
||||
`define GPIO_SUPPORTED 1'b1
|
||||
`define GPIO_BASE 56'h10060000
|
||||
`define GPIO_RANGE 56'h000000FF
|
||||
`define UART_SUPPORTED 1'b1
|
||||
`define UART_BASE 56'h10000000
|
||||
`define UART_RANGE 56'h00000007
|
||||
`define PLIC_SUPPORTED 1'b1
|
||||
`define PLIC_BASE 56'h0C000000
|
||||
`define PLIC_RANGE 56'h03FFFFFF
|
||||
`define SDC_SUPPORTED 1'b0
|
||||
`define SDC_BASE 56'h00012100
|
||||
`define SDC_RANGE 56'h0000001F
|
||||
|
||||
// Test modes
|
||||
|
||||
// Tie GPIO outputs back to inputs
|
||||
`define GPIO_LOOPBACK_TEST 1
|
||||
|
||||
// Hardware configuration
|
||||
`define UART_PRESCALE 1
|
||||
|
||||
// Interrupt configuration
|
||||
`define PLIC_NUM_SRC 10
|
||||
// comment out the following if >=32 sources
|
||||
`define PLIC_NUM_SRC_LT_32
|
||||
`define PLIC_GPIO_ID 3
|
||||
`define PLIC_UART_ID 10
|
||||
|
||||
`define BPRED_SUPPORTED 1
|
||||
`define BPRED_TYPE "BP_GSHARE" // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
|
||||
`define BPRED_SIZE 10
|
||||
`define BTB_SIZE 10
|
||||
|
||||
`define SVADU_SUPPORTED 0
|
||||
`define ZMMUL_SUPPORTED 0
|
||||
|
||||
// FPU division architecture
|
||||
`define RADIX 32'h4
|
||||
`define DIVCOPIES 32'h4
|
||||
|
||||
// bit manipulation
|
||||
`define ZBA_SUPPORTED 0
|
||||
`define ZBB_SUPPORTED 0
|
||||
`define ZBC_SUPPORTED 0
|
||||
`define ZBS_SUPPORTED 0
|
||||
|
||||
// Memory synthesis configuration
|
||||
`define USE_SRAM 0
|
||||
@ -1,157 +0,0 @@
|
||||
//////////////////////////////////////////
|
||||
// wally-config.vh
|
||||
//
|
||||
// Written: David_Harris@hmc.edu 4 January 2021
|
||||
// Modified:
|
||||
//
|
||||
// Purpose: Specify which features are configured
|
||||
// Macros to determine which modes are supported based on MISA
|
||||
//
|
||||
// A component of the Wally configurable RISC-V project.
|
||||
//
|
||||
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
//
|
||||
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||
// may obtain a copy of the License at
|
||||
//
|
||||
// https://solderpad.org/licenses/SHL-2.1/
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||
// either express or implied. See the License for the specific language governing permissions
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// include shared configuration
|
||||
`include "wally-shared.vh"
|
||||
|
||||
`define FPGA 0
|
||||
`define QEMU 0
|
||||
|
||||
// RV32 or RV64: XLEN = 32 or 64
|
||||
`define XLEN 64
|
||||
|
||||
// IEEE 754 compliance
|
||||
`define IEEE754 0
|
||||
|
||||
// MISA RISC-V configuration per specification
|
||||
`define MISA (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0 )
|
||||
`define ZICSR_SUPPORTED 1
|
||||
`define ZIFENCEI_SUPPORTED 1
|
||||
`define COUNTERS 32
|
||||
`define ZICOUNTERS_SUPPORTED 1
|
||||
`define ZFH_SUPPORTED 0
|
||||
`define SSTC_SUPPORTED 1
|
||||
|
||||
// LSU microarchitectural Features
|
||||
`define BUS_SUPPORTED 1
|
||||
`define DCACHE_SUPPORTED 1
|
||||
`define ICACHE_SUPPORTED 1
|
||||
`define VIRTMEM_SUPPORTED 1
|
||||
`define VECTORED_INTERRUPTS_SUPPORTED 1
|
||||
`define BIGENDIAN_SUPPORTED 1
|
||||
|
||||
// TLB configuration. Entries should be a power of 2
|
||||
`define ITLB_ENTRIES 32
|
||||
`define DTLB_ENTRIES 32
|
||||
|
||||
// Cache configuration. Sizes should be a power of two
|
||||
// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
|
||||
`define DCACHE_NUMWAYS 4
|
||||
`define DCACHE_WAYSIZEINBYTES 4096
|
||||
`define DCACHE_LINELENINBITS 512
|
||||
`define ICACHE_NUMWAYS 4
|
||||
`define ICACHE_WAYSIZEINBYTES 4096
|
||||
`define ICACHE_LINELENINBITS 512
|
||||
|
||||
// Integer Divider Configuration
|
||||
// IDIV_BITSPERCYCLE must be 1, 2, or 4
|
||||
`define IDIV_BITSPERCYCLE 4
|
||||
`define IDIV_ON_FPU 1
|
||||
|
||||
// Legal number of PMP entries are 0, 16, or 64
|
||||
`define PMP_ENTRIES 16
|
||||
|
||||
// Address space
|
||||
`define RESET_VECTOR 64'h0000000080000000
|
||||
|
||||
// Bus Interface width
|
||||
`define AHBW 64
|
||||
|
||||
// WFI Timeout Wait
|
||||
`define WFI_TIMEOUT_BIT 16
|
||||
|
||||
// Peripheral Physical Addresses
|
||||
// Peripheral memory space extends from BASE to BASE+RANGE
|
||||
// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
|
||||
|
||||
// *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file?
|
||||
`define DTIM_SUPPORTED 1'b0
|
||||
`define DTIM_BASE 56'h80000000
|
||||
`define DTIM_RANGE 56'h007FFFFF
|
||||
`define IROM_SUPPORTED 1'b0
|
||||
`define IROM_BASE 56'h80000000
|
||||
`define IROM_RANGE 56'h007FFFFF
|
||||
`define BOOTROM_SUPPORTED 1'b1
|
||||
`define BOOTROM_BASE 56'h00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder
|
||||
`define BOOTROM_RANGE 56'h00000FFF
|
||||
`define UNCORE_RAM_SUPPORTED 1'b1
|
||||
`define UNCORE_RAM_BASE 56'h80000000
|
||||
`define UNCORE_RAM_RANGE 56'h7FFFFFFF
|
||||
`define EXT_MEM_SUPPORTED 1'b0
|
||||
`define EXT_MEM_BASE 56'h80000000
|
||||
`define EXT_MEM_RANGE 56'h07FFFFFF
|
||||
`define CLINT_SUPPORTED 1'b1
|
||||
`define CLINT_BASE 56'h02000000
|
||||
`define CLINT_RANGE 56'h0000FFFF
|
||||
`define GPIO_SUPPORTED 1'b1
|
||||
`define GPIO_BASE 56'h10060000
|
||||
`define GPIO_RANGE 56'h000000FF
|
||||
`define UART_SUPPORTED 1'b1
|
||||
`define UART_BASE 56'h10000000
|
||||
`define UART_RANGE 56'h00000007
|
||||
`define PLIC_SUPPORTED 1'b1
|
||||
`define PLIC_BASE 56'h0C000000
|
||||
`define PLIC_RANGE 56'h03FFFFFF
|
||||
`define SDC_SUPPORTED 1'b0
|
||||
`define SDC_BASE 56'h00012100
|
||||
`define SDC_RANGE 56'h0000001F
|
||||
|
||||
// Test modes
|
||||
|
||||
// Tie GPIO outputs back to inputs
|
||||
`define GPIO_LOOPBACK_TEST 1
|
||||
|
||||
// Hardware configuration
|
||||
`define UART_PRESCALE 1
|
||||
|
||||
// Interrupt configuration
|
||||
`define PLIC_NUM_SRC 10
|
||||
// comment out the following if >=32 sources
|
||||
`define PLIC_NUM_SRC_LT_32
|
||||
`define PLIC_GPIO_ID 3
|
||||
`define PLIC_UART_ID 10
|
||||
|
||||
`define BPRED_SUPPORTED 1
|
||||
`define BPRED_TYPE "BP_GSHARE" // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
|
||||
`define BPRED_SIZE 10
|
||||
`define BTB_SIZE 10
|
||||
|
||||
`define SVADU_SUPPORTED 1
|
||||
`define ZMMUL_SUPPORTED 0
|
||||
|
||||
// FPU division architecture
|
||||
`define RADIX 32'h4
|
||||
`define DIVCOPIES 32'h4
|
||||
|
||||
// bit manipulation
|
||||
`define ZBA_SUPPORTED 1
|
||||
`define ZBB_SUPPORTED 1
|
||||
`define ZBC_SUPPORTED 1
|
||||
`define ZBS_SUPPORTED 1
|
||||
|
||||
// Memory synthesis configuration
|
||||
`define USE_SRAM 0
|
||||
@ -1,157 +0,0 @@
|
||||
//////////////////////////////////////////
|
||||
// wally-config.vh
|
||||
//
|
||||
// Written: David_Harris@hmc.edu 4 January 2021
|
||||
// Modified:
|
||||
//
|
||||
// Purpose: Specify which features are configured
|
||||
// Macros to determine which modes are supported based on MISA
|
||||
//
|
||||
// A component of the Wally configurable RISC-V project.
|
||||
//
|
||||
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
//
|
||||
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||
// may obtain a copy of the License at
|
||||
//
|
||||
// https://solderpad.org/licenses/SHL-2.1/
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||
// either express or implied. See the License for the specific language governing permissions
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// include shared configuration
|
||||
`include "wally-shared.vh"
|
||||
|
||||
`define FPGA 0
|
||||
`define QEMU 0
|
||||
|
||||
// RV32 or RV64: XLEN = 32 or 64
|
||||
`define XLEN 64
|
||||
|
||||
// IEEE 754 compliance
|
||||
`define IEEE754 0
|
||||
|
||||
// MISA RISC-V configuration per specification
|
||||
`define MISA (32'h00000104)
|
||||
`define ZICSR_SUPPORTED 0
|
||||
`define ZIFENCEI_SUPPORTED 0
|
||||
`define COUNTERS 32
|
||||
`define ZICOUNTERS_SUPPORTED 0
|
||||
`define ZFH_SUPPORTED 0
|
||||
`define SSTC_SUPPORTED 0
|
||||
|
||||
// LSU microarchitectural Features
|
||||
`define BUS_SUPPORTED 0
|
||||
`define DCACHE_SUPPORTED 0
|
||||
`define ICACHE_SUPPORTED 0
|
||||
`define VIRTMEM_SUPPORTED 0
|
||||
`define VECTORED_INTERRUPTS_SUPPORTED 1
|
||||
`define BIGENDIAN_SUPPORTED 0
|
||||
|
||||
// TLB configuration. Entries should be a power of 2
|
||||
`define ITLB_ENTRIES 0
|
||||
`define DTLB_ENTRIES 0
|
||||
|
||||
// Cache configuration. Sizes should be a power of two
|
||||
// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
|
||||
`define DCACHE_NUMWAYS 4
|
||||
`define DCACHE_WAYSIZEINBYTES 4096
|
||||
`define DCACHE_LINELENINBITS 512
|
||||
`define ICACHE_NUMWAYS 4
|
||||
`define ICACHE_WAYSIZEINBYTES 4096
|
||||
`define ICACHE_LINELENINBITS 512
|
||||
|
||||
// Integer Divider Configuration
|
||||
// IDIV_BITSPERCYCLE must be 1, 2, or 4
|
||||
`define IDIV_BITSPERCYCLE 4
|
||||
`define IDIV_ON_FPU 0
|
||||
|
||||
// Legal number of PMP entries are 0, 16, or 64
|
||||
`define PMP_ENTRIES 0
|
||||
|
||||
// Address space
|
||||
`define RESET_VECTOR 64'h0000000080000000
|
||||
|
||||
// Bus Interface width
|
||||
`define AHBW (`XLEN)
|
||||
|
||||
// WFI Timeout Wait
|
||||
`define WFI_TIMEOUT_BIT 16
|
||||
|
||||
// Peripheral Physiccal Addresses
|
||||
// Peripheral memory space extends from BASE to BASE+RANGE
|
||||
// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
|
||||
|
||||
// *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file?
|
||||
`define DTIM_SUPPORTED 1'b1
|
||||
`define DTIM_BASE 56'h80000000
|
||||
`define DTIM_RANGE 56'h007FFFFF
|
||||
`define IROM_SUPPORTED 1'b1
|
||||
`define IROM_BASE 56'h80000000
|
||||
`define IROM_RANGE 56'h007FFFFF
|
||||
`define BOOTROM_SUPPORTED 1'b0
|
||||
`define BOOTROM_BASE 56'h00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder
|
||||
`define BOOTROM_RANGE 56'h00000FFF
|
||||
`define UNCORE_RAM_SUPPORTED 1'b0
|
||||
`define UNCORE_RAM_BASE 56'h80000000
|
||||
`define UNCORE_RAM_RANGE 56'h7FFFFFFF
|
||||
`define EXT_MEM_SUPPORTED 1'b0
|
||||
`define EXT_MEM_BASE 56'h80000000
|
||||
`define EXT_MEM_RANGE 56'h07FFFFFF
|
||||
`define CLINT_SUPPORTED 1'b0
|
||||
`define CLINT_BASE 56'h02000000
|
||||
`define CLINT_RANGE 56'h0000FFFF
|
||||
`define GPIO_SUPPORTED 1'b0
|
||||
`define GPIO_BASE 56'h10060000
|
||||
`define GPIO_RANGE 56'h000000FF
|
||||
`define UART_SUPPORTED 1'b0
|
||||
`define UART_BASE 56'h10000000
|
||||
`define UART_RANGE 56'h00000007
|
||||
`define PLIC_SUPPORTED 1'b0
|
||||
`define PLIC_BASE 56'h0C000000
|
||||
`define PLIC_RANGE 56'h03FFFFFF
|
||||
`define SDC_SUPPORTED 1'b0
|
||||
`define SDC_BASE 56'h00012100
|
||||
`define SDC_RANGE 56'h0000001F
|
||||
|
||||
// Test modes
|
||||
|
||||
// Tie GPIO outputs back to inputs
|
||||
`define GPIO_LOOPBACK_TEST 1
|
||||
|
||||
// Hardware configuration
|
||||
`define UART_PRESCALE 1
|
||||
|
||||
// Interrupt configuration
|
||||
`define PLIC_NUM_SRC 10
|
||||
// comment out the following if >=32 sources
|
||||
`define PLIC_NUM_SRC_LT_32
|
||||
`define PLIC_GPIO_ID 3
|
||||
`define PLIC_UART_ID 10
|
||||
|
||||
`define BPRED_SUPPORTED 0
|
||||
`define BPRED_TYPE "BP_GSHARE" // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
|
||||
`define BPRED_SIZE 10
|
||||
`define BTB_SIZE 10
|
||||
|
||||
`define SVADU_SUPPORTED 0
|
||||
`define ZMMUL_SUPPORTED 0
|
||||
|
||||
// FPU division architecture
|
||||
`define RADIX 32'h4
|
||||
`define DIVCOPIES 32'h4
|
||||
|
||||
// bit manipulation
|
||||
`define ZBA_SUPPORTED 0
|
||||
`define ZBB_SUPPORTED 0
|
||||
`define ZBC_SUPPORTED 0
|
||||
`define ZBS_SUPPORTED 0
|
||||
|
||||
// Memory synthesis configuration
|
||||
`define USE_SRAM 0
|
||||
@ -1,142 +0,0 @@
|
||||
//////////////////////////////////////////
|
||||
// wally-shared.vh
|
||||
//
|
||||
// Written: david_harris@hmc.edu 7 June 2021
|
||||
//
|
||||
// Purpose: Shared and default configuration values common to all designs
|
||||
//
|
||||
// A component of the Wally configurable RISC-V project.
|
||||
//
|
||||
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
//
|
||||
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||
// may obtain a copy of the License at
|
||||
//
|
||||
// https://solderpad.org/licenses/SHL-2.1/
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||
// either express or implied. See the License for the specific language governing permissions
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// constants defining different privilege modes
|
||||
// defined in Table 1.1 of the privileged spec
|
||||
`define M_MODE (2'b11)
|
||||
`define S_MODE (2'b01)
|
||||
`define U_MODE (2'b00)
|
||||
|
||||
// Virtual Memory Constants
|
||||
`define VPN_SEGMENT_BITS (`XLEN == 32 ? 10 : 9)
|
||||
`define VPN_BITS (`XLEN==32 ? (2*`VPN_SEGMENT_BITS) : (4*`VPN_SEGMENT_BITS))
|
||||
`define PPN_BITS (`XLEN==32 ? 22 : 44)
|
||||
`define PA_BITS (`XLEN==32 ? 34 : 56)
|
||||
`define SVMODE_BITS (`XLEN==32 ? 1 : 4)
|
||||
`define ASID_BASE (`XLEN==32 ? 22 : 44)
|
||||
`define ASID_BITS (`XLEN==32 ? 9 : 16)
|
||||
|
||||
// constants to check SATP_MODE against
|
||||
// defined in Table 4.3 of the privileged spec
|
||||
`define NO_TRANSLATE 0
|
||||
`define SV32 1
|
||||
`define SV39 8
|
||||
`define SV48 9
|
||||
|
||||
// macros to define supported modes
|
||||
`define A_SUPPORTED ((`MISA >> 0) % 2 == 1)
|
||||
`define B_SUPPORTED ((`ZBA_SUPPORTED | `ZBB_SUPPORTED | `ZBC_SUPPORTED | `ZBS_SUPPORTED)) // not based on MISA
|
||||
`define C_SUPPORTED ((`MISA >> 2) % 2 == 1)
|
||||
`define D_SUPPORTED ((`MISA >> 3) % 2 == 1)
|
||||
`define E_SUPPORTED ((`MISA >> 4) % 2 == 1)
|
||||
`define F_SUPPORTED ((`MISA >> 5) % 2 == 1)
|
||||
`define I_SUPPORTED ((`MISA >> 8) % 2 == 1)
|
||||
`define M_SUPPORTED ((`MISA >> 12) % 2 == 1)
|
||||
`define Q_SUPPORTED ((`MISA >> 16) % 2 == 1)
|
||||
`define S_SUPPORTED ((`MISA >> 18) % 2 == 1)
|
||||
`define U_SUPPORTED ((`MISA >> 20) % 2 == 1)
|
||||
// N-mode user-level interrupts are depricated per Andrew Waterman 1/13/21
|
||||
|
||||
// logarithm of XLEN, used for number of index bits to select
|
||||
`define LOG_XLEN (`XLEN == 32 ? 5 : 6)
|
||||
|
||||
// Number of 64 bit PMP Configuration Register entries (or pairs of 32 bit entries)
|
||||
`define PMPCFG_ENTRIES (`PMP_ENTRIES/8)
|
||||
|
||||
// Floating point constants for Quad, Double, Single, and Half precisions
|
||||
`define Q_LEN 32'd128
|
||||
`define Q_NE 32'd15
|
||||
`define Q_NF 32'd112
|
||||
`define Q_BIAS 32'd16383
|
||||
`define Q_FMT 2'd3
|
||||
`define D_LEN 32'd64
|
||||
`define D_NE 32'd11
|
||||
`define D_NF 32'd52
|
||||
`define D_BIAS 32'd1023
|
||||
`define D_FMT 2'd1
|
||||
`define S_LEN 32'd32
|
||||
`define S_NE 32'd8
|
||||
`define S_NF 32'd23
|
||||
`define S_BIAS 32'd127
|
||||
`define S_FMT 2'd0
|
||||
`define H_LEN 32'd16
|
||||
`define H_NE 32'd5
|
||||
`define H_NF 32'd10
|
||||
`define H_BIAS 32'd15
|
||||
`define H_FMT 2'd2
|
||||
|
||||
// Floating point length FLEN and number of exponent (NE) and fraction (NF) bits
|
||||
`define FLEN (`Q_SUPPORTED ? `Q_LEN : `D_SUPPORTED ? `D_LEN : `S_LEN)
|
||||
`define NE (`Q_SUPPORTED ? `Q_NE : `D_SUPPORTED ? `D_NE : `S_NE)
|
||||
`define NF (`Q_SUPPORTED ? `Q_NF : `D_SUPPORTED ? `D_NF : `S_NF)
|
||||
`define FMT (`Q_SUPPORTED ? 2'd3 : `D_SUPPORTED ? 2'd1 : 2'd0)
|
||||
`define BIAS (`Q_SUPPORTED ? `Q_BIAS : `D_SUPPORTED ? `D_BIAS : `S_BIAS)
|
||||
/* Delete once tested dh 10/10/22
|
||||
|
||||
`define FLEN (`Q_SUPPORTED ? `Q_LEN : `D_SUPPORTED ? `D_LEN : `F_SUPPORTED ? `S_LEN : `H_LEN)
|
||||
`define NE (`Q_SUPPORTED ? `Q_NE : `D_SUPPORTED ? `D_NE : `F_SUPPORTED ? `S_NE : `H_NE)
|
||||
`define NF (`Q_SUPPORTED ? `Q_NF : `D_SUPPORTED ? `D_NF : `F_SUPPORTED ? `S_NF : `H_NF)
|
||||
`define FMT (`Q_SUPPORTED ? 2'd3 : `D_SUPPORTED ? 2'd1 : `F_SUPPORTED ? 2'd0 : 2'd2)
|
||||
`define BIAS (`Q_SUPPORTED ? `Q_BIAS : `D_SUPPORTED ? `D_BIAS : `F_SUPPORTED ? `S_BIAS : `H_BIAS)*/
|
||||
|
||||
// Floating point constants needed for FPU paramerterization
|
||||
`define FPSIZES ((32)'(`Q_SUPPORTED)+(32)'(`D_SUPPORTED)+(32)'(`F_SUPPORTED)+(32)'(`ZFH_SUPPORTED))
|
||||
`define FMTBITS ((32)'(`FPSIZES>=3)+1)
|
||||
`define LEN1 ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_LEN : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_LEN : `H_LEN)
|
||||
`define NE1 ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_NE : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_NE : `H_NE)
|
||||
`define NF1 ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_NF : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_NF : `H_NF)
|
||||
`define FMT1 ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? 2'd1 : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? 2'd0 : 2'd2)
|
||||
`define BIAS1 ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_BIAS : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_BIAS : `H_BIAS)
|
||||
`define LEN2 ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? `S_LEN : `H_LEN)
|
||||
`define NE2 ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? `S_NE : `H_NE)
|
||||
`define NF2 ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? `S_NF : `H_NF)
|
||||
`define FMT2 ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? 2'd0 : 2'd2)
|
||||
`define BIAS2 ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? `S_BIAS : `H_BIAS)
|
||||
|
||||
// largest length in IEU/FPU
|
||||
`define CVTLEN ((`NF<`XLEN) ? (`XLEN) : (`NF))
|
||||
`define LLEN (($unsigned(`FLEN)<$unsigned(`XLEN)) ? ($unsigned(`XLEN)) : ($unsigned(`FLEN)))
|
||||
`define LOGCVTLEN $unsigned($clog2(`CVTLEN+1))
|
||||
`define NORMSHIFTSZ (((`CVTLEN+`NF+1)>(`DIVb + 1 +`NF+1) & (`CVTLEN+`NF+1)>(3*`NF+6)) ? (`CVTLEN+`NF+1) : ((`DIVb + 1 +`NF+1) > (3*`NF+6) ? (`DIVb + 1 +`NF+1) : (3*`NF+6)))
|
||||
`define LOGNORMSHIFTSZ ($clog2(`NORMSHIFTSZ))
|
||||
`define CORRSHIFTSZ (((`CVTLEN+`NF+1)>(`DIVb + 1 +`NF+1) & (`CVTLEN+`NF+1)>(3*`NF+6)) ? (`CVTLEN+`NF+1) : ((`DIVN+1+`NF) > (3*`NF+4) ? (`DIVN+1+`NF) : (3*`NF+4)))
|
||||
|
||||
// division constants
|
||||
|
||||
`define DIVN (((`NF<`XLEN) & `IDIV_ON_FPU) ? `XLEN : `NF+2) // standard length of input
|
||||
`define LOGR ($clog2(`RADIX)) // r = log(R)
|
||||
`define RK (`LOGR*`DIVCOPIES) // r*k used for intdiv preproc
|
||||
`define LOGRK ($clog2(`RK)) // log2(r*k)
|
||||
`define FPDUR ((`DIVN+1+(`LOGR*`DIVCOPIES))/(`LOGR*`DIVCOPIES)+(`RADIX/4))
|
||||
`define DURLEN ($clog2(`FPDUR+1))
|
||||
`define DIVb (`FPDUR*`LOGR*`DIVCOPIES-1) // canonical fdiv size (b)
|
||||
`define DIVBLEN ($clog2(`DIVb+1)-1)
|
||||
`define DIVa (`DIVb+1-`XLEN) // used for idiv on fpu
|
||||
|
||||
// Disable spurious Verilator warnings
|
||||
|
||||
/* verilator lint_off STMTDLY */
|
||||
/* verilator lint_off ASSIGNDLY */
|
||||
/* verilator lint_off PINCONNECTEMPTY */
|
||||
@ -1,206 +0,0 @@
|
||||
D Wally Toolchain Docker Container
|
||||
|
||||
Installing RISC-V tools from source gives you maximum control, but has several disadvantages:
|
||||
|
||||
* Building the executables takes several hours.
|
||||
* Linux is poorly standardized, and the build steps might not work on your version
|
||||
* The source files are constantly changing, and the versions you download might not be compatible with this textbook flow.
|
||||
|
||||
Docker is a tools to run applications in a prepackaged container including all of the operating system support required. Wally offers a ~30GB container image with the open-source tools pre-installed from Section D.1. In particular, using the container solves the long build time for gcc and the fussy installation of sail. The container runs on any platform supporting Docker, including Windows and Mac as well as Linux. It can access files outside the container, including local installation of CAD tools such as Questa, and a local clone of the core-v-wally repository.
|
||||
|
||||
Docker can be run on most operating systems, including Linux, Windows, and Mac. The Wally Docker container is hosted at DockerHub (http://docker.io).
|
||||
|
||||
Podman is a more secure and easier-to-use variation of Docker for Linux developed by RedHat. Both Docker and Podman run the same containers.
|
||||
|
||||
D.3.1 Podman Installation on Linux
|
||||
|
||||
A system administrator must install Podman if it is not already present.
|
||||
|
||||
For Ubuntu 20.10 or later:
|
||||
|
||||
$ sudo apt-get -y install podman
|
||||
|
||||
For RedHat / Rocky:
|
||||
|
||||
$ sudo yum -y install podman
|
||||
|
||||
D.3.2 Pulling the Wally Container
|
||||
|
||||
Once Podman is installed, a user can pull the Wally container image. The user must sign up for a free account at docker.io, and will be prompted for the credentials when running podman login.
|
||||
|
||||
$ podman login docker.io
|
||||
$ podman pull docker.io/wallysoc/wally-docker:latest
|
||||
|
||||
D.3.3 Running the Docker Container in Podman
|
||||
|
||||
To activate podman with GUI support, first identify your display port in the /tmp/.X11-unix file as shown below. For example, the user ben is on port X51.
|
||||
|
||||
$ ls -la /tmp/.X11-unix/
|
||||
drwxrwxrwt 2 root root 4096 Jan 6 05:01 .
|
||||
drwxrwxrwt 122 root root 40960 Jan 17 08:09 ..
|
||||
srwxrwxrwx 1 root root 0 Jan 5 08:48 X0
|
||||
srwxrwxrwx 1 xwalter xwalter 0 Jan 5 09:21 X50
|
||||
srwxrwxrwx 1 ben ben 0 Jan 6 05:01 X51
|
||||
|
||||
Then run podman with the display number after the X (51 in this case). The -v options also mount the user’s home directory (/home/ben) and cad tools (/cad) to be visible from the container. Change these as necessary based on your local system configuration.
|
||||
|
||||
$ podman run -it --net=host -e DISPLAY=:51 -v /tmp/.X11-unix:/tmp/.X11-unix -v /home/ben:/home/ben -v /cad:/cad -p 8080:8080 docker.io/wallysoc/wally-docker
|
||||
|
||||
Podman sets up all the RISC-V software in the same location of /opt/riscv as the cad user as discussed previously. This shared directory is called $RISCV. This environmental variable should also be set up within the Docker container automatically and ready to use once the container is run. It is important to understand that Docker containers are self-contained, and any data created within your container is lost when you exit the container. Therefore, be sure to work in your mounted home directory (e.g. /home/ben) to permanently save your work outside the container.
|
||||
|
||||
To have permission to write to your mounted home directory, you must become root inside the Wally container. This is an acceptable practice as the security will be maintained within podman for the user that runs podman. To become root once inside your container:
|
||||
|
||||
$ su # when prompted for password, enter wally
|
||||
|
||||
D.3.4 Cleaning up a Podman Container
|
||||
|
||||
The Docker container image is large, so users may need to clean up a container when they aren’t using it anymore.
|
||||
The images that are loaded can be examined, once you pull the Wally container, by typing:
|
||||
|
||||
$ podman images
|
||||
|
||||
To remove individual podman images, the following Linux command will remove the specific podman image where the image name is obtained from the podman images command (this command also works equally well using the <Image_ID> instead of the <Image_name>, as well).
|
||||
|
||||
$ podman rmi -f <Image_name>
|
||||
|
||||
D.3.5 Running the Docker Container on Windows or MacOS
|
||||
|
||||
Docker Desktop is easiest to use for Mac OS or Windows and can be installed by downloading from http://docker.com. Once the desktop application is installed, users can log into their DockerHub account through the Docker Desktop application and manage their containers easily.
|
||||
|
||||
*** with Questa
|
||||
*** questa unavailable native on Mac
|
||||
|
||||
|
||||
D.3.6 Regenerating the Docker File
|
||||
|
||||
We use the following steps to generate the Docker file. You can adapt them is you wish to make your own custom Docker image, such as one with commercial CAD tools installed in your local environment.
|
||||
|
||||
*** how to use this
|
||||
|
||||
# Compliance Development Environment Image
|
||||
FROM debian
|
||||
|
||||
# UPDATE / UPGRADE
|
||||
RUN apt update
|
||||
|
||||
# INSTALL
|
||||
RUN apt install -y git gawk make texinfo bison flex build-essential python libz-
|
||||
dev libexpat-dev autoconf device-tree-compiler ninja-build libpixman-1-dev build
|
||||
-essential ncurses-base ncurses-bin libncurses5-dev dialog curl wget ftp libgmp-
|
||||
dev python3-pip pkg-config libglib2.0-dev opam build-essential z3 pkg-config zl
|
||||
ib1g-dev verilator cpio bc vim emacs gedit nano
|
||||
|
||||
RUN pip3 install chardet==3.0.4
|
||||
RUN pip3 install urllib3==1.22
|
||||
RUN pip3 install testresources
|
||||
RUN pip3 install riscof --ignore-installed PyYAML
|
||||
RUN echo "root:wally" | chpasswd
|
||||
|
||||
# ADD RISCV
|
||||
WORKDIR /opt/riscv
|
||||
|
||||
# Create a user group 'xyzgroup'
|
||||
ARG USERNAME=cad
|
||||
ARG USER_UID=1000
|
||||
ARG USER_GID=$USER_UID
|
||||
|
||||
# Create the user
|
||||
RUN groupadd --gid $USER_GID $USERNAME \
|
||||
&& useradd --uid $USER_UID --gid $USER_GID -m $USERNAME \
|
||||
# [Optional] Add sudo support. Omit if you don't need to install software af
|
||||
ter connecting.
|
||||
&& apt-get update \
|
||||
&& apt-get install -y sudo \
|
||||
&& echo $USERNAME ALL=\(root\) NOPASSWD:ALL > /etc/sudoers.d/$USERNAME \
|
||||
&& chmod 0440 /etc/sudoers.d/$USERNAME
|
||||
|
||||
# Change RISCV user
|
||||
run chown -Rf cad:cad /opt
|
||||
|
||||
# Add cad user
|
||||
USER $USERNAME
|
||||
|
||||
# SET ENVIRONMENT VARIABLES
|
||||
ENV RISCV=/opt/riscv
|
||||
ENV PATH=$PATH:$RISCV/bin
|
||||
|
||||
# TOOLCHAIN
|
||||
RUN git clone https://github.com/riscv/riscv-gnu-toolchain && \
|
||||
cd riscv-gnu-toolchain && \
|
||||
./configure --prefix=${RISCV} --enable-multilib --with-multilib-generator="r
|
||||
v32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32
|
||||
imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv6
|
||||
4imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;" && \
|
||||
make --jobs && \
|
||||
make install
|
||||
|
||||
# elf2hex
|
||||
ENV PATH=$RISCV/riscv-gnu-toolchain/bin:$PATH
|
||||
WORKDIR /opt/riscv
|
||||
RUN git clone https://github.com/sifive/elf2hex.git && \
|
||||
cd elf2hex && \
|
||||
autoreconf -i && \
|
||||
./configure --target=riscv64-unknown-elf --prefix=$RISCV && \
|
||||
make && \
|
||||
make install
|
||||
|
||||
# QEMU
|
||||
WORKDIR /opt/riscv
|
||||
RUN git clone --recurse-submodules https://github.com/qemu/qemu && \
|
||||
cd qemu && \
|
||||
./configure --target-list=riscv64-softmmu --prefix=$RISCV && \
|
||||
make --jobs && \
|
||||
make install
|
||||
|
||||
# Spike
|
||||
WORKDIR /opt/riscv
|
||||
RUN git clone https://github.com/riscv-software-src/riscv-isa-sim && \
|
||||
mkdir riscv-isa-sim/build && \
|
||||
cd riscv-isa-sim/build && \
|
||||
../configure --prefix=$RISCV --enable-commitlog && \
|
||||
make --jobs && \
|
||||
make install && \
|
||||
cd ../arch_test_target/spike/device && \
|
||||
sed -i 's/--isa=rv32ic/--isa=rv32iac/' rv32i_m/privilege/Makefile.include && \
|
||||
sed -i 's/--isa=rv64ic/--isa=rv64iac/' rv64i_m/privilege/Makefile.include
|
||||
|
||||
# SAIL
|
||||
WORKDIR /opt/riscv
|
||||
RUN opam init -y --disable-sandboxing
|
||||
RUN opam switch create ocaml-base-compiler.4.06.1
|
||||
RUN opam install sail -y
|
||||
RUN eval $(opam config env) && \
|
||||
cd $RISCV && \
|
||||
git clone https://github.com/riscv/sail-riscv.git && \
|
||||
cd sail-riscv && \
|
||||
make && \
|
||||
ARCH=RV32 make && \
|
||||
ARCH=RV64 make && \
|
||||
ln -s $RISCV/sail-riscv/c_emulator/riscv_sim_RV64 $RISCV/bin/riscv_sim_RV64 &&
|
||||
\
|
||||
ln -s $RISCV/sail-riscv/c_emulator/riscv_sim_RV32 $RISCV/bin/riscv_sim_RV32
|
||||
|
||||
# Buildroot
|
||||
WORKDIR /opt/riscv
|
||||
RUN git clone --recurse-submodules https://stineje:ghp_kXIHqiMSv4tFec2BCAvrhSrIh
|
||||
3KNUD06IejU@github.com/davidharrishmc/riscv-wally.git
|
||||
ENV export WALLY=/opt/riscv/riscv-wally
|
||||
RUN git clone https://github.com/buildroot/buildroot.git && \
|
||||
cd buildroot && \
|
||||
git checkout 2021.05 && \
|
||||
cp -r /opt/riscv/riscv-wally/linux/buildroot-config-src/wally ./board && \
|
||||
cp ./board/wally/main.config .config && \
|
||||
make --jobs
|
||||
|
||||
# change to cad's hometown
|
||||
WORKDIR /home/cad
|
||||
|
||||
|
||||
D.3.7 Integrating Commercial CAD Tools into a Local Docker Container
|
||||
|
||||
|
||||
|
||||
RISC-V System-on-Chip Design Lecture Notes
|
||||
© 2023 D. Harris, J. Stine, , R. Thompson, and S. Harris
|
||||
These notes may be used and modified for educational and/or non-commercial purposes so long as the source is attributed.
|
||||
|
||||
132
docs/Dockerfile
132
docs/Dockerfile
@ -1,132 +0,0 @@
|
||||
###########################################
|
||||
## Dockerfile
|
||||
##
|
||||
## Written: james.stine@okstate.edu 28 January 2023
|
||||
## Modified:
|
||||
##
|
||||
## Purpose: Dockerfile for Wally docker container creation
|
||||
##
|
||||
## A component of the CORE-V-WALLY configurable RISC-V project.
|
||||
##
|
||||
## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
|
||||
##
|
||||
## SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
##
|
||||
## Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||
## except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||
## may obtain a copy of the License at
|
||||
##
|
||||
## https:##solderpad.org#licenses#SHL-2.1#
|
||||
##
|
||||
## Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||
## License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||
## either express or implied. See the License for the specific language governing permissions
|
||||
## and limitations under the License.
|
||||
################################################################################################
|
||||
# Compliance Development Environment Image
|
||||
FROM debian
|
||||
|
||||
# UPDATE / UPGRADE
|
||||
RUN apt update
|
||||
|
||||
# INSTALL
|
||||
RUN apt install -y git gawk make texinfo bison flex build-essential python libz-dev libexpat-dev autoconf device-tree-compiler ninja-build libpixman-1-dev build-essential ncurses-base ncurses-bin libncurses5-dev dialog curl wget ftp libgmp-dev python3-pip pkg-config libglib2.0-dev opam build-essential z3 pkg-config zlib1g-dev verilator cpio bc vim emacs gedit nano
|
||||
|
||||
RUN pip3 install chardet==3.0.4
|
||||
RUN pip3 install urllib3==1.22
|
||||
RUN pip3 install testresources
|
||||
RUN pip3 install riscof --ignore-installed PyYAML
|
||||
RUN echo "root:wally" | chpasswd
|
||||
|
||||
# ADD RISCV
|
||||
WORKDIR /opt/riscv
|
||||
|
||||
# Create a user group 'xyzgroup'
|
||||
ARG USERNAME=cad
|
||||
ARG USER_UID=1000
|
||||
ARG USER_GID=$USER_UID
|
||||
|
||||
# Create the user
|
||||
RUN groupadd --gid $USER_GID $USERNAME \
|
||||
&& useradd --uid $USER_UID --gid $USER_GID -m $USERNAME \
|
||||
# [Optional] Add sudo support. Omit if you don't need to install software after connecting.
|
||||
&& apt-get update \
|
||||
&& apt-get install -y sudo \
|
||||
&& echo $USERNAME ALL=\(root\) NOPASSWD:ALL > /etc/sudoers.d/$USERNAME \
|
||||
&& chmod 0440 /etc/sudoers.d/$USERNAME
|
||||
|
||||
# Change RISCV user
|
||||
run chown -Rf cad:cad /opt
|
||||
|
||||
# Add cad user
|
||||
USER $USERNAME
|
||||
|
||||
# SET ENVIRONMENT VARIABLES
|
||||
ENV RISCV=/opt/riscv
|
||||
ENV PATH=$PATH:$RISCV/bin
|
||||
|
||||
# TOOLCHAIN
|
||||
RUN git clone https://github.com/riscv/riscv-gnu-toolchain && \
|
||||
cd riscv-gnu-toolchain && \
|
||||
./configure --prefix=${RISCV} --enable-multilib --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;" && \
|
||||
make --jobs && \
|
||||
make install
|
||||
|
||||
# elf2hex
|
||||
ENV PATH=$RISCV/riscv-gnu-toolchain/bin:$PATH
|
||||
WORKDIR /opt/riscv
|
||||
RUN git clone https://github.com/sifive/elf2hex.git && \
|
||||
cd elf2hex && \
|
||||
autoreconf -i && \
|
||||
./configure --target=riscv64-unknown-elf --prefix=$RISCV && \
|
||||
make && \
|
||||
make install
|
||||
|
||||
# QEMU
|
||||
WORKDIR /opt/riscv
|
||||
RUN git clone --recurse-submodules https://github.com/qemu/qemu && \
|
||||
cd qemu && \
|
||||
./configure --target-list=riscv64-softmmu --prefix=$RISCV && \
|
||||
make --jobs && \
|
||||
make install
|
||||
|
||||
# Spike
|
||||
WORKDIR /opt/riscv
|
||||
RUN git clone https://github.com/riscv-software-src/riscv-isa-sim && \
|
||||
mkdir riscv-isa-sim/build && \
|
||||
cd riscv-isa-sim/build && \
|
||||
../configure --prefix=$RISCV --enable-commitlog && \
|
||||
make --jobs && \
|
||||
make install && \
|
||||
cd ../arch_test_target/spike/device && \
|
||||
sed -i 's/--isa=rv32ic/--isa=rv32iac/' rv32i_m/privilege/Makefile.include && \
|
||||
sed -i 's/--isa=rv64ic/--isa=rv64iac/' rv64i_m/privilege/Makefile.include
|
||||
|
||||
# SAIL
|
||||
WORKDIR /opt/riscv
|
||||
RUN opam init -y --disable-sandboxing
|
||||
RUN opam switch create ocaml-base-compiler.4.06.1
|
||||
RUN opam install sail -y
|
||||
RUN eval $(opam config env) && \
|
||||
cd $RISCV && \
|
||||
git clone https://github.com/riscv/sail-riscv.git && \
|
||||
cd sail-riscv && \
|
||||
make && \
|
||||
ARCH=RV32 make && \
|
||||
ARCH=RV64 make && \
|
||||
ln -s $RISCV/sail-riscv/c_emulator/riscv_sim_RV64 $RISCV/bin/riscv_sim_RV64 && \
|
||||
ln -s $RISCV/sail-riscv/c_emulator/riscv_sim_RV32 $RISCV/bin/riscv_sim_RV32
|
||||
|
||||
# Buildroot
|
||||
WORKDIR /opt/riscv
|
||||
RUN git clone --recurse-submodules https://github.com/openhwgroup/cvw.git
|
||||
ENV export WALLY=/opt/riscv/riscv-wally
|
||||
RUN git clone https://github.com/buildroot/buildroot.git && \
|
||||
cd buildroot && \
|
||||
git checkout 2021.05 && \
|
||||
cp -r /opt/riscv/riscv-wally/linux/buildroot-config-src/wally ./board && \
|
||||
cp ./board/wally/main.config .config && \
|
||||
make --jobs
|
||||
|
||||
# change to cad's hometown
|
||||
WORKDIR /home/cad
|
||||
@ -1,41 +0,0 @@
|
||||
### Cross-Compile Buildroot Linux
|
||||
|
||||
Building Linux is only necessary for exploring the boot process in Chapter 17. Building and generating a trace is a time-consuming operation that could be skipped for now; you can return to this section later if you are interested in the Linux details.
|
||||
|
||||
Buildroot depends on configuration files in riscv-wally, so the cad user must install Wally first according to the instructions in Section 2.2.2. However, don’t source ~/wally-riscv/setup.sh because it will set LD_LIBRARY_PATH in a way to cause make to fail on buildroot.
|
||||
|
||||
To configure and build Buildroot:
|
||||
|
||||
$ cd $RISCV
|
||||
$ export WALLY=~/riscv-wally # make sure you haven’t sourced ~/riscv-wally/setup.sh by now
|
||||
$ git clone https://github.com/buildroot/buildroot.git
|
||||
$ cd buildroot
|
||||
$ git checkout 2021.05 # last tested working version
|
||||
$ cp -r $WALLY/linux/buildroot-config-src/wally ./board
|
||||
$ cp ./board/wally/main.config .config
|
||||
$ make --jobs
|
||||
|
||||
To generate disassembly files and the device tree, run another make script. Note that you can expect some warnings about phandle references while running dtc on wally-virt.dtb.
|
||||
Depending on your system configuration this makefile may need a bit of tweaking. It places the output buildroot images in $RISCV/linux-testvectors and the buildroot object dumps in $RISCV/buildroot/output/images/disassembly. If these directories are owned by root then the makefile will likely fail. You can either change the makefile's target directories or change temporarily change the owner of the two directories.
|
||||
|
||||
$ source ~/riscv-wally/setup.sh
|
||||
$ cd $WALLY/linux/buildroot-scripts
|
||||
$ make all
|
||||
|
||||
Note: When the make tasks complete, you’ll find source code in $RISCV/buildroot/output/build and the executables in $RISCV/buildroot/output/images.
|
||||
|
||||
### Generate load images for linux boot
|
||||
|
||||
The Questa linux boot uses preloaded bootram and ram memory. We use QEMU to generate these preloaded memory files. Files output in $RISCV/linux-testvectors
|
||||
|
||||
cd cvw/linux/testvector-generation
|
||||
./genInitMem.sh
|
||||
|
||||
This may require changing file permissions to the linux-testvectors directory.
|
||||
|
||||
### Generate QEMU linux trace
|
||||
|
||||
The linux testbench can instruction by instruction compare Wally's committed instructions against QEMU. To do this QEMU outputs a log file consisting of all instructions executed. Interrupts are handled by forcing the testbench to generate an interrupt at the same cycle as in QEMU. Generating this trace will take more than 24 hours.
|
||||
|
||||
cd cvw/linux/testvector-generation
|
||||
./genTrace.sh
|
||||
@ -1,52 +0,0 @@
|
||||
# CORE-V Wally Design Verification Test Plan
|
||||
|
||||
CORE-V Wally is functionally tested in the following ways. Each test is run in lock-step against ImperasDV to ensure all architectural state is correct after each instruction.
|
||||
|
||||
| Functions | Coverage Method | Status |
|
||||
| ----------- | ----------- |----|
|
||||
| Instructions | riscv-arch-test | Pass |
|
||||
| Privileged Unit | wally-riscv-arch-test | Pass |
|
||||
| Virtual Memory | wally-riscv-arch-test | Pass |
|
||||
| PMP | wally-riscv-arch-test | Pass
|
||||
| Peripherals | wally-riscv-arch-test | Pass |
|
||||
| Floating-Point | TestFloat | Pass |
|
||||
| General | Code Coverage | 91% |
|
||||
| General | Boot Linux in Sim | Pass |
|
||||
| General | Boot Linux on FPGA | Pass |
|
||||
|
||||
|
||||
The following performance validation is also run:
|
||||
| Function | Method | Status |
|
||||
| --- | --- | --- |
|
||||
| Overall Performance | embench | Pass|
|
||||
| Overall Performance | coremark | Pass |
|
||||
| Branch Predictor | *** | Pass |
|
||||
| Cache Miss Rate | *** | Pass |
|
||||
|
||||
|
||||
|
||||
* Run [RISC-V Architecture Compatibility Tests](https://github.com/riscv-non-isa/riscv-arch-test) in lock-step against the ImperasDV reference model.
|
||||
* Run custom tests to cover virtual memory, PMP, privileged unit, and peripherals in lock step against ImperasDV.
|
||||
* ***pending: Run random tests generated by risc-dv
|
||||
* Run CoreMark and Embench benchmarks.
|
||||
* Run performance validation against reference models for the branch predictor and caches.
|
||||
* Run the TestFloat suite against all precisions of all operations for the FPU unit.
|
||||
* *** 83.5% coverage of statements, branches, expressions, and FSM states and transitions
|
||||
* Boot Buildroot Linux in lock-step against ImperasDV.
|
||||
* Boot Buildroot Linux on an FPGA and run programs.
|
||||
|
||||
# Running Tests
|
||||
|
||||
#
|
||||
|
||||
# Detailed Test Plans
|
||||
|
||||
The test plans for specific units are lined below:
|
||||
|
||||
* Privileged Unit
|
||||
* Memory Management Unit
|
||||
* Peripherals
|
||||
* Branch Predictor Performance Validation
|
||||
* Cache Performance Validation
|
||||
|
||||
Wally is described in an upcoming textbook, *RISC-V System-on-Chip Design*, by Harris, Stine, Thompson, and Harris.
|
||||
@ -1,30 +0,0 @@
|
||||
# core-v-wally Design Verification Test Plan
|
||||
|
||||
This document outlines the test plan for the Wally rv64gc configuration to reach Technology Readiness Level 5.
|
||||
|
||||
1. Pass riscv-arch-test
|
||||
2. Boot Linux
|
||||
3. FPU pass all TestFloat vectors
|
||||
4. Performance verification: Caches and branch predictor miss rates match independent simulation
|
||||
5. Directed tests
|
||||
- Privileged unit: Chapter 5 test plan
|
||||
- MMU: PMA, PMP, virtual memory: Chapter 8 test plan
|
||||
- Peripherals: Chapter 16 test plan
|
||||
6. Random tests
|
||||
- riscdv tests
|
||||
7. Coverage tests
|
||||
- Directed tests to bring coverage up to 100%.
|
||||
- Statement, experssion, branch, condition, FSM coverage in Questa
|
||||
- Do not measure toggle coverage
|
||||
|
||||
All tests operate correctly in lock-step with ImperasDV
|
||||
|
||||
Open questions:
|
||||
1. How to define extent of riscdv random tests needed?
|
||||
2. What other directed tests?
|
||||
PMP Tests
|
||||
Virtual Memory Tests
|
||||
How to define pipeline tests?
|
||||
Simple ones like use after load stall are not important.
|
||||
Hard ones such as page table walker fault during data access while I$ access is pending are hard to articulate and code
|
||||
Is there an example of a good directed pipeline test plan & implementation
|
||||
@ -5,7 +5,7 @@ $(TARGET).objdump: $(TARGET)
|
||||
spike $(TARGET)
|
||||
|
||||
$(TARGET): $(TARGET).c Makefile
|
||||
riscv64-unknown-elf-gcc -o $(TARGET) -g\
|
||||
riscv64-unknown-elf-gcc -o $(TARGET) -g -O2\
|
||||
-march=rv64gc -mabi=lp64d -mcmodel=medany \
|
||||
-nostdlib -static -lm -fno-tree-loop-distribute-patterns \
|
||||
-T../common/test.ld -I../common \
|
||||
|
||||
35
examples/C/fir/fir.S
Normal file
35
examples/C/fir/fir.S
Normal file
@ -0,0 +1,35 @@
|
||||
// fir.s
|
||||
// mmasserfrye@hmc.edu 30 January 2022
|
||||
// FIR filter
|
||||
|
||||
// a0 = N, a1 = M, a2 = &X, a3 = &c, a4 = &Y
|
||||
|
||||
.global fir
|
||||
|
||||
fir:
|
||||
li t0, 0 # n = 0 = t0
|
||||
slli t6, a0, 3 # N*8
|
||||
slli t5, a1, 3 # M*8
|
||||
addi t4, t5, -8 # (M-1)*8
|
||||
for1:
|
||||
bge t0, t6, end # exit outer for if n >= N
|
||||
fmv.d.x f3, zero # sum = 0 = f3
|
||||
li t2, 0 # i = 0 = t2
|
||||
add t1, t4, t0 # [(M-1) + n]*8
|
||||
for2:
|
||||
bge t2, t5, for1end # exit inner for if i >= M
|
||||
sub t3, t1, t2 # [(M-1) + n - i]*8
|
||||
add t3, t3, a2 # t3 = offset + &X
|
||||
fld f0, 0(t3) # X[n-i+(M-1)]
|
||||
add t3, t2, a3 # t3 = offset + &c
|
||||
fld f1, 0(t3) # c[i]
|
||||
fmadd.d f3, f0, f1, f3 # sum += c[i]*X[n-i+(M-1)]
|
||||
addi t2, t2, 8 # i++
|
||||
j for2
|
||||
for1end:
|
||||
add t3, t0, a4 # t3 = offset + &Y
|
||||
fsd f3, 0(t3) # Y[n] = sum
|
||||
addi t0, t0, 8 # n++
|
||||
j for1
|
||||
end:
|
||||
ret
|
||||
33
examples/C/lab1matrix/Makefile
Normal file
33
examples/C/lab1matrix/Makefile
Normal file
@ -0,0 +1,33 @@
|
||||
TARGET = matMult
|
||||
|
||||
$(TARGET).objdump: $(TARGET)
|
||||
riscv64-unknown-elf-objdump -S -D $(TARGET) > $(TARGET).objdump
|
||||
spike $(TARGET)
|
||||
|
||||
$(TARGET): $(TARGET).c Makefile
|
||||
riscv64-unknown-elf-gcc -o $(TARGET) -g -O\
|
||||
-march=rv64gc -mabi=lp64d -mcmodel=medany \
|
||||
-nostdlib -static -lm -fno-tree-loop-distribute-patterns \
|
||||
-T../common/test.ld -I../common \
|
||||
$(TARGET).c ../common/crt.S ../common/syscalls.c
|
||||
# Compiler flags:
|
||||
# -o $(TARGET) defines the name of the output file
|
||||
# -g generates debugging symbols for gdb
|
||||
# -O turns on basic optimization; -O3 turns on heavy optimization; omit for no optimization
|
||||
# -march=rv64gc -mabi=lp64d =mcmodel=medany generates code for RV64GC with doubles and long/ptrs = 64 bits
|
||||
# -static forces static linking (no dynamic shared libraries on bare metal)
|
||||
# -lm links the math library if necessary (when #include math.h)
|
||||
# -nostdlib avoids inserting standard startup files and default libraries
|
||||
# because we are using crt.s on bare metal
|
||||
# -fno-tree-loop-distribute-patterns turns replacing loops with memcpy/memset in the std library
|
||||
# -T specifies the linker file
|
||||
# -I specifies the include path (e.g. for util.h)
|
||||
# The last line defines the C files to compile.
|
||||
# crt.S is needed as our startup file to initialize the processor
|
||||
# syscalls.c implements printf through the HTIF for Spike
|
||||
# other flags from riscv-tests makefiles that don't seem to be important
|
||||
# -ffast-math -DPREALLOCATE=1 -std=gnu99 \
|
||||
# -fno-common -fno-builtin-printf -nostartfiles -lgcc \
|
||||
|
||||
clean:
|
||||
rm -f $(TARGET) $(TARGET).objdump
|
||||
BIN
examples/C/lab1matrix/matMult
Executable file
BIN
examples/C/lab1matrix/matMult
Executable file
Binary file not shown.
87
examples/C/lab1matrix/matMult.c
Normal file
87
examples/C/lab1matrix/matMult.c
Normal file
@ -0,0 +1,87 @@
|
||||
// matMult.c
|
||||
// mmasserfrye@hmc.edu 30 January 2022
|
||||
|
||||
#include <stdio.h> // supports printf
|
||||
#include <math.h> // supports fabs
|
||||
#include "util.h" // supports verify
|
||||
|
||||
// puts the indicated row of length n from matrix mat into array arr
|
||||
void getRow(int n, int row, double *mat, double *arr){
|
||||
int ind;
|
||||
for (int i=0; i<n; i++){
|
||||
ind = i+row*n;
|
||||
arr[i] = mat[ind];
|
||||
}
|
||||
}
|
||||
|
||||
// computes the dot product of arrays a and b of length n
|
||||
double dotproduct(int n, double a[], double b[]) {
|
||||
|
||||
volatile int i;
|
||||
double sum;
|
||||
sum = 0;
|
||||
|
||||
for (i=0; i<n; i++) {
|
||||
if (i==0) sum=0;
|
||||
sum += a[i]*b[i];
|
||||
}
|
||||
return sum;
|
||||
}
|
||||
|
||||
// multiplies matrices A (m1 x n1m2) and B (n1m2 x n2) and puts the result in Y
|
||||
void mult(int m1, int n1m2, int n2, double *A, double *B, double *Y) {
|
||||
|
||||
// transpose B into Bt so we can dot product matching rows
|
||||
double Bt[n2*n1m2];
|
||||
int ind;
|
||||
int indt;
|
||||
for (int i=0; i<n1m2; i++){
|
||||
for (int j=0; j<n2; j++){
|
||||
ind = i*n2+j;
|
||||
indt = j*n1m2+i;
|
||||
Bt[indt] = B[ind];
|
||||
}
|
||||
}
|
||||
|
||||
int indY;
|
||||
double Arow[n1m2];
|
||||
double Bcol[n1m2];
|
||||
|
||||
for (int i=0; i<m1; i++){
|
||||
for (int j=0; j<n2; j++){
|
||||
indY = i*n2+j;
|
||||
getRow(n1m2, i, A, Arow);
|
||||
getRow(n1m2, j, Bt, Bcol);
|
||||
Y[indY] = dotproduct(n1m2, Arow, Bcol);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
int main(void) {
|
||||
|
||||
// change these bits to test stuff
|
||||
int m = 20;
|
||||
int n = 1;
|
||||
double X[20]; // change to m*n
|
||||
double Y[400]; // change to m^2
|
||||
|
||||
// fill in some numbers so the test feels legit
|
||||
for (int i=0; i<n; i++){
|
||||
X[i] = i;
|
||||
}
|
||||
|
||||
setStats(1);
|
||||
mult(m, n, m, X, X, Y);
|
||||
setStats(0);
|
||||
|
||||
/*
|
||||
// use this code from Harris's fir.c to print matrix one element at a time
|
||||
// library linked doesn't support printing doubles, so convert to integers to print
|
||||
for (int i=0; i<m*m; i++) {
|
||||
int tmp = Y[i];
|
||||
printf("Y[%d] = %d\n", i, tmp);
|
||||
}
|
||||
*/
|
||||
return 0;
|
||||
|
||||
}
|
||||
@ -4,7 +4,7 @@ $(TARGET).objdump: $(TARGET)
|
||||
riscv64-unknown-elf-objdump -S -D $(TARGET) > $(TARGET).objdump
|
||||
|
||||
$(TARGET): $(TARGET).c Makefile
|
||||
riscv64-unknown-elf-gcc -o $(TARGET) -gdwarf-2 -O\
|
||||
riscv64-unknown-elf-gcc -o $(TARGET) -g -O\
|
||||
-march=rv64gc -mabi=lp64d -mcmodel=medany \
|
||||
-nostdlib -static -lm -fno-tree-loop-distribute-patterns \
|
||||
-T../common/test.ld -I../common \
|
||||
|
||||
@ -1,77 +0,0 @@
|
||||
//
|
||||
// softfloat_div.c
|
||||
// james.stine@okstate.edu 12 April 2023
|
||||
//
|
||||
// Demonstrate using SoftFloat to compute 754 fp divide, then print results
|
||||
// (adapted from original C built by David Harris)
|
||||
//
|
||||
|
||||
#include <stdio.h>
|
||||
#include <stdint.h>
|
||||
#include "softfloat.h"
|
||||
#include "softfloat_types.h"
|
||||
typedef union sp {
|
||||
uint32_t v;
|
||||
unsigned short x[2];
|
||||
float f;
|
||||
} sp;
|
||||
|
||||
void printF32 (char *msg, float32_t f) {
|
||||
sp conv;
|
||||
int i, j;
|
||||
conv.v = f.v; // use union to convert between hexadecimal and floating-point views
|
||||
printf("%s: ", msg); // print out nicely
|
||||
printf("0x%04x_%04x = %1.15g\n", (conv.v >> 16),(conv.v & 0xFFFF), conv.f);
|
||||
}
|
||||
|
||||
void printFlags(void) {
|
||||
int NX = softfloat_exceptionFlags % 2;
|
||||
int UF = (softfloat_exceptionFlags >> 1) % 2;
|
||||
int OF = (softfloat_exceptionFlags >> 2) % 2;
|
||||
int DZ = (softfloat_exceptionFlags >> 3) % 2;
|
||||
int NV = (softfloat_exceptionFlags >> 4) % 2;
|
||||
printf ("Flags: Inexact %d Underflow %d Overflow %d DivideZero %d Invalid %d\n",
|
||||
NX, UF, OF, DZ, NV);
|
||||
}
|
||||
|
||||
void softfloatInit(void) {
|
||||
// RNE: softfloat_round_near_even
|
||||
// RZ: softfloat_round_minMag
|
||||
// RU: softfloat_round_max
|
||||
// RD: softfloat_round_min
|
||||
// RM: softfloat_round_near_maxMag
|
||||
softfloat_roundingMode = softfloat_round_near_even;
|
||||
softfloat_exceptionFlags = 0; // clear exceptions
|
||||
softfloat_detectTininess = softfloat_tininess_afterRounding; // RISC-V behavior for tininess
|
||||
}
|
||||
|
||||
int main() {
|
||||
|
||||
// float32_t is typedef in SoftFloat
|
||||
float32_t x, y, r1, r2;
|
||||
sp convx, convy;
|
||||
|
||||
// Choose two random values
|
||||
convx.f = 1.30308703073;
|
||||
convy.f = 1.903038030370;
|
||||
// Convert to SoftFloat format
|
||||
x.v = (convx.x[1] << 16) + convx.x[0];
|
||||
y.v = (convy.x[1] << 16) + convy.x[0];
|
||||
|
||||
printf("Example using SoftFloat\n");
|
||||
|
||||
softfloatInit();
|
||||
r1 = f32_div(x, y);
|
||||
printf("-------\n");
|
||||
printF32("X", x);
|
||||
printF32("Y", y);
|
||||
printF32("result = X/Y", r1);
|
||||
printFlags();
|
||||
|
||||
r2 = f32_sqrt(x);
|
||||
printf("-------\n");
|
||||
printF32("X", x);
|
||||
printF32("result = sqrt(X)", r2);
|
||||
printFlags();
|
||||
|
||||
}
|
||||
@ -1,72 +0,0 @@
|
||||
// sqrttest.c
|
||||
// David_Harris@hmc.edu 21 September 2022
|
||||
//
|
||||
// Compute square roots to make test cases for fdivsqrt
|
||||
|
||||
#include <stdio.h>
|
||||
#include <stdint.h>
|
||||
#include "softfloat.h"
|
||||
#include "softfloat_types.h"
|
||||
typedef union sp {
|
||||
uint32_t v;
|
||||
float f;
|
||||
} sp;
|
||||
|
||||
void printF32 (char *msg, float32_t f) {
|
||||
sp conv;
|
||||
int i, j;
|
||||
conv.v = f.v; // use union to convert between hexadecimal and floating-point views
|
||||
printf("%s: ", msg); // print out nicely
|
||||
printf("0x%04x_%04x = %g\n", (conv.v >> 16),(conv.v & 0xFFFF), conv.f);
|
||||
}
|
||||
|
||||
void printF32hex(float32_t f) {
|
||||
sp conv;
|
||||
int i, j;
|
||||
conv.v = f.v; // use union to convert between hexadecimal and floating-point views
|
||||
printf("%08x", conv.v);
|
||||
}
|
||||
|
||||
void printFlags(void) {
|
||||
int NX = softfloat_exceptionFlags % 2;
|
||||
int UF = (softfloat_exceptionFlags >> 1) % 2;
|
||||
int OF = (softfloat_exceptionFlags >> 2) % 2;
|
||||
int DZ = (softfloat_exceptionFlags >> 3) % 2;
|
||||
int NV = (softfloat_exceptionFlags >> 4) % 2;
|
||||
printf ("Flags: Inexact %d Underflow %d Overflow %d DivideZero %d Invalid %d\n",
|
||||
NX, UF, OF, DZ, NV);
|
||||
}
|
||||
|
||||
void printFlagsHex(void) {
|
||||
printf("%02x", softfloat_exceptionFlags);
|
||||
}
|
||||
|
||||
void softfloatInit(void) {
|
||||
// rounding modes: RNE: softfloat_round_near_even
|
||||
// RZ: softfloat_round_minMag
|
||||
// RP: softfloat_round_max
|
||||
// RM: softfloat_round_min
|
||||
softfloat_roundingMode = softfloat_round_near_even;
|
||||
softfloat_exceptionFlags = 0; // clear exceptions
|
||||
softfloat_detectTininess = softfloat_tininess_afterRounding; // RISC-V behavior for tininess
|
||||
}
|
||||
|
||||
int main()
|
||||
{
|
||||
float32_t x, y, z, r;
|
||||
|
||||
//3F908312
|
||||
//3F98F5C3
|
||||
|
||||
//8683F7FF_FFC00000_10
|
||||
|
||||
//3F908312
|
||||
x.v = 0x3F800000;
|
||||
while (x.v < 0x40000000) {
|
||||
softfloatInit();
|
||||
r = f32_sqrt(x);
|
||||
printF32hex(x); printf("_");
|
||||
printF32hex(r); printf("_"); printFlagsHex(); printf("\n");
|
||||
x.v += 1;
|
||||
}
|
||||
}
|
||||
@ -12,8 +12,6 @@ SECTIONS
|
||||
.data.string : { *(.data.string)}
|
||||
. = ALIGN(0x1000);
|
||||
.bss : { *(.bss) }
|
||||
. = ALIGN(0x1000);
|
||||
.text : { *(.text.main) }
|
||||
_end = .;
|
||||
}
|
||||
|
||||
|
||||
4225
examples/verilog/fma/baby_torture.tv
Normal file
4225
examples/verilog/fma/baby_torture.tv
Normal file
File diff suppressed because it is too large
Load Diff
1057
examples/verilog/fma/baby_torture_rz.tv
Normal file
1057
examples/verilog/fma/baby_torture_rz.tv
Normal file
File diff suppressed because it is too large
Load Diff
23
examples/verilog/fma/fma.do
Normal file
23
examples/verilog/fma/fma.do
Normal file
@ -0,0 +1,23 @@
|
||||
# fma.do
|
||||
#
|
||||
# run with vsim -do "do fma.do"
|
||||
# add -c before -do for batch simulation
|
||||
|
||||
onbreak {resume}
|
||||
|
||||
# create library
|
||||
vlib worklib
|
||||
|
||||
vlog -lint -sv -work worklib fma16.v testbench.v
|
||||
vopt +acc worklib.testbench_fma16 -work worklib -o testbenchopt
|
||||
vsim -lib worklib testbenchopt
|
||||
|
||||
add wave sim:/testbench_fma16/clk
|
||||
add wave sim:/testbench_fma16/reset
|
||||
add wave sim:/testbench_fma16/x
|
||||
add wave sim:/testbench_fma16/y
|
||||
add wave sim:/testbench_fma16/z
|
||||
add wave sim:/testbench_fma16/result
|
||||
add wave sim:/testbench_fma16/rexpected
|
||||
|
||||
run -all
|
||||
268
examples/verilog/fma/fma16.v
Normal file
268
examples/verilog/fma/fma16.v
Normal file
@ -0,0 +1,268 @@
|
||||
// fma16.sv
|
||||
// David_Harris@hmc.edu 26 February 2022
|
||||
// 16-bit floating-point multiply-accumulate
|
||||
|
||||
// Operation: general purpose multiply, add, fma, with optional negation
|
||||
// If mul=1, p = x * y. Else p = x.
|
||||
// If add=1, result = p + z. Else result = p.
|
||||
// If negr or negz = 1, negate result or z to handle negations and subtractions
|
||||
// fadd: mul = 0, add = 1, negr = negz = 0
|
||||
// fsub: mul = 0, add = 1, negr = 0, negz = 1
|
||||
// fmul: mul = 1, add = 0, negr = 0, negz = 0
|
||||
// fmadd: mul = 1, add = 1, negr = 0, negz = 0
|
||||
// fmsub: mul = 1, add = 1, negr = 0, negz = 1
|
||||
// fnmadd: mul = 1, add = 1, negr = 1, negz = 0
|
||||
// fnmsub: mul = 1, add = 1, negr = 1, negz = 1
|
||||
|
||||
`define FFLEN 16
|
||||
`define Nf 10
|
||||
`define Ne 5
|
||||
`define BIAS 15
|
||||
`define EMIN (-(2**(`Ne-1)-1))
|
||||
`define EMAX (2**(`Ne-1)-1)
|
||||
|
||||
`define NaN 16'h7E00
|
||||
`define INF 15'h7C00
|
||||
|
||||
// rounding modes *** update
|
||||
`define RZ 3'b00
|
||||
`define RNE 3'b01
|
||||
`define RM 3'b10
|
||||
`define RP 3'b11
|
||||
|
||||
module fma16(
|
||||
input logic [`FFLEN-1:0] x, y, z,
|
||||
input logic mul, add, negr, negz,
|
||||
input logic [1:0] roundmode, // 00: rz, 01: rne, 10: rp, 11: rn
|
||||
output logic [`FFLEN-1:0] result);
|
||||
|
||||
logic [`Nf:0] xm, ym, zm; // U1.Nf
|
||||
logic [`Ne-1:0] xe, ye, ze; // B_Ne
|
||||
logic xs, ys, zs;
|
||||
logic zs1; // sign before optional negation
|
||||
logic [2*`Nf+1:0] pm; // U2.2Nf
|
||||
logic [`Ne:0] pe; // B_Ne+1
|
||||
logic ps; // sign of product
|
||||
logic [22:0] rm;
|
||||
logic [`Ne+1:0] re;
|
||||
logic rs;
|
||||
logic xzero, yzero, zzero, xinf, yinf, zinf, xnan, ynan, znan;
|
||||
logic [`Ne+1:0] re2;
|
||||
|
||||
unpack16 unpack(x, y, z, xm, ym, zm, xe, ye, ze, xs, ys, zs1, xzero, yzero, zzero, xinf, yinf, zinf, xnan, ynan, znan); // unpack inputs
|
||||
//signadj16 signadj(negr, negz, xs, ys, zs1, ps, zs); // handle negations
|
||||
mult16 mult16(mul, xm, ym, xe, ye, xs, ys, pm, pe, ps); // p = x * y
|
||||
add16 add16(add, pm, zm, pe, ze, ps, zs, negz, rm, re, re2, rs); // r = z + p
|
||||
postproc16 post(roundmode, xzero, yzero, zzero, xinf, yinf, zinf, xnan, ynan, znan, rm, zm, re, ze, rs, zs, ps, re2, result); // normalize, round, pack
|
||||
endmodule
|
||||
|
||||
module mult16(
|
||||
input logic mul,
|
||||
input logic [`Nf:0] xm, ym,
|
||||
input logic [`Ne-1:0] xe, ye,
|
||||
input logic xs, ys,
|
||||
output logic [2*`Nf+1:0] pm,
|
||||
output logic [`Ne:0] pe,
|
||||
output logic ps);
|
||||
|
||||
// only multiply if mul = 1
|
||||
assign pm = mul ? xm * ym : {1'b0, xm, 10'b0}; // multiply mantiassas
|
||||
assign pe = mul ? xe + ye - `BIAS : {1'b0, xe}; // add exponents, account for bias
|
||||
assign ps = xs ^ ys; // negative if X xor Y are negative
|
||||
endmodule
|
||||
|
||||
module add16(
|
||||
input logic add,
|
||||
input logic [2*`Nf+1:0] pm, // U2.2Nf
|
||||
input logic [`Nf:0] zm, // U1.Nf
|
||||
input logic [`Ne:0] pe, // B_Ne+1
|
||||
input logic [`Ne-1:0] ze, // B_Ne
|
||||
input logic ps, zs,
|
||||
input logic negz,
|
||||
output logic [22:0] rm,
|
||||
output logic [`Ne+1:0] re, // B_Ne+2
|
||||
output logic [`Ne+1:0] re2,
|
||||
output logic rs);
|
||||
|
||||
logic [`Nf*3+7:0] paligned, zaligned, zalignedaddsub, r, r2, rnormed, rnormed2; // U(Nf+6).(2Nf+2) aligned significands
|
||||
logic signed [`Ne:0] ExpDiff; // Q(Ne+2).0
|
||||
logic [`Ne:0] AlignCnt; // U(Ne+3) bits to right shift Z for alignment *** check size.
|
||||
logic [`Nf-1:0] prezsticky;
|
||||
logic zsticky;
|
||||
logic effectivesub;
|
||||
logic rs0;
|
||||
logic [`Ne:0] leadingzeros, NormCnt; // *** should paramterize size
|
||||
logic [`Ne:0] re1;
|
||||
|
||||
// Alignment shift
|
||||
assign paligned = {{(`Nf+4){1'b0}}, pm, 2'b00}; // constant shift to prepend leading and trailing 0s.
|
||||
assign ExpDiff = pe - {1'b0, ze}; // Compute exponent difference as signed number
|
||||
always_comb // AlignCount mux; see Muller page 254
|
||||
if (ExpDiff <= (-2*`Nf - 1)) begin AlignCnt = 3*`Nf + 7; re = {1'b0, pe}; end
|
||||
else if (ExpDiff <= 2) begin AlignCnt = `Nf + 4 - ExpDiff; re = {1'b0, pe}; end
|
||||
else if (ExpDiff <= `Nf+3) begin AlignCnt = `Nf + 4 - ExpDiff; re = {2'b0, ze}; end
|
||||
else begin AlignCnt = 0; re = {2'b0, ze}; end
|
||||
// Shift Zm right by AlignCnt. Produce 3Nf+8 bits of Zaligned in U(Nf+6).(2Nf+2) and Nf bits becoming sticky
|
||||
assign {zaligned, prezsticky} = {zm, {(3*`Nf+7){1'b0}}} >> AlignCnt; //Right shift
|
||||
assign zsticky = |prezsticky; // Sticky bit if any of the discarded bits were 1
|
||||
|
||||
// Effective subtraction
|
||||
assign effectivesub = ps ^ zs ^ negz; // subtract |z| from |p|
|
||||
assign zalignedaddsub = effectivesub ? ~zaligned : zaligned; // invert zaligned for subtraction
|
||||
|
||||
// Adder
|
||||
assign r = paligned + zalignedaddsub + {{`Nf*3+7{1'b0}}, effectivesub}; // add aligned significands
|
||||
assign rs0 = r[`Nf*3+7]; // sign of the initial result
|
||||
assign r2 = rs0 ? ~r+1 : r; // invert sum if negative; could optimize with end-around carry?
|
||||
|
||||
// Sign Logic
|
||||
assign rs = ps ^ rs0; // flip the sign if necessary
|
||||
|
||||
// Leading zero counter
|
||||
lzc lzc(r2, leadingzeros); // count number of leading zeros in 2Nf+5 lower digits of r2
|
||||
assign re1 = pe +2 - leadingzeros; // *** declare, # of bits
|
||||
|
||||
// Normalization shift
|
||||
always_comb // NormCount mux
|
||||
if (ExpDiff < 3) begin
|
||||
if (re1 >= `EMIN) begin NormCnt = `Nf + 3 + leadingzeros; re2 = {1'b0, re1}; end
|
||||
else begin NormCnt = `Nf + 5 + pe - `EMIN; re2 = `EMIN; end
|
||||
end else begin NormCnt = AlignCnt; re = {2'b00, ze}; end
|
||||
assign rnormed = r2 << NormCnt; // *** update sticky
|
||||
/* temporarily comment out to start synth
|
||||
|
||||
// One-bit secondary normalization
|
||||
if (ExpDiff <= 2) begin rnormed2 = rnormed; re2 = re; end // no secondary normalization
|
||||
else begin // *** handle sticky
|
||||
if (rnormed[***]) begin rnormed2 = rnormed >> 1; re2 = re+1; end
|
||||
else if (rnormed[***-1]) begin rnormed2 = rnormed; re2 = re; end
|
||||
else begin rnormed2 = rnormed << 1; re2 = re-1; end
|
||||
end
|
||||
|
||||
// round
|
||||
assign l = rnormed2[***]; // least significant bit
|
||||
assign r = rnormed2[***-1]; // rounding bit
|
||||
assign s = ***; // sticky bit
|
||||
always_comb
|
||||
case (roundmode)
|
||||
RZ: roundup = 0;
|
||||
RP: roundup = ~rs & (r | s);
|
||||
RM: roundup = rs & (r | s);
|
||||
RNE: roundup = r & (s | l);
|
||||
default: roundup = 0;
|
||||
endcase
|
||||
assign {re3, rrounded} = {re2, rnormed2[***]} + roundup; // increment if necessary
|
||||
*/
|
||||
|
||||
// *** need to handle rounding to MAXNUM vs. INFINITY
|
||||
|
||||
// add or pass product through
|
||||
/* assign rm = add ? arm : {1'b0, pm};
|
||||
assign re = add ? are : {1'b0, pe};
|
||||
assign rs = add ? ars : ps; */
|
||||
endmodule
|
||||
|
||||
module lzc(
|
||||
input logic [`Nf*3+7:0] r2,
|
||||
output logic [`Ne:0] leadingzeros
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
module postproc16(
|
||||
input logic [1:0] roundmode,
|
||||
input logic xzero, yzero, zzero, xinf, yinf, zinf, xnan, ynan, znan,
|
||||
input logic [22:0] rm,
|
||||
input logic [`Nf:0] zm, // U1.Nf
|
||||
input logic [6:0] re,
|
||||
input logic [`Ne-1:0] ze, // B_Ne
|
||||
input logic rs, zs, ps,
|
||||
input logic [`Ne+1:0] re2,
|
||||
output logic [15:0] result);
|
||||
|
||||
logic [9:0] uf, uff;
|
||||
logic [6:0] ue;
|
||||
logic [6:0] ueb, uebiased;
|
||||
logic invalid;
|
||||
|
||||
// Special cases
|
||||
// *** not handling signaling NaN
|
||||
// *** also add overflow/underflow/inexact
|
||||
always_comb begin
|
||||
if (xnan | ynan | znan) begin result = `NaN; invalid = 0; end // propagate NANs
|
||||
else if ((xinf | yinf) & zinf & (ps ^ zs)) begin result = `NaN; invalid = 1; end // infinity - infinity
|
||||
else if (xzero & yinf | xinf & yzero) begin result = `NaN; invalid = 1; end // zero times infinity
|
||||
else if (xinf | yinf) begin result = {ps, `INF}; invalid = 0; end // X or Y
|
||||
else if (zinf) begin result = {zs, `INF}; invalid = 0; end // infinite Z
|
||||
else if (xzero | yzero) begin result = {zs, ze, zm[`Nf-1:0]}; invalid = 0; end
|
||||
else if (re2 >= `EMAX) begin result = {rs, `INF}; invalid = 0; end
|
||||
else begin result = {rs, re[`Ne-1:0], rm[`Nf-1:0]}; invalid = 0; end
|
||||
end
|
||||
|
||||
always_comb
|
||||
if (rm[21]) begin // normalization right shift by 1 and bump up exponent;
|
||||
ue = re + 7'b1;
|
||||
uf = rm[20:11];
|
||||
end else begin // no normalization shift needed
|
||||
ue = re;
|
||||
uf = rm[19:10];
|
||||
end
|
||||
|
||||
// overflow
|
||||
always_comb begin
|
||||
ueb = ue-7'd15;
|
||||
if (ue >= 7'd46) begin // overflow
|
||||
/* uebiased = 7'd30;
|
||||
uff = 10'h3ff; */
|
||||
end else begin
|
||||
uebiased = ue-7'd15;
|
||||
uff = uf;
|
||||
end
|
||||
end
|
||||
|
||||
assign result = {rs, uebiased[4:0], uff};
|
||||
|
||||
// add special case handling for zeros, NaN, Infinity
|
||||
endmodule
|
||||
|
||||
module signadj16(
|
||||
input logic negr, negz,
|
||||
input logic xs, ys, zs1,
|
||||
output logic ps, zs);
|
||||
|
||||
assign ps = xs ^ ys; // sign of product
|
||||
assign zs = zs1 ^ negz; // sign of addend
|
||||
endmodule
|
||||
|
||||
module unpack16(
|
||||
input logic [15:0] x, y, z,
|
||||
output logic [10:0] xm, ym, zm,
|
||||
output logic [4:0] xe, ye, ze,
|
||||
output logic xs, ys, zs,
|
||||
output logic xzero, yzero, zzero, xinf, yinf, zinf, xnan, ynan, znan);
|
||||
|
||||
unpacknum16 upx(x, xm, xe, xs, xzero, xinf, xnan);
|
||||
unpacknum16 upy(y, ym, ye, ys, yzero, yinf, ynan);
|
||||
unpacknum16 upz(z, zm, ze, zs, zzero, zinf, znan);
|
||||
endmodule
|
||||
|
||||
module unpacknum16(
|
||||
input logic [15:0] num,
|
||||
output logic [10:0] m,
|
||||
output logic [4:0] e,
|
||||
output logic s,
|
||||
output logic zero, inf, nan);
|
||||
|
||||
logic [9:0] f; // fraction without leading 1
|
||||
logic [4:0] eb; // biased exponent
|
||||
|
||||
assign {s, eb, f} = num; // pull bit fields out of floating-point number
|
||||
assign m = {1'b1, f}; // prepend leading 1 to fraction
|
||||
assign e = eb; // leave bias in exponent ***
|
||||
assign zero = (e == 0 && f == 0);
|
||||
assign inf = (e == 31 && f == 0);
|
||||
assign nan = (e == 31 && f != 0);
|
||||
endmodule
|
||||
|
||||
|
||||
24
examples/verilog/fma/fma16_template.v
Normal file
24
examples/verilog/fma/fma16_template.v
Normal file
@ -0,0 +1,24 @@
|
||||
// fma16.sv
|
||||
// David_Harris@hmc.edu 26 February 2022
|
||||
// 16-bit floating-point multiply-accumulate
|
||||
|
||||
// Operation: general purpose multiply, add, fma, with optional negation
|
||||
// If mul=1, p = x * y. Else p = x.
|
||||
// If add=1, result = p + z. Else result = p.
|
||||
// If negr or negz = 1, negate result or z to handle negations and subtractions
|
||||
// fadd: mul = 0, add = 1, negr = negz = 0
|
||||
// fsub: mul = 0, add = 1, negr = 0, negz = 1
|
||||
// fmul: mul = 1, add = 0, negr = 0, negz = 0
|
||||
// fmadd: mul = 1, add = 1, negr = 0, negz = 0
|
||||
// fmsub: mul = 1, add = 1, negr = 0, negz = 1
|
||||
// fnmadd: mul = 1, add = 1, negr = 1, negz = 0
|
||||
// fnmsub: mul = 1, add = 1, negr = 1, negz = 1
|
||||
|
||||
module fma16(
|
||||
input logic [15:0] x, y, z,
|
||||
input logic mul, add, negr, negz,
|
||||
input logic [1:0] roundmode, // 00: rz, 01: rne, 10: rp, 11: rn
|
||||
output logic [15:0] result);
|
||||
|
||||
endmodule
|
||||
|
||||
240
examples/verilog/fma/fma16_testgen.c
Normal file
240
examples/verilog/fma/fma16_testgen.c
Normal file
@ -0,0 +1,240 @@
|
||||
#include <stdio.h>
|
||||
#include <stdint.h>
|
||||
#include "softfloat.h"
|
||||
#include "softfloat_types.h"
|
||||
|
||||
typedef union sp {
|
||||
float32_t v;
|
||||
float f;
|
||||
} sp;
|
||||
|
||||
// lists of tests, terminated with 0x8000
|
||||
uint16_t easyExponents[] = {15, 0x8000};
|
||||
uint16_t medExponents[] = {1, 14, 15, 16, 20, 30, 0x8000};
|
||||
uint16_t allExponents[] = {1, 15, 16, 30, 31, 0x8000};
|
||||
uint16_t easyFracts[] = {0, 0x200, 0x8000}; // 1.0 and 1.1
|
||||
uint16_t medFracts[] = {0, 0x200, 0x001, 0x3FF, 0x8000};
|
||||
uint16_t zeros[] = {0x0000, 0x8000};
|
||||
uint16_t infs[] = {0x7C00, 0xFC00};
|
||||
uint16_t nans[] = {0x7D00, 0x7D01};
|
||||
|
||||
void softfloatInit(void) {
|
||||
softfloat_roundingMode = softfloat_round_minMag;
|
||||
softfloat_exceptionFlags = 0;
|
||||
softfloat_detectTininess = softfloat_tininess_beforeRounding;
|
||||
}
|
||||
|
||||
float convFloat(float16_t f16) {
|
||||
float32_t f32;
|
||||
float res;
|
||||
sp r;
|
||||
|
||||
f32 = f16_to_f32(f16);
|
||||
r.v = f32;
|
||||
res = r.f;
|
||||
return res;
|
||||
}
|
||||
|
||||
void genCase(FILE *fptr, float16_t x, float16_t y, float16_t z, int mul, int add, int negp, int negz, int roundingMode, int zeroAllowed, int infAllowed, int nanAllowed) {
|
||||
float16_t result;
|
||||
int op, flagVals;
|
||||
char calc[80], flags[80];
|
||||
float32_t x32, y32, z32, r32;
|
||||
float xf, yf, zf, rf;
|
||||
float16_t smallest;
|
||||
|
||||
if (!mul) y.v = 0x3C00; // force y to 1 to avoid multiply
|
||||
if (!add) z.v = 0x0000; // force z to 0 to avoid add
|
||||
if (negp) x.v ^= 0x8000; // flip sign of x to negate p
|
||||
if (negz) z.v ^= 0x8000; // flip sign of z to negate z
|
||||
op = roundingMode << 4 | mul<<3 | add<<2 | negp<<1 | negz;
|
||||
// printf("op = %02x rm %d mul %d add %d negp %d negz %d\n", op, roundingMode, mul, add, negp, negz);
|
||||
softfloat_exceptionFlags = 0; // clear exceptions
|
||||
result = f16_mulAdd(x, y, z);
|
||||
|
||||
sprintf(flags, "NV: %d OF: %d UF: %d NX: %d",
|
||||
(softfloat_exceptionFlags >> 4) % 2,
|
||||
(softfloat_exceptionFlags >> 2) % 2,
|
||||
(softfloat_exceptionFlags >> 1) % 2,
|
||||
(softfloat_exceptionFlags) % 2);
|
||||
// pack these four flags into one nibble, discarding DZ flag
|
||||
flagVals = softfloat_exceptionFlags & 0x7 | ((softfloat_exceptionFlags >> 1) & 0x8);
|
||||
|
||||
|
||||
// convert to floats for printing
|
||||
xf = convFloat(x);
|
||||
yf = convFloat(y);
|
||||
zf = convFloat(z);
|
||||
rf = convFloat(result);
|
||||
if (mul)
|
||||
if (add) sprintf(calc, "%f * %f + %f = %f", xf, yf, zf, rf);
|
||||
else sprintf(calc, "%f * %f = %f", xf, yf, rf);
|
||||
else sprintf(calc, "%f + %f = %f", xf, zf, rf);
|
||||
|
||||
// omit denorms, which aren't required for this project
|
||||
smallest.v = 0x0400;
|
||||
float16_t resultmag = result;
|
||||
resultmag.v &= 0x7FFF; // take absolute value
|
||||
if (f16_lt(resultmag, smallest) && (resultmag.v != 0x0000)) fprintf (fptr, "// skip denorm: ");
|
||||
if (resultmag.v == 0x0000 && !zeroAllowed) fprintf(fptr, "// skip zero: ");
|
||||
if ((resultmag.v == 0x7C00 || resultmag.v == 0x7BFF) && !infAllowed) fprintf(fptr, "// Skip inf: ");
|
||||
if (resultmag.v > 0x7C00 && !nanAllowed) fprintf(fptr, "// Skip NaN: ");
|
||||
fprintf(fptr, "%04x_%04x_%04x_%02x_%04x_%01x // %s %s\n", x.v, y.v, z.v, op, result.v, flagVals, calc, flags);
|
||||
}
|
||||
|
||||
void prepTests(uint16_t *e, uint16_t *f, char *testName, char *desc, float16_t *cases,
|
||||
FILE *fptr, int *numCases) {
|
||||
int i, j;
|
||||
|
||||
fprintf(fptr, desc); fprintf(fptr, "\n");
|
||||
*numCases=0;
|
||||
for (i=0; e[i] != 0x8000; i++)
|
||||
for (j=0; f[j] != 0x8000; j++) {
|
||||
cases[*numCases].v = f[j] | e[i]<<10;
|
||||
*numCases = *numCases + 1;
|
||||
}
|
||||
}
|
||||
|
||||
void genMulTests(uint16_t *e, uint16_t *f, int sgn, char *testName, char *desc, int roundingMode, int zeroAllowed, int infAllowed, int nanAllowed) {
|
||||
int i, j, k, numCases;
|
||||
float16_t x, y, z;
|
||||
float16_t cases[100000];
|
||||
FILE *fptr;
|
||||
char fn[80];
|
||||
|
||||
sprintf(fn, "work/%s.tv", testName);
|
||||
fptr = fopen(fn, "w");
|
||||
prepTests(e, f, testName, desc, cases, fptr, &numCases);
|
||||
z.v = 0x0000;
|
||||
for (i=0; i < numCases; i++) {
|
||||
x.v = cases[i].v;
|
||||
for (j=0; j<numCases; j++) {
|
||||
y.v = cases[j].v;
|
||||
for (k=0; k<=sgn; k++) {
|
||||
y.v ^= (k<<15);
|
||||
genCase(fptr, x, y, z, 1, 0, 0, 0, roundingMode, zeroAllowed, infAllowed, nanAllowed);
|
||||
}
|
||||
}
|
||||
}
|
||||
fclose(fptr);
|
||||
}
|
||||
|
||||
void genAddTests(uint16_t *e, uint16_t *f, int sgn, char *testName, char *desc, int roundingMode, int zeroAllowed, int infAllowed, int nanAllowed) {
|
||||
int i, j, k, numCases;
|
||||
float16_t x, y, z;
|
||||
float16_t cases[100000];
|
||||
FILE *fptr;
|
||||
char fn[80];
|
||||
|
||||
sprintf(fn, "work/%s.tv", testName);
|
||||
fptr = fopen(fn, "w");
|
||||
prepTests(e, f, testName, desc, cases, fptr, &numCases);
|
||||
y.v = 0x0000;
|
||||
for (i=0; i < numCases; i++) {
|
||||
x.v = cases[i].v;
|
||||
for (j=0; j<numCases; j++) {
|
||||
z.v = cases[j].v;
|
||||
for (k=0; k<=sgn; k++) {
|
||||
z.v ^= (k<<15);
|
||||
genCase(fptr, x, y, z, 0, 1, 0, 0, roundingMode, zeroAllowed, infAllowed, nanAllowed);
|
||||
}
|
||||
}
|
||||
}
|
||||
fclose(fptr);
|
||||
}
|
||||
|
||||
|
||||
void genFMATests(uint16_t *e, uint16_t *f, int sgn, char *testName, char *desc, int roundingMode, int zeroAllowed, int infAllowed, int nanAllowed) {
|
||||
int i, j, k, l, numCases;
|
||||
float16_t x, y, z;
|
||||
float16_t cases[100000];
|
||||
FILE *fptr;
|
||||
char fn[80];
|
||||
|
||||
sprintf(fn, "work/%s.tv", testName);
|
||||
fptr = fopen(fn, "w");
|
||||
prepTests(e, f, testName, desc, cases, fptr, &numCases);
|
||||
for (i=0; i < numCases; i++) {
|
||||
x.v = cases[i].v;
|
||||
for (j=0; j<numCases; j++) {
|
||||
y.v = cases[j].v;
|
||||
for (k=0; k<numCases; k++) {
|
||||
z.v = cases[k].v;
|
||||
for (l=0; l<=sgn; l++) {
|
||||
z.v ^= (l<<15);
|
||||
genCase(fptr, x, y, z, 1, 1, 0, 0, roundingMode, zeroAllowed, infAllowed, nanAllowed);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
fclose(fptr);
|
||||
}
|
||||
|
||||
void genSpecialTests(uint16_t *e, uint16_t *f, int sgn, char *testName, char *desc, int roundingMode, int zeroAllowed, int infAllowed, int nanAllowed) {
|
||||
int i, j, k, sx, sy, sz, numCases;
|
||||
float16_t x, y, z;
|
||||
float16_t cases[100000];
|
||||
FILE *fptr;
|
||||
char fn[80];
|
||||
|
||||
sprintf(fn, "work/%s.tv", testName);
|
||||
fptr = fopen(fn, "w");
|
||||
prepTests(e, f, testName, desc, cases, fptr, &numCases);
|
||||
cases[numCases].v = 0x0000; // add +0 case
|
||||
cases[numCases+1].v = 0x8000; // add -0 case
|
||||
numCases += 2;
|
||||
for (i=0; i < numCases; i++) {
|
||||
x.v = cases[i].v;
|
||||
for (j=0; j<numCases; j++) {
|
||||
y.v = cases[j].v;
|
||||
for (k=0; k<numCases; k++) {
|
||||
z.v = cases[k].v;
|
||||
for (sx=0; sx<=sgn; sx++) {
|
||||
x.v ^= (sx<<15);
|
||||
for (sy=0; sy<=sgn; sy++) {
|
||||
y.v ^= (sy<<15);
|
||||
for (sz=0; sz<=sgn; sz++) {
|
||||
z.v ^= (sz<<15);
|
||||
genCase(fptr, x, y, z, 1, 1, 0, 0, roundingMode, zeroAllowed, infAllowed, nanAllowed);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
fclose(fptr);
|
||||
}
|
||||
|
||||
|
||||
int main()
|
||||
{
|
||||
softfloatInit(); // configure softfloat modes
|
||||
|
||||
// Test cases: multiplication
|
||||
genMulTests(easyExponents, easyFracts, 0, "fmul_0", "// Multiply with exponent of 0, significand of 1.0 and 1.1, RZ", 0, 0, 0, 0);
|
||||
genMulTests(medExponents, medFracts, 0, "fmul_1", "// Multiply with various exponents and unsigned fractions, RZ", 0, 0, 0, 0);
|
||||
genMulTests(medExponents, medFracts, 1, "fmul_2", "// Multiply with various exponents and signed fractions, RZ", 0, 0, 0, 0);
|
||||
|
||||
// Test cases: addition
|
||||
genAddTests(easyExponents, easyFracts, 0, "fadd_0", "// Add with exponent of 0, significand of 1.0 and 1.1, RZ", 0, 0, 0, 0);
|
||||
genAddTests(medExponents, medFracts, 0, "fadd_1", "// Add with various exponents and unsigned fractions, RZ", 0, 0, 0, 0);
|
||||
genAddTests(medExponents, medFracts, 1, "fadd_2", "// Add with various exponents and signed fractions, RZ", 0, 0, 0, 0);
|
||||
|
||||
// Test cases: FMA
|
||||
genFMATests(easyExponents, easyFracts, 0, "fma_0", "// FMA with exponent of 0, significand of 1.0 and 1.1, RZ", 0, 0, 0, 0);
|
||||
genFMATests(medExponents, medFracts, 0, "fma_1", "// FMA with various exponents and unsigned fractions, RZ", 0, 0, 0, 0);
|
||||
genFMATests(medExponents, medFracts, 1, "fma_2", "// FMA with various exponents and signed fractions, RZ", 0, 0, 0, 0);
|
||||
|
||||
// Test cases: Zero, Infinity, NaN
|
||||
genSpecialTests(allExponents, medFracts, 1, "fma_special_rz", "// FMA with special cases, RZ", 0, 1, 1, 1);
|
||||
|
||||
// Full test cases with other rounding modes
|
||||
softfloat_roundingMode = softfloat_round_near_even;
|
||||
genSpecialTests(allExponents, medFracts, 1, "fma_special_rne", "// FMA with special cases, RNE", 1, 1, 1, 1);
|
||||
softfloat_roundingMode = softfloat_round_min;
|
||||
genSpecialTests(allExponents, medFracts, 1, "fma_special_rm", "// FMA with special cases, RM", 2, 1, 1, 1);
|
||||
softfloat_roundingMode = softfloat_round_max;
|
||||
genSpecialTests(allExponents, medFracts, 1, "fma_special_rp", "// FMA with special cases, RP", 3, 1, 1, 1);
|
||||
|
||||
return 0;
|
||||
}
|
||||
8
examples/verilog/fma/lint-fma
Executable file
8
examples/verilog/fma/lint-fma
Executable file
@ -0,0 +1,8 @@
|
||||
#!/bin/bash
|
||||
# check for warnings in Verilog code
|
||||
# The verilator lint tool is faster and better than Modelsim so it is best to run this first.
|
||||
export PATH=$PATH:/usr/local/bin/
|
||||
verilator=`which verilator`
|
||||
|
||||
basepath=$(dirname $0)/..
|
||||
$verilator --lint-only --top-module fma16 fma16.v
|
||||
2
examples/verilog/fma/sim-fma
Executable file
2
examples/verilog/fma/sim-fma
Executable file
@ -0,0 +1,2 @@
|
||||
vsim -do "do fma.do"
|
||||
|
||||
1
examples/verilog/fma/sim-fma-batch
Executable file
1
examples/verilog/fma/sim-fma-batch
Executable file
@ -0,0 +1 @@
|
||||
vsim -c -do "do fma.do"
|
||||
1
examples/verilog/fma/synth
Executable file
1
examples/verilog/fma/synth
Executable file
@ -0,0 +1 @@
|
||||
make -C ../../../synthDC synth DESIGN=fma16
|
||||
52
examples/verilog/fma/testbench.v
Normal file
52
examples/verilog/fma/testbench.v
Normal file
@ -0,0 +1,52 @@
|
||||
/* verilator lint_off STMTDLY */
|
||||
module testbench_fma16;
|
||||
reg clk, reset;
|
||||
reg [15:0] x, y, z, rexpected;
|
||||
wire [15:0] result;
|
||||
reg [7:0] ctrl;
|
||||
reg [3:0] flagsexpected;
|
||||
reg mul, add, negp, negz;
|
||||
reg [1:0] roundmode;
|
||||
reg [31:0] vectornum, errors;
|
||||
reg [75:0] testvectors[10000:0];
|
||||
|
||||
// instantiate device under test
|
||||
fma16 dut(x, y, z, mul, add, negp, negz, roundmode, result);
|
||||
|
||||
// generate clock
|
||||
always
|
||||
begin
|
||||
clk = 1; #5; clk = 0; #5;
|
||||
end
|
||||
|
||||
// at start of test, load vectors and pulse reset
|
||||
initial
|
||||
begin
|
||||
$readmemh("work/fmul_0.tv", testvectors);
|
||||
vectornum = 0; errors = 0;
|
||||
reset = 1; #22; reset = 0;
|
||||
end
|
||||
|
||||
// apply test vectors on rising edge of clk
|
||||
always @(posedge clk)
|
||||
begin
|
||||
#1; {x, y, z, ctrl, rexpected, flagsexpected} = testvectors[vectornum];
|
||||
{roundmode, mul, add, negp, negz} = ctrl[5:0];
|
||||
end
|
||||
|
||||
// check results on falling edge of clk
|
||||
always @(negedge clk)
|
||||
if (~reset) begin // skip during reset
|
||||
if (result !== rexpected) begin // check result // *** should also add tests on flags eventually
|
||||
$display("Error: inputs %h * %h + %h", x, y, z);
|
||||
$display(" result = %h (%h expected)", result, rexpected);
|
||||
errors = errors + 1;
|
||||
end
|
||||
vectornum = vectornum + 1;
|
||||
if (testvectors[vectornum] === 'x) begin
|
||||
$display("%d tests completed with %d errors",
|
||||
vectornum, errors);
|
||||
$stop;
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
86257
examples/verilog/fma/torture.tv
Normal file
86257
examples/verilog/fma/torture.tv
Normal file
File diff suppressed because it is too large
Load Diff
130
examples/verilog/fma/torturegen.pl
Executable file
130
examples/verilog/fma/torturegen.pl
Executable file
@ -0,0 +1,130 @@
|
||||
#!/usr/bin/perl -w
|
||||
# torturegen.pl
|
||||
# David_Harris@hmc.edu 19 April 2022
|
||||
# Convert TestFloat cases into format for fma16 project torture test
|
||||
# Strip out cases involving denorms
|
||||
|
||||
use strict;
|
||||
|
||||
my @basenames = ("add", "mul", "mulAdd");
|
||||
my @roundingmodes = ("rz", "rd", "ru", "rne");
|
||||
my @names = ();
|
||||
foreach my $name (@basenames) {
|
||||
foreach my $mode (@roundingmodes) {
|
||||
push(@names, "f16_${name}_$mode.tv");
|
||||
}
|
||||
}
|
||||
|
||||
open(TORTURE, ">work/torture.tv") || die("Can't write torture.tv");
|
||||
my $datestring = localtime();
|
||||
print(TORTURE "// Torture tests generated $datestring by $0\n");
|
||||
foreach my $tv (@names) {
|
||||
open(TV, "work/$tv") || die("Can't read $tv");
|
||||
my $type = &getType($tv); # is it mul, add, mulAdd
|
||||
my $rm = &getRm($tv); # rounding mode
|
||||
# if ($rm != 0) { next; } # only do rz
|
||||
print (TORTURE "\n////////// Testcases from $tv of type $type rounding mode $rm\n");
|
||||
print ("\n////////// Testcases from $tv of type $type rounding mode $rm\n");
|
||||
my $linecount = 0;
|
||||
my $babyTorture = 0;
|
||||
while (<TV>) {
|
||||
my $line = $_;
|
||||
$linecount++;
|
||||
my $density = 10;
|
||||
if ($type eq "mulAdd") {$density = 500;}
|
||||
if ($babyTorture) {
|
||||
$density = 100;
|
||||
if ($type eq "mulAdd") {$density = 50000;}
|
||||
}
|
||||
if ((($linecount + $rm) % $density) != 0) { next }; # too many tests to use
|
||||
chomp($line); # strip off newline
|
||||
my @parts = split(/_/, $line);
|
||||
my ($x, $y, $z, $op, $w, $flags);
|
||||
$x = $parts[0];
|
||||
if ($type eq "add") { $y = "0000"; } else {$y = $parts[1]};
|
||||
if ($type eq "mul") { $z = "3CFF"; } elsif ($type eq "add") {$z = $parts[1]} else { $z = $parts[2]};
|
||||
$op = $rm << 4;
|
||||
if ($type eq "mul" || $type eq "mulAdd") { $op = $op + 8; }
|
||||
if ($type eq "add" || $type eq "mulAdd") { $op = $op + 4; }
|
||||
my $opname = sprintf("%02x", $op);
|
||||
if ($type eq "mulAdd") {$w = $parts[3];} else {$w = $parts[2]};
|
||||
if ($type eq "mulAdd") {$flags = $parts[4];} else {$flags = $parts[3]};
|
||||
$flags = substr($flags, -1); # take last character
|
||||
if (&fpval($w) eq "NaN") { $w = "7e00"; }
|
||||
my $vec = "${x}_${y}_${z}_${opname}_${w}_${flags}";
|
||||
my $skip = "";
|
||||
if (&isdenorm($x) || &isdenorm($y) || &isdenorm($z) || &isdenorm($w)) {
|
||||
$skip = "Skipped denorm";
|
||||
}
|
||||
my $summary = &summary($x, $y, $z, $w, $type);
|
||||
if ($skip ne "") {
|
||||
print TORTURE "// $skip $tv line $linecount $line $summary\n"
|
||||
}
|
||||
else { print TORTURE "$vec // $tv line $linecount $line $summary\n";}
|
||||
}
|
||||
close(TV);
|
||||
}
|
||||
close(TORTURE);
|
||||
|
||||
sub fpval {
|
||||
my $val = shift;
|
||||
$val = hex($val); # convert hex string to number
|
||||
my $frac = $val & 0x3FF;
|
||||
my $exp = ($val >> 10) & 0x1F;
|
||||
my $sign = $val >> 15;
|
||||
|
||||
my $res;
|
||||
if ($exp == 31 && $frac != 0) { return "NaN"; }
|
||||
elsif ($exp == 31) { $res = "INF"; }
|
||||
elsif ($val == 0) { $res = 0; }
|
||||
elsif ($exp == 0) { $res = "Denorm"; }
|
||||
else { $res = sprintf("1.%011b x 2^%d", $frac, $exp-15); }
|
||||
|
||||
if ($sign == 1) { $res = "-$res"; }
|
||||
return $res;
|
||||
}
|
||||
|
||||
sub summary {
|
||||
my $x = shift; my $y = shift; my $z = shift; my $w = shift; my $type = shift;
|
||||
|
||||
my $xv = &fpval($x);
|
||||
my $yv = &fpval($y);
|
||||
my $zv = &fpval($z);
|
||||
my $wv = &fpval($w);
|
||||
|
||||
if ($type eq "add") { return "$xv + $zv = $wv"; }
|
||||
elsif ($type eq "mul") { return "$xv * $yv = $wv"; }
|
||||
else {return "$xv * $yv + $zv = $wv"; }
|
||||
}
|
||||
|
||||
sub getType {
|
||||
my $tv = shift;
|
||||
|
||||
if ($tv =~ /mulAdd/) { return("mulAdd"); }
|
||||
elsif ($tv =~ /mul/) { return "mul"; }
|
||||
else { return "add"; }
|
||||
}
|
||||
|
||||
sub getRm {
|
||||
my $tv = shift;
|
||||
|
||||
if ($tv =~ /rz/) { return 0; }
|
||||
elsif ($tv =~ /rne/) { return 1; }
|
||||
elsif ($tv =~ /rd/) {return 2; }
|
||||
elsif ($tv =~ /ru/) { return 3; }
|
||||
else { return "bad"; }
|
||||
}
|
||||
|
||||
sub isdenorm {
|
||||
my $fp = shift;
|
||||
my $val = hex($fp);
|
||||
my $expv = $val >> 10;
|
||||
$expv = $expv & 0x1F;
|
||||
my $denorm = 0;
|
||||
if ($expv == 0 && $val != 0) { $denorm = 1;}
|
||||
# my $e0 = ($expv == 0);
|
||||
# my $vn0 = ($val != 0);
|
||||
# my $denorm = 0; #($exp == 0 && $val != 0); # denorm exponent but not all zero
|
||||
# print("Num $fp Exp $expv Denorm $denorm Done\n");
|
||||
return $denorm;
|
||||
}
|
||||
62
examples/verilog/fma/wave.do
Normal file
62
examples/verilog/fma/wave.do
Normal file
@ -0,0 +1,62 @@
|
||||
onerror {resume}
|
||||
quietly WaveActivateNextPane {} 0
|
||||
add wave -noupdate /testbench_fma16/clk
|
||||
add wave -noupdate /testbench_fma16/reset
|
||||
add wave -noupdate /testbench_fma16/x
|
||||
add wave -noupdate /testbench_fma16/y
|
||||
add wave -noupdate /testbench_fma16/z
|
||||
add wave -noupdate /testbench_fma16/result
|
||||
add wave -noupdate /testbench_fma16/rexpected
|
||||
add wave -noupdate /testbench_fma16/dut/x
|
||||
add wave -noupdate /testbench_fma16/dut/y
|
||||
add wave -noupdate /testbench_fma16/dut/z
|
||||
add wave -noupdate /testbench_fma16/dut/mul
|
||||
add wave -noupdate /testbench_fma16/dut/add
|
||||
add wave -noupdate /testbench_fma16/dut/negr
|
||||
add wave -noupdate /testbench_fma16/dut/negz
|
||||
add wave -noupdate /testbench_fma16/dut/roundmode
|
||||
add wave -noupdate /testbench_fma16/dut/result
|
||||
add wave -noupdate /testbench_fma16/dut/XManE
|
||||
add wave -noupdate /testbench_fma16/dut/YManE
|
||||
add wave -noupdate /testbench_fma16/dut/ZManE
|
||||
add wave -noupdate /testbench_fma16/dut/XExpE
|
||||
add wave -noupdate /testbench_fma16/dut/YExpE
|
||||
add wave -noupdate /testbench_fma16/dut/ZExpE
|
||||
add wave -noupdate /testbench_fma16/dut/PExpE
|
||||
add wave -noupdate /testbench_fma16/dut/Ne
|
||||
add wave -noupdate /testbench_fma16/dut/upOneExt
|
||||
add wave -noupdate /testbench_fma16/dut/XSgnE
|
||||
add wave -noupdate /testbench_fma16/dut/YSgnE
|
||||
add wave -noupdate /testbench_fma16/dut/ZSgnE
|
||||
add wave -noupdate /testbench_fma16/dut/PSgnE
|
||||
add wave -noupdate /testbench_fma16/dut/ProdManE
|
||||
add wave -noupdate /testbench_fma16/dut/NfracS
|
||||
add wave -noupdate /testbench_fma16/dut/ProdManAl
|
||||
add wave -noupdate /testbench_fma16/dut/ZManExt
|
||||
add wave -noupdate /testbench_fma16/dut/ZManAl
|
||||
add wave -noupdate /testbench_fma16/dut/Nfrac
|
||||
add wave -noupdate /testbench_fma16/dut/res
|
||||
add wave -noupdate -radix decimal /testbench_fma16/dut/AlignCnt
|
||||
add wave -noupdate /testbench_fma16/dut/NSamt
|
||||
add wave -noupdate /testbench_fma16/dut/ZExpGreater
|
||||
add wave -noupdate /testbench_fma16/dut/ACLess
|
||||
add wave -noupdate /testbench_fma16/dut/upOne
|
||||
add wave -noupdate /testbench_fma16/dut/KillProd
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {{Cursor 1} {3746 ns} 1} {{Cursor 2} {4169 ns} 0}
|
||||
quietly wave cursor active 2
|
||||
configure wave -namecolwidth 237
|
||||
configure wave -valuecolwidth 64
|
||||
configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 0
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
configure wave -gridoffset 0
|
||||
configure wave -gridperiod 1
|
||||
configure wave -griddelta 40
|
||||
configure wave -timeline 0
|
||||
configure wave -timelineunits ns
|
||||
update
|
||||
WaveRestoreZoom {4083 ns} {4235 ns}
|
||||
@ -16,7 +16,7 @@ a large number of debuging signals.
|
||||
|
||||
* Programming the flash card
|
||||
You'll need to write the linux image to the flash card. Use the convert2bin.py
|
||||
script in linux-testgen/linux-testvectors/ [*** moved?] to convert the ram.txt
|
||||
script in pipelined/linux-testgen/linux-testvectors/ to convert the ram.txt
|
||||
file from QEMU's preload to generate the binary. Then to copy
|
||||
sudo dd if=ram.bin of=<path to flash card>.
|
||||
|
||||
|
||||
@ -1,48 +0,0 @@
|
||||
NET "ddr3_dq[0]" LOC = "K5" | IOSTANDARD = SSTL15 ;
|
||||
NET "ddr3_dq[1]" LOC = "L3" | IOSTANDARD = SSTL15 ;
|
||||
NET "ddr3_dq[2]" LOC = "K3" | IOSTANDARD = SSTL15 ;
|
||||
NET "ddr3_dq[3]" LOC = "L6" | IOSTANDARD = SSTL15 ;
|
||||
NET "ddr3_dq[4]" LOC = "M3" | IOSTANDARD = SSTL15 ;
|
||||
NET "ddr3_dq[5]" LOC = "M1" | IOSTANDARD = SSTL15 ;
|
||||
NET "ddr3_dq[6]" LOC = "L4" | IOSTANDARD = SSTL15 ;
|
||||
NET "ddr3_dq[7]" LOC = "M2" | IOSTANDARD = SSTL15 ;
|
||||
NET "ddr3_dq[8]" LOC = "V4" | IOSTANDARD = SSTL15 ;
|
||||
NET "ddr3_dq[9]" LOC = "T5" | IOSTANDARD = SSTL15 ;
|
||||
NET "ddr3_dq[10]" LOC = "U4" | IOSTANDARD = SSTL15 ;
|
||||
NET "ddr3_dq[11]" LOC = "V5" | IOSTANDARD = SSTL15 ;
|
||||
NET "ddr3_dq[12]" LOC = "V1" | IOSTANDARD = SSTL15 ;
|
||||
NET "ddr3_dq[13]" LOC = "T3" | IOSTANDARD = SSTL15 ;
|
||||
NET "ddr3_dq[14]" LOC = "U3" | IOSTANDARD = SSTL15 ;
|
||||
NET "ddr3_dq[15]" LOC = "R3" | IOSTANDARD = SSTL15 ;
|
||||
NET "ddr3_dm[0]" LOC = "L1" | IOSTANDARD = SSTL15 ;
|
||||
NET "ddr3_dm[1]" LOC = "U1" | IOSTANDARD = SSTL15 ;
|
||||
NET "ddr3_dqs_p[0]" LOC = "N2" | IOSTANDARD = DIFF_SSTL15 ;
|
||||
NET "ddr3_dqs_n[0]" LOC = "N1" | IOSTANDARD = DIFF_SSTL15 ;
|
||||
NET "ddr3_dqs_p[1]" LOC = "U2" | IOSTANDARD = DIFF_SSTL15 ;
|
||||
NET "ddr3_dqs_n[1]" LOC = "V2" | IOSTANDARD = DIFF_SSTL15 ;
|
||||
NET "ddr3_addr[13]" LOC = "T8" | IOSTANDARD = SSTL15 ;
|
||||
NET "ddr3_addr[12]" LOC = "T6" | IOSTANDARD = SSTL15 ;
|
||||
NET "ddr3_addr[11]" LOC = "U6" | IOSTANDARD = SSTL15 ;
|
||||
NET "ddr3_addr[10]" LOC = "R6" | IOSTANDARD = SSTL15 ;
|
||||
NET "ddr3_addr[9]" LOC = "V7" | IOSTANDARD = SSTL15 ;
|
||||
NET "ddr3_addr[8]" LOC = "R8" | IOSTANDARD = SSTL15 ;
|
||||
NET "ddr3_addr[7]" LOC = "U7" | IOSTANDARD = SSTL15 ;
|
||||
NET "ddr3_addr[6]" LOC = "V6" | IOSTANDARD = SSTL15 ;
|
||||
NET "ddr3_addr[5]" LOC = "R7" | IOSTANDARD = SSTL15 ;
|
||||
NET "ddr3_addr[4]" LOC = "N6" | IOSTANDARD = SSTL15 ;
|
||||
NET "ddr3_addr[3]" LOC = "T1" | IOSTANDARD = SSTL15 ;
|
||||
NET "ddr3_addr[2]" LOC = "N4" | IOSTANDARD = SSTL15 ;
|
||||
NET "ddr3_addr[1]" LOC = "M6" | IOSTANDARD = SSTL15 ;
|
||||
NET "ddr3_addr[0]" LOC = "R2" | IOSTANDARD = SSTL15 ;
|
||||
NET "ddr3_ba[2]" LOC = "P2" | IOSTANDARD = SSTL15 ;
|
||||
NET "ddr3_ba[1]" LOC = "P4" | IOSTANDARD = SSTL15 ;
|
||||
NET "ddr3_ba[0]" LOC = "R1" | IOSTANDARD = SSTL15 ;
|
||||
NET "ddr3_ck_p[0]" LOC = "U9" | IOSTANDARD = DIFF_SSTL15 ;
|
||||
NET "ddr3_ck_n[0]" LOC = "V9" | IOSTANDARD = DIFF_SSTL15 ;
|
||||
NET "ddr3_ras_n" LOC = "P3" | IOSTANDARD = SSTL15 ;
|
||||
NET "ddr3_cas_n" LOC = "M4" | IOSTANDARD = SSTL15 ;
|
||||
NET "ddr3_we_n" LOC = "P5" | IOSTANDARD = SSTL15 ;
|
||||
NET "ddr3_reset_n" LOC = "K6" | IOSTANDARD = LVCMOS15 ;
|
||||
NET "ddr3_cke[0]" LOC = "N5" | IOSTANDARD = SSTL15 ;
|
||||
NET "ddr3_odt[0]" LOC = "R5" | IOSTANDARD = SSTL15 ;
|
||||
NET "ddr3_cs_n[0]" LOC = "U8" | IOSTANDARD = SSTL15 ;
|
||||
@ -1,219 +0,0 @@
|
||||
# The main clocks are all autogenerated by the Xilinx IP
|
||||
# clk_out3_xlnx_mmcm is the 20Mhz clock from the mmcm used to drive wally and the AHB Bus.
|
||||
# mmcm_clkout0 is the clock output of the DDR3 memory interface / 4.
|
||||
# This clock is not used by wally or the AHB Bus. However it is used by the AXI BUS on the DD3 IP.
|
||||
|
||||
create_generated_clock -name CLKDiv64_Gen -source [get_pins wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/I0] -multiply_by 1 -divide_by 1 [get_pins wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/O]
|
||||
|
||||
##### clock #####
|
||||
set_property PACKAGE_PIN E3 [get_ports {default_100mhz_clk}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {default_100mhz_clk}]
|
||||
|
||||
##### GPI ####
|
||||
set_property PACKAGE_PIN A8 [get_ports {GPI[0]}]
|
||||
set_property PACKAGE_PIN C9 [get_ports {GPI[1]}]
|
||||
set_property PACKAGE_PIN B9 [get_ports {GPI[2]}]
|
||||
set_property PACKAGE_PIN B8 [get_ports {GPI[3]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {GPI[3]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {GPI[2]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {GPI[1]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {GPI[0]}]
|
||||
set_input_delay -clock [get_clocks clk_out3_xlnx_mmcm] -min -add_delay 0.000 [get_ports {GPI[*]}]
|
||||
set_input_delay -clock [get_clocks clk_out3_xlnx_mmcm] -max -add_delay 0.000 [get_ports {GPI[*]}]
|
||||
set_max_delay -from [get_ports {GPI[*]}] 10.000
|
||||
|
||||
##### GPO ####
|
||||
set_property PACKAGE_PIN G6 [get_ports {GPO[0]}]
|
||||
set_property PACKAGE_PIN F6 [get_ports {GPO[1]}]
|
||||
set_property PACKAGE_PIN E1 [get_ports {GPO[2]}]
|
||||
set_property PACKAGE_PIN G3 [get_ports {GPO[4]}]
|
||||
set_property PACKAGE_PIN J4 [get_ports {GPO[3]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {GPO[4]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {GPO[3]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {GPO[2]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {GPO[1]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {GPO[0]}]
|
||||
set_max_delay -to [get_ports {GPO[*]}] 10.000
|
||||
set_output_delay -clock [get_clocks clk_out3_xlnx_mmcm] -min -add_delay 0.000 [get_ports {GPO[*]}]
|
||||
set_output_delay -clock [get_clocks clk_out3_xlnx_mmcm] -max -add_delay 0.000 [get_ports {GPO[*]}]
|
||||
|
||||
|
||||
##### UART #####
|
||||
# *** IOSTANDARD is probably wrong
|
||||
set_property PACKAGE_PIN A9 [get_ports UARTSin]
|
||||
set_property PACKAGE_PIN D10 [get_ports UARTSout]
|
||||
set_max_delay -from [get_ports UARTSin] 14.000
|
||||
set_max_delay -to [get_ports UARTSout] 14.000
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports UARTSin]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports UARTSout]
|
||||
set_property DRIVE 4 [get_ports UARTSout]
|
||||
set_input_delay -clock [get_clocks clk_out3_xlnx_mmcm] -min -add_delay 0.000 [get_ports UARTSin]
|
||||
set_input_delay -clock [get_clocks clk_out3_xlnx_mmcm] -max -add_delay 0.000 [get_ports UARTSin]
|
||||
set_output_delay -clock [get_clocks clk_out3_xlnx_mmcm] -min -add_delay 0.000 [get_ports UARTSout]
|
||||
set_output_delay -clock [get_clocks clk_out3_xlnx_mmcm] -max -add_delay 0.000 [get_ports UARTSout]
|
||||
|
||||
|
||||
##### reset #####
|
||||
#************** reset is inverted
|
||||
set_input_delay -clock [get_clocks clk_out3_xlnx_mmcm] -min -add_delay 2.000 [get_ports resetn]
|
||||
set_input_delay -clock [get_clocks clk_out3_xlnx_mmcm] -max -add_delay 2.000 [get_ports resetn]
|
||||
set_max_delay -from [get_ports resetn] 15.000
|
||||
set_false_path -from [get_ports resetn]
|
||||
set_property PACKAGE_PIN C2 [get_ports {resetn}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {resetn}]
|
||||
|
||||
|
||||
set_input_delay -clock [get_clocks clk_out3_xlnx_mmcm] -min -add_delay 2.000 [get_ports south_reset]
|
||||
set_input_delay -clock [get_clocks clk_out3_xlnx_mmcm] -max -add_delay 2.000 [get_ports south_reset]
|
||||
set_max_delay -from [get_ports south_reset] 15.000
|
||||
set_false_path -from [get_ports south_reset]
|
||||
set_property PACKAGE_PIN D9 [get_ports {south_reset}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {south_reset}]
|
||||
|
||||
|
||||
|
||||
##### SD Card I/O #####
|
||||
#***** may have to switch to Pmod JB or JC.
|
||||
set_property PACKAGE_PIN D4 [get_ports {SDCDat[3]}]
|
||||
set_property PACKAGE_PIN D2 [get_ports {SDCDat[2]}]
|
||||
set_property PACKAGE_PIN E2 [get_ports {SDCDat[1]}]
|
||||
set_property PACKAGE_PIN F4 [get_ports {SDCDat[0]}]
|
||||
set_property PACKAGE_PIN F3 [get_ports SDCCLK]
|
||||
set_property PACKAGE_PIN D3 [get_ports {SDCCmd}]
|
||||
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {SDCDat[3]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {SDCDat[2]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {SDCDat[1]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {SDCDat[0]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports SDCCLK]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {SDCCmd}]
|
||||
set_property PULLUP true [get_ports {SDCDat[3]}]
|
||||
set_property PULLUP true [get_ports {SDCDat[2]}]
|
||||
set_property PULLUP true [get_ports {SDCDat[1]}]
|
||||
set_property PULLUP true [get_ports {SDCDat[0]}]
|
||||
set_property PULLUP true [get_ports {SDCCmd}]
|
||||
|
||||
|
||||
set_input_delay -clock [get_clocks CLKDiv64_Gen] -min -add_delay 2.500 [get_ports {SDCDat[*]}]
|
||||
set_input_delay -clock [get_clocks CLKDiv64_Gen] -max -add_delay 21.000 [get_ports {SDCDat[*]}]
|
||||
|
||||
set_input_delay -clock [get_clocks CLKDiv64_Gen] -min -add_delay 2.500 [get_ports {SDCCmd}]
|
||||
set_input_delay -clock [get_clocks CLKDiv64_Gen] -max -add_delay 14.000 [get_ports {SDCCmd}]
|
||||
|
||||
|
||||
set_output_delay -clock [get_clocks CLKDiv64_Gen] -min -add_delay 2.000 [get_ports {SDCCmd}]
|
||||
set_output_delay -clock [get_clocks CLKDiv64_Gen] -max -add_delay 6.000 [get_ports {SDCCmd}]
|
||||
|
||||
set_output_delay -clock [get_clocks CLKDiv64_Gen] 0.000 [get_ports SDCCLK]
|
||||
|
||||
# *********************************
|
||||
#set_property DCI_CASCADE {64} [get_iobanks 65]
|
||||
#set_property INTERNAL_VREF 0.9 [get_iobanks 65]
|
||||
|
||||
# ddr3
|
||||
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[0]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[1]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[2]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[3]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[4]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[5]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[6]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[7]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[8]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[9]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[10]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[11]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[12]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[13]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[14]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[15]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddr3_dm[0]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddr3_dm[1]
|
||||
set_property IOSTANDARD DIFF [get_ports ddr3_dqs_p[0]
|
||||
set_property IOSTANDARD DIFF [get_ports ddr3_dqs_n[0]
|
||||
set_property IOSTANDARD DIFF [get_ports ddr3_dqs_p[1]
|
||||
set_property IOSTANDARD DIFF [get_ports ddr3_dqs_n[1]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[13]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[12]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[11]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[10]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[9]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[8]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[7]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[6]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[5]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[4]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[3]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[2]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[1]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[0]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddr3_ba[2]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddr3_ba[1]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddr3_ba[0]
|
||||
set_property IOSTANDARD DIFF [get_ports ddr3_ck_p[0]
|
||||
set_property IOSTANDARD DIFF [get_ports ddr3_ck_n[0]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddr3_ras_n
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddr3_cas_n
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddr3_we_n
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddr3_reset_n
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddr3_cke[0]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddr3_odt[0]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddr3_cs_n[0]
|
||||
|
||||
|
||||
set_properity PACKAGE_PIN K5 [get_ports ddr3_dq[0]]
|
||||
set_properity PACKAGE_PIN L3 [get_ports ddr3_dq[1]]
|
||||
set_properity PACKAGE_PIN K3 [get_ports ddr3_dq[2]]
|
||||
set_properity PACKAGE_PIN L6 [get_ports ddr3_dq[3]]
|
||||
set_properity PACKAGE_PIN M3 [get_ports ddr3_dq[4]]
|
||||
set_properity PACKAGE_PIN M1 [get_ports ddr3_dq[5]]
|
||||
set_properity PACKAGE_PIN L4 [get_ports ddr3_dq[6]]
|
||||
set_properity PACKAGE_PIN M2 [get_ports ddr3_dq[7]]
|
||||
set_properity PACKAGE_PIN V4 [get_ports ddr3_dq[8]]
|
||||
set_properity PACKAGE_PIN T5 [get_ports ddr3_dq[9]]
|
||||
set_properity PACKAGE_PIN U4 [get_ports ddr3_dq[10]]
|
||||
set_properity PACKAGE_PIN V5 [get_ports ddr3_dq[11]]
|
||||
set_properity PACKAGE_PIN V1 [get_ports ddr3_dq[12]]
|
||||
set_properity PACKAGE_PIN T3 [get_ports ddr3_dq[13]]
|
||||
set_properity PACKAGE_PIN U3 [get_ports ddr3_dq[14]]
|
||||
set_properity PACKAGE_PIN R3 [get_ports ddr3_dq[15]]
|
||||
set_properity PACKAGE_PIN L1 [get_ports ddr3_dm[0]]
|
||||
set_properity PACKAGE_PIN U1 [get_ports ddr3_dm[1]]
|
||||
set_properity PACKAGE_PIN N2 [get_ports ddr3_dqs_p[0]]
|
||||
set_properity PACKAGE_PIN N1 [get_ports ddr3_dqs_n[0]]
|
||||
set_properity PACKAGE_PIN U2 [get_ports ddr3_dqs_p[1]]
|
||||
set_properity PACKAGE_PIN V2 [get_ports ddr3_dqs_n[1]]
|
||||
set_properity PACKAGE_PIN T8 [get_ports ddr3_addr[13]]
|
||||
set_properity PACKAGE_PIN T6 [get_ports ddr3_addr[12]]
|
||||
set_properity PACKAGE_PIN U6 [get_ports ddr3_addr[11]]
|
||||
set_properity PACKAGE_PIN R6 [get_ports ddr3_addr[10]]
|
||||
set_properity PACKAGE_PIN V7 [get_ports ddr3_addr[9]]
|
||||
set_properity PACKAGE_PIN R8 [get_ports ddr3_addr[8]]
|
||||
set_properity PACKAGE_PIN U7 [get_ports ddr3_addr[7]]
|
||||
set_properity PACKAGE_PIN V6 [get_ports ddr3_addr[6]]
|
||||
set_properity PACKAGE_PIN R7 [get_ports ddr3_addr[5]]
|
||||
set_properity PACKAGE_PIN N6 [get_ports ddr3_addr[4]]
|
||||
set_properity PACKAGE_PIN T1 [get_ports ddr3_addr[3]]
|
||||
set_properity PACKAGE_PIN N4 [get_ports ddr3_addr[2]]
|
||||
set_properity PACKAGE_PIN M6 [get_ports ddr3_addr[1]]
|
||||
set_properity PACKAGE_PIN R2 [get_ports ddr3_addr[0]]
|
||||
set_properity PACKAGE_PIN P2 [get_ports ddr3_ba[2]]
|
||||
set_properity PACKAGE_PIN P4 [get_ports ddr3_ba[1]]
|
||||
set_properity PACKAGE_PIN R1 [get_ports ddr3_ba[0]]
|
||||
set_properity PACKAGE_PIN U9 [get_ports ddr3_ck_p[0]]
|
||||
set_properity PACKAGE_PIN V9 [get_ports ddr3_ck_n[0]]
|
||||
set_properity PACKAGE_PIN P3 [get_ports ddr3_ras_n]
|
||||
set_properity PACKAGE_PIN M4 [get_ports ddr3_cas_n]
|
||||
set_properity PACKAGE_PIN P5 [get_ports ddr3_we_n]
|
||||
set_properity PACKAGE_PIN K6 [get_ports ddr3_reset_n]
|
||||
set_properity PACKAGE_PIN N5 [get_ports ddr3_cke[0]]
|
||||
set_properity PACKAGE_PIN R5 [get_ports ddr3_odt[0]]
|
||||
set_properity PACKAGE_PIN U8 [get_ports ddr3_cs_n[0]]
|
||||
|
||||
|
||||
# **** may have to bring this one back
|
||||
#set_max_delay -datapath_only -from [get_pins xlnx_ddr4_c0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/calDone_gated_reg/C] -to [get_pins xlnx_proc_sys_reset_0/U0/EXT_LPF/lpf_int_reg/D] 20.000
|
||||
|
||||
|
||||
set_property CLOCK_DEDICATED_ROUTE ANY_CMT_COLUMN [get_nets wallypipelinedsoc/uncore.uncore/sdc.SDC/clockgater/CLK]
|
||||
@ -1,263 +0,0 @@
|
||||
# The main clocks are all autogenerated by the Xilinx IP
|
||||
# mmcm_clkout1 is the 22Mhz clock from the DDR4 IP used to drive wally and the AHBLite Bus.
|
||||
# mmcm_clkout0 is the clock output of the DDR4 memory interface / 4.
|
||||
# This clock is not used by wally or the AHBLite Bus. However it is used by the AXI BUS on the DD4 IP.
|
||||
|
||||
create_generated_clock -name CLKDiv64_Gen -source [get_pins wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/I0] -multiply_by 1 -divide_by 2 [get_pins wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/O]
|
||||
|
||||
##### GPI ####
|
||||
set_property PACKAGE_PIN E34 [get_ports {GPI[0]}]
|
||||
set_property PACKAGE_PIN M22 [get_ports {GPI[1]}]
|
||||
set_property PACKAGE_PIN AW27 [get_ports {GPI[2]}]
|
||||
set_property PACKAGE_PIN A10 [get_ports {GPI[3]}]
|
||||
set_property IOSTANDARD LVCMOS12 [get_ports {GPI[3]}]
|
||||
set_property IOSTANDARD LVCMOS12 [get_ports {GPI[2]}]
|
||||
set_property IOSTANDARD LVCMOS12 [get_ports {GPI[1]}]
|
||||
set_property IOSTANDARD LVCMOS12 [get_ports {GPI[0]}]
|
||||
set_input_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 2.000 [get_ports {GPI[*]}]
|
||||
set_input_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 2.000 [get_ports {GPI[*]}]
|
||||
set_max_delay -from [get_ports {GPI[*]}] 10.000
|
||||
|
||||
##### GPO ####
|
||||
set_property PACKAGE_PIN AT32 [get_ports {GPO[0]}]
|
||||
set_property PACKAGE_PIN AV34 [get_ports {GPO[1]}]
|
||||
set_property PACKAGE_PIN AY30 [get_ports {GPO[2]}]
|
||||
set_property PACKAGE_PIN BF32 [get_ports {GPO[4]}]
|
||||
set_property PACKAGE_PIN BB32 [get_ports {GPO[3]}]
|
||||
set_property IOSTANDARD LVCMOS12 [get_ports {GPO[4]}]
|
||||
set_property IOSTANDARD LVCMOS12 [get_ports {GPO[3]}]
|
||||
set_property IOSTANDARD LVCMOS12 [get_ports {GPO[2]}]
|
||||
set_property IOSTANDARD LVCMOS12 [get_ports {GPO[1]}]
|
||||
set_property IOSTANDARD LVCMOS12 [get_ports {GPO[0]}]
|
||||
set_max_delay -to [get_ports {GPO[*]}] 10.000
|
||||
set_output_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports {GPO[*]}]
|
||||
set_output_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 0.000 [get_ports {GPO[*]}]
|
||||
|
||||
|
||||
##### UART #####
|
||||
set_property PACKAGE_PIN BC24 [get_ports UARTSin]
|
||||
set_property PACKAGE_PIN BE24 [get_ports UARTSout]
|
||||
set_max_delay -from [get_ports UARTSin] 10.000
|
||||
set_max_delay -to [get_ports UARTSout] 10.000
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports UARTSin]
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports UARTSout]
|
||||
# set_property DRIVE 6 [get_ports UARTSout]
|
||||
set_input_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 2.000 [get_ports UARTSin]
|
||||
set_input_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 2.000 [get_ports UARTSin]
|
||||
set_output_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports UARTSout]
|
||||
set_output_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 0.000 [get_ports UARTSout]
|
||||
|
||||
|
||||
##### reset #####
|
||||
set_input_delay -clock [get_clocks default_250mhz_clk1_0_p] -min -add_delay 2.000 [get_ports reset]
|
||||
set_input_delay -clock [get_clocks default_250mhz_clk1_0_p] -max -add_delay 2.000 [get_ports reset]
|
||||
set_input_delay -clock [get_clocks mmcm_clkout0] -min -add_delay 0.000 [get_ports reset]
|
||||
set_input_delay -clock [get_clocks mmcm_clkout0] -max -add_delay 0.000 [get_ports reset]
|
||||
set_input_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports reset]
|
||||
set_input_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 0.000 [get_ports reset]
|
||||
set_max_delay -from [get_ports reset] 15.000
|
||||
set_false_path -from [get_ports reset]
|
||||
set_property PACKAGE_PIN E34 [get_ports {reset}]
|
||||
set_property IOSTANDARD LVCMOS12 [get_ports {reset}]
|
||||
|
||||
|
||||
|
||||
##### cpu_reset #####
|
||||
set_property PACKAGE_PIN AY35 [get_ports {cpu_reset}]
|
||||
set_property IOSTANDARD LVCMOS12 [get_ports {cpu_reset}]
|
||||
set_output_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports {cpu_reset}]
|
||||
set_output_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 0.000 [get_ports {cpu_reset}]
|
||||
|
||||
|
||||
##### calib #####
|
||||
set_property PACKAGE_PIN BA37 [get_ports calib]
|
||||
set_property IOSTANDARD LVCMOS12 [get_ports calib]
|
||||
set_output_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports calib]
|
||||
set_output_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 20.000 [get_ports calib]
|
||||
set_max_delay -from [get_pins xlnx_ddr4_c0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/calDone_gated_reg/C] -to [get_ports calib] 50.000
|
||||
|
||||
|
||||
##### ahblite_resetn #####
|
||||
set_property PACKAGE_PIN AV36 [get_ports {ahblite_resetn}]
|
||||
set_property IOSTANDARD LVCMOS12 [get_ports {ahblite_resetn}]
|
||||
set_output_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports {ahblite_resetn}]
|
||||
set_output_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 0.000 [get_ports {ahblite_resetn}]
|
||||
|
||||
|
||||
##### south_rst #####
|
||||
set_property PACKAGE_PIN D9 [get_ports south_rst]
|
||||
set_property IOSTANDARD LVCMOS12 [get_ports south_rst]
|
||||
set_input_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 2.000 [get_ports south_rst]
|
||||
set_input_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 2.000 [get_ports south_rst]
|
||||
|
||||
|
||||
##### SD Card I/O #####
|
||||
set_property PACKAGE_PIN BC14 [get_ports {SDCDat[3]}]
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports {SDCDat[3]}]
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports {SDCDat[2]}]
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports {SDCDat[1]}]
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports {SDCDat[0]}]
|
||||
set_property PACKAGE_PIN BF7 [get_ports {SDCDat[2]}]
|
||||
set_property PACKAGE_PIN BC13 [get_ports {SDCDat[1]}]
|
||||
set_property PACKAGE_PIN AW16 [get_ports {SDCDat[0]}]
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports SDCCLK]
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports {SDCCmd}]
|
||||
set_property PACKAGE_PIN BB16 [get_ports SDCCLK]
|
||||
set_property PACKAGE_PIN BA10 [get_ports {SDCCmd}]
|
||||
set_property PULLUP true [get_ports {SDCDat[3]}]
|
||||
set_property PULLUP true [get_ports {SDCDat[2]}]
|
||||
set_property PULLUP true [get_ports {SDCDat[1]}]
|
||||
set_property PULLUP true [get_ports {SDCDat[0]}]
|
||||
set_property PULLUP true [get_ports {SDCCmd}]
|
||||
|
||||
|
||||
set_input_delay -clock [get_clocks CLKDiv64_Gen] -min -add_delay 2.500 [get_ports {SDCDat[*]}]
|
||||
set_input_delay -clock [get_clocks CLKDiv64_Gen] -max -add_delay 21.000 [get_ports {SDCDat[*]}]
|
||||
|
||||
set_input_delay -clock [get_clocks CLKDiv64_Gen] -min -add_delay 2.500 [get_ports {SDCCmd}]
|
||||
set_input_delay -clock [get_clocks CLKDiv64_Gen] -max -add_delay 14.000 [get_ports {SDCCmd}]
|
||||
|
||||
|
||||
set_output_delay -clock [get_clocks CLKDiv64_Gen] -min -add_delay 2.000 [get_ports {SDCCmd}]
|
||||
set_output_delay -clock [get_clocks CLKDiv64_Gen] -max -add_delay 6.000 [get_ports {SDCCmd}]
|
||||
|
||||
set_output_delay -clock [get_clocks CLKDiv64_Gen] 0.000 [get_ports SDCCLK]
|
||||
|
||||
|
||||
|
||||
set_property DCI_CASCADE {64} [get_iobanks 65]
|
||||
set_property INTERNAL_VREF 0.9 [get_iobanks 65]
|
||||
|
||||
|
||||
set_property PACKAGE_PIN E33 [get_ports c0_ddr4_act_n]
|
||||
set_property PACKAGE_PIN C30 [get_ports {c0_ddr4_adr[0]}]
|
||||
set_property PACKAGE_PIN A31 [get_ports {c0_ddr4_adr[10]}]
|
||||
set_property PACKAGE_PIN A33 [get_ports {c0_ddr4_adr[11]}]
|
||||
set_property PACKAGE_PIN F29 [get_ports {c0_ddr4_adr[12]}]
|
||||
set_property PACKAGE_PIN B32 [get_ports {c0_ddr4_adr[13]}]
|
||||
set_property PACKAGE_PIN D29 [get_ports {c0_ddr4_adr[14]}]
|
||||
set_property PACKAGE_PIN B31 [get_ports {c0_ddr4_adr[15]}]
|
||||
set_property PACKAGE_PIN B33 [get_ports {c0_ddr4_adr[16]}]
|
||||
set_property PACKAGE_PIN D32 [get_ports {c0_ddr4_adr[1]}]
|
||||
set_property PACKAGE_PIN B30 [get_ports {c0_ddr4_adr[2]}]
|
||||
set_property PACKAGE_PIN C33 [get_ports {c0_ddr4_adr[3]}]
|
||||
set_property PACKAGE_PIN E32 [get_ports {c0_ddr4_adr[4]}]
|
||||
set_property PACKAGE_PIN A29 [get_ports {c0_ddr4_adr[5]}]
|
||||
set_property PACKAGE_PIN C29 [get_ports {c0_ddr4_adr[6]}]
|
||||
set_property PACKAGE_PIN E29 [get_ports {c0_ddr4_adr[7]}]
|
||||
set_property PACKAGE_PIN A30 [get_ports {c0_ddr4_adr[8]}]
|
||||
set_property PACKAGE_PIN C32 [get_ports {c0_ddr4_adr[9]}]
|
||||
set_property PACKAGE_PIN G30 [get_ports {c0_ddr4_ba[0]}]
|
||||
set_property PACKAGE_PIN F30 [get_ports {c0_ddr4_ba[1]}]
|
||||
set_property PACKAGE_PIN F33 [get_ports {c0_ddr4_bg[0]}]
|
||||
set_property PACKAGE_PIN E31 [get_ports {c0_ddr4_ck_t[0]}]
|
||||
set_property PACKAGE_PIN D31 [get_ports {c0_ddr4_ck_c[0]}]
|
||||
set_property PACKAGE_PIN K29 [get_ports {c0_ddr4_cke[0]}]
|
||||
set_property PACKAGE_PIN D30 [get_ports {c0_ddr4_cs_n[0]}]
|
||||
set_property PACKAGE_PIN J37 [get_ports {c0_ddr4_dq[0]}]
|
||||
set_property PACKAGE_PIN F35 [get_ports {c0_ddr4_dq[10]}]
|
||||
set_property PACKAGE_PIN J35 [get_ports {c0_ddr4_dq[11]}]
|
||||
set_property PACKAGE_PIN G37 [get_ports {c0_ddr4_dq[12]}]
|
||||
set_property PACKAGE_PIN H35 [get_ports {c0_ddr4_dq[13]}]
|
||||
set_property PACKAGE_PIN G36 [get_ports {c0_ddr4_dq[14]}]
|
||||
set_property PACKAGE_PIN H37 [get_ports {c0_ddr4_dq[15]}]
|
||||
set_property PACKAGE_PIN C39 [get_ports {c0_ddr4_dq[16]}]
|
||||
set_property PACKAGE_PIN A38 [get_ports {c0_ddr4_dq[17]}]
|
||||
set_property PACKAGE_PIN B40 [get_ports {c0_ddr4_dq[18]}]
|
||||
set_property PACKAGE_PIN D40 [get_ports {c0_ddr4_dq[19]}]
|
||||
set_property PACKAGE_PIN H40 [get_ports {c0_ddr4_dq[1]}]
|
||||
set_property PACKAGE_PIN E38 [get_ports {c0_ddr4_dq[20]}]
|
||||
set_property PACKAGE_PIN B38 [get_ports {c0_ddr4_dq[21]}]
|
||||
set_property PACKAGE_PIN E37 [get_ports {c0_ddr4_dq[22]}]
|
||||
set_property PACKAGE_PIN C40 [get_ports {c0_ddr4_dq[23]}]
|
||||
set_property PACKAGE_PIN C34 [get_ports {c0_ddr4_dq[24]}]
|
||||
set_property PACKAGE_PIN A34 [get_ports {c0_ddr4_dq[25]}]
|
||||
set_property PACKAGE_PIN D34 [get_ports {c0_ddr4_dq[26]}]
|
||||
set_property PACKAGE_PIN A35 [get_ports {c0_ddr4_dq[27]}]
|
||||
set_property PACKAGE_PIN A36 [get_ports {c0_ddr4_dq[28]}]
|
||||
set_property PACKAGE_PIN C35 [get_ports {c0_ddr4_dq[29]}]
|
||||
set_property PACKAGE_PIN F38 [get_ports {c0_ddr4_dq[2]}]
|
||||
set_property PACKAGE_PIN B35 [get_ports {c0_ddr4_dq[30]}]
|
||||
set_property PACKAGE_PIN D35 [get_ports {c0_ddr4_dq[31]}]
|
||||
set_property PACKAGE_PIN N27 [get_ports {c0_ddr4_dq[32]}]
|
||||
set_property PACKAGE_PIN R27 [get_ports {c0_ddr4_dq[33]}]
|
||||
set_property PACKAGE_PIN N24 [get_ports {c0_ddr4_dq[34]}]
|
||||
set_property PACKAGE_PIN R24 [get_ports {c0_ddr4_dq[35]}]
|
||||
set_property PACKAGE_PIN P24 [get_ports {c0_ddr4_dq[36]}]
|
||||
set_property PACKAGE_PIN P26 [get_ports {c0_ddr4_dq[37]}]
|
||||
set_property PACKAGE_PIN P27 [get_ports {c0_ddr4_dq[38]}]
|
||||
set_property PACKAGE_PIN T24 [get_ports {c0_ddr4_dq[39]}]
|
||||
set_property PACKAGE_PIN H39 [get_ports {c0_ddr4_dq[3]}]
|
||||
set_property PACKAGE_PIN K27 [get_ports {c0_ddr4_dq[40]}]
|
||||
set_property PACKAGE_PIN L26 [get_ports {c0_ddr4_dq[41]}]
|
||||
set_property PACKAGE_PIN J27 [get_ports {c0_ddr4_dq[42]}]
|
||||
set_property PACKAGE_PIN K28 [get_ports {c0_ddr4_dq[43]}]
|
||||
set_property PACKAGE_PIN K26 [get_ports {c0_ddr4_dq[44]}]
|
||||
set_property PACKAGE_PIN M25 [get_ports {c0_ddr4_dq[45]}]
|
||||
set_property PACKAGE_PIN J26 [get_ports {c0_ddr4_dq[46]}]
|
||||
set_property PACKAGE_PIN L28 [get_ports {c0_ddr4_dq[47]}]
|
||||
set_property PACKAGE_PIN E27 [get_ports {c0_ddr4_dq[48]}]
|
||||
set_property PACKAGE_PIN E28 [get_ports {c0_ddr4_dq[49]}]
|
||||
set_property PACKAGE_PIN K37 [get_ports {c0_ddr4_dq[4]}]
|
||||
set_property PACKAGE_PIN E26 [get_ports {c0_ddr4_dq[50]}]
|
||||
set_property PACKAGE_PIN H27 [get_ports {c0_ddr4_dq[51]}]
|
||||
set_property PACKAGE_PIN F25 [get_ports {c0_ddr4_dq[52]}]
|
||||
set_property PACKAGE_PIN F28 [get_ports {c0_ddr4_dq[53]}]
|
||||
set_property PACKAGE_PIN G25 [get_ports {c0_ddr4_dq[54]}]
|
||||
set_property PACKAGE_PIN G27 [get_ports {c0_ddr4_dq[55]}]
|
||||
set_property PACKAGE_PIN B28 [get_ports {c0_ddr4_dq[56]}]
|
||||
set_property PACKAGE_PIN A28 [get_ports {c0_ddr4_dq[57]}]
|
||||
set_property PACKAGE_PIN B25 [get_ports {c0_ddr4_dq[58]}]
|
||||
set_property PACKAGE_PIN B27 [get_ports {c0_ddr4_dq[59]}]
|
||||
set_property PACKAGE_PIN G40 [get_ports {c0_ddr4_dq[5]}]
|
||||
set_property PACKAGE_PIN D25 [get_ports {c0_ddr4_dq[60]}]
|
||||
set_property PACKAGE_PIN C27 [get_ports {c0_ddr4_dq[61]}]
|
||||
set_property PACKAGE_PIN C25 [get_ports {c0_ddr4_dq[62]}]
|
||||
set_property PACKAGE_PIN D26 [get_ports {c0_ddr4_dq[63]}]
|
||||
set_property PACKAGE_PIN F39 [get_ports {c0_ddr4_dq[6]}]
|
||||
set_property PACKAGE_PIN F40 [get_ports {c0_ddr4_dq[7]}]
|
||||
set_property PACKAGE_PIN F36 [get_ports {c0_ddr4_dq[8]}]
|
||||
set_property PACKAGE_PIN J36 [get_ports {c0_ddr4_dq[9]}]
|
||||
set_property PACKAGE_PIN H38 [get_ports {c0_ddr4_dqs_t[0]}]
|
||||
set_property PACKAGE_PIN G38 [get_ports {c0_ddr4_dqs_c[0]}]
|
||||
set_property PACKAGE_PIN H34 [get_ports {c0_ddr4_dqs_t[1]}]
|
||||
set_property PACKAGE_PIN G35 [get_ports {c0_ddr4_dqs_c[1]}]
|
||||
set_property PACKAGE_PIN A39 [get_ports {c0_ddr4_dqs_t[2]}]
|
||||
set_property PACKAGE_PIN A40 [get_ports {c0_ddr4_dqs_c[2]}]
|
||||
set_property PACKAGE_PIN B36 [get_ports {c0_ddr4_dqs_t[3]}]
|
||||
set_property PACKAGE_PIN B37 [get_ports {c0_ddr4_dqs_c[3]}]
|
||||
set_property PACKAGE_PIN P25 [get_ports {c0_ddr4_dqs_t[4]}]
|
||||
set_property PACKAGE_PIN N25 [get_ports {c0_ddr4_dqs_c[4]}]
|
||||
set_property PACKAGE_PIN L24 [get_ports {c0_ddr4_dqs_t[5]}]
|
||||
set_property PACKAGE_PIN L25 [get_ports {c0_ddr4_dqs_c[5]}]
|
||||
set_property PACKAGE_PIN H28 [get_ports {c0_ddr4_dqs_t[6]}]
|
||||
set_property PACKAGE_PIN G28 [get_ports {c0_ddr4_dqs_c[6]}]
|
||||
set_property PACKAGE_PIN B26 [get_ports {c0_ddr4_dqs_t[7]}]
|
||||
set_property PACKAGE_PIN A26 [get_ports {c0_ddr4_dqs_c[7]}]
|
||||
set_property PACKAGE_PIN J31 [get_ports {c0_ddr4_odt[0]}]
|
||||
set_property PACKAGE_PIN M28 [get_ports c0_ddr4_reset_n]
|
||||
|
||||
|
||||
set_property PACKAGE_PIN J39 [get_ports {c0_ddr4_dm_dbi_n[0]}]
|
||||
set_property PACKAGE_PIN F34 [get_ports {c0_ddr4_dm_dbi_n[1]}]
|
||||
set_property PACKAGE_PIN E39 [get_ports {c0_ddr4_dm_dbi_n[2]}]
|
||||
set_property PACKAGE_PIN D37 [get_ports {c0_ddr4_dm_dbi_n[3]}]
|
||||
set_property PACKAGE_PIN T26 [get_ports {c0_ddr4_dm_dbi_n[4]}]
|
||||
set_property PACKAGE_PIN M27 [get_ports {c0_ddr4_dm_dbi_n[5]}]
|
||||
set_property PACKAGE_PIN G26 [get_ports {c0_ddr4_dm_dbi_n[6]}]
|
||||
set_property PACKAGE_PIN D27 [get_ports {c0_ddr4_dm_dbi_n[7]}]
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
set_max_delay -datapath_only -from [get_pins xlnx_ddr4_c0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/calDone_gated_reg/C] -to [get_pins xlnx_proc_sys_reset_0/U0/EXT_LPF/lpf_int_reg/D] 10.000
|
||||
|
||||
|
||||
set_output_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports c0_ddr4_reset_n]
|
||||
set_output_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 20.000 [get_ports c0_ddr4_reset_n]
|
||||
|
||||
|
||||
|
||||
set_max_delay -from [get_pins {xlnx_ddr4_c0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/cal_RESET_n_reg[0]/C}] -to [get_ports c0_ddr4_reset_n] 50.000
|
||||
|
||||
@ -1,266 +0,0 @@
|
||||
# The main clocks are all autogenerated by the Xilinx IP
|
||||
# mmcm_clkout1 is the 22Mhz clock from the DDR4 IP used to drive wally and the AHBLite Bus.
|
||||
# mmcm_clkout0 is the clock output of the DDR4 memory interface / 4.
|
||||
# This clock is not used by wally or the AHBLite Bus. However it is used by the AXI BUS on the DD4 IP.
|
||||
|
||||
create_generated_clock -name CLKDiv64_Gen -source [get_pins wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/I0] -multiply_by 1 -divide_by 2 [get_pins wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/O]
|
||||
|
||||
##### GPI ####
|
||||
set_property PACKAGE_PIN BB24 [get_ports {GPI[0]}]
|
||||
set_property PACKAGE_PIN BF22 [get_ports {GPI[1]}]
|
||||
set_property PACKAGE_PIN BD23 [get_ports {GPI[2]}]
|
||||
set_property PACKAGE_PIN BE23 [get_ports {GPI[3]}]
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports {GPI[3]}]
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports {GPI[2]}]
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports {GPI[1]}]
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports {GPI[0]}]
|
||||
set_input_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 2.000 [get_ports {GPI[*]}]
|
||||
set_input_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 2.000 [get_ports {GPI[*]}]
|
||||
set_max_delay -from [get_ports {GPI[*]}] 10.000
|
||||
|
||||
##### GPO ####
|
||||
set_property PACKAGE_PIN AT32 [get_ports {GPO[0]}]
|
||||
set_property PACKAGE_PIN AV34 [get_ports {GPO[1]}]
|
||||
set_property PACKAGE_PIN AY30 [get_ports {GPO[2]}]
|
||||
set_property PACKAGE_PIN BF32 [get_ports {GPO[4]}]
|
||||
set_property PACKAGE_PIN BB32 [get_ports {GPO[3]}]
|
||||
set_property IOSTANDARD LVCMOS12 [get_ports {GPO[4]}]
|
||||
set_property IOSTANDARD LVCMOS12 [get_ports {GPO[3]}]
|
||||
set_property IOSTANDARD LVCMOS12 [get_ports {GPO[2]}]
|
||||
set_property IOSTANDARD LVCMOS12 [get_ports {GPO[1]}]
|
||||
set_property IOSTANDARD LVCMOS12 [get_ports {GPO[0]}]
|
||||
set_max_delay -to [get_ports {GPO[*]}] 10.000
|
||||
set_output_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports {GPO[*]}]
|
||||
set_output_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 0.000 [get_ports {GPO[*]}]
|
||||
|
||||
|
||||
##### UART #####
|
||||
#set_property PACKAGE_PIN AW25 [get_ports UARTSin]
|
||||
set_property PACKAGE_PIN L31 [get_ports UARTSin]
|
||||
#set_property PACKAGE_PIN BB21 [get_ports UARTSout]
|
||||
set_property PACKAGE_PIN P29 [get_ports UARTSout]
|
||||
set_max_delay -from [get_ports UARTSin] 10.000
|
||||
set_max_delay -to [get_ports UARTSout] 10.000
|
||||
set_property IOSTANDARD LVCMOS12 [get_ports UARTSin]
|
||||
set_property IOSTANDARD LVCMOS12 [get_ports UARTSout]
|
||||
set_property DRIVE 6 [get_ports UARTSout]
|
||||
set_input_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 2.000 [get_ports UARTSin]
|
||||
set_input_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 2.000 [get_ports UARTSin]
|
||||
set_output_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports UARTSout]
|
||||
set_output_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 0.000 [get_ports UARTSout]
|
||||
|
||||
|
||||
##### reset #####
|
||||
set_input_delay -clock [get_clocks default_250mhz_clk1_0_p] -min -add_delay 2.000 [get_ports reset]
|
||||
set_input_delay -clock [get_clocks default_250mhz_clk1_0_p] -max -add_delay 2.000 [get_ports reset]
|
||||
set_input_delay -clock [get_clocks mmcm_clkout0] -min -add_delay 0.000 [get_ports reset]
|
||||
set_input_delay -clock [get_clocks mmcm_clkout0] -max -add_delay 0.000 [get_ports reset]
|
||||
set_input_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports reset]
|
||||
set_input_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 0.000 [get_ports reset]
|
||||
set_max_delay -from [get_ports reset] 15.000
|
||||
set_false_path -from [get_ports reset]
|
||||
set_property PACKAGE_PIN L19 [get_ports {reset}]
|
||||
set_property IOSTANDARD LVCMOS12 [get_ports {reset}]
|
||||
|
||||
|
||||
|
||||
##### cpu_reset #####
|
||||
set_property PACKAGE_PIN AV36 [get_ports {cpu_reset}]
|
||||
set_property IOSTANDARD LVCMOS12 [get_ports {cpu_reset}]
|
||||
set_output_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports {cpu_reset}]
|
||||
set_output_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 0.000 [get_ports {cpu_reset}]
|
||||
|
||||
|
||||
##### calib #####
|
||||
set_property PACKAGE_PIN BA37 [get_ports calib]
|
||||
set_property IOSTANDARD LVCMOS12 [get_ports calib]
|
||||
set_output_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports calib]
|
||||
set_output_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 20.000 [get_ports calib]
|
||||
set_max_delay -from [get_pins xlnx_ddr4_c0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/calDone_gated_reg/C] -to [get_ports calib] 50.000
|
||||
|
||||
|
||||
##### ahblite_resetn #####
|
||||
set_property PACKAGE_PIN AU37 [get_ports {ahblite_resetn}]
|
||||
set_property IOSTANDARD LVCMOS12 [get_ports {ahblite_resetn}]
|
||||
set_output_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports {ahblite_resetn}]
|
||||
set_output_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 0.000 [get_ports {ahblite_resetn}]
|
||||
|
||||
|
||||
##### south_rst #####
|
||||
set_property PACKAGE_PIN BE22 [get_ports south_rst]
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports south_rst]
|
||||
set_input_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 2.000 [get_ports south_rst]
|
||||
set_input_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 2.000 [get_ports south_rst]
|
||||
|
||||
|
||||
##### SD Card I/O #####
|
||||
set_property PACKAGE_PIN AY14 [get_ports {SDCDat[3]}]
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports {SDCDat[3]}]
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports {SDCDat[2]}]
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports {SDCDat[1]}]
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports {SDCDat[0]}]
|
||||
set_property PACKAGE_PIN AU16 [get_ports {SDCDat[2]}]
|
||||
set_property PACKAGE_PIN AV16 [get_ports {SDCDat[1]}]
|
||||
set_property PACKAGE_PIN AW15 [get_ports {SDCDat[0]}]
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports SDCCLK]
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports {SDCCmd}]
|
||||
set_property PACKAGE_PIN AV15 [get_ports SDCCLK]
|
||||
set_property PACKAGE_PIN AY15 [get_ports {SDCCmd}]
|
||||
set_property PULLUP true [get_ports {SDCDat[3]}]
|
||||
set_property PULLUP true [get_ports {SDCDat[2]}]
|
||||
set_property PULLUP true [get_ports {SDCDat[1]}]
|
||||
set_property PULLUP true [get_ports {SDCDat[0]}]
|
||||
set_property PULLUP true [get_ports {SDCCmd}]
|
||||
|
||||
|
||||
set_input_delay -clock [get_clocks CLKDiv64_Gen] -min -add_delay 2.500 [get_ports {SDCDat[*]}]
|
||||
set_input_delay -clock [get_clocks CLKDiv64_Gen] -max -add_delay 21.000 [get_ports {SDCDat[*]}]
|
||||
|
||||
set_input_delay -clock [get_clocks CLKDiv64_Gen] -min -add_delay 2.500 [get_ports {SDCCmd}]
|
||||
set_input_delay -clock [get_clocks CLKDiv64_Gen] -max -add_delay 14.000 [get_ports {SDCCmd}]
|
||||
|
||||
|
||||
set_output_delay -clock [get_clocks CLKDiv64_Gen] -min -add_delay 2.000 [get_ports {SDCCmd}]
|
||||
set_output_delay -clock [get_clocks CLKDiv64_Gen] -max -add_delay 6.000 [get_ports {SDCCmd}]
|
||||
|
||||
set_output_delay -clock [get_clocks CLKDiv64_Gen] 0.000 [get_ports SDCCLK]
|
||||
|
||||
|
||||
|
||||
set_property DCI_CASCADE {64} [get_iobanks 65]
|
||||
set_property INTERNAL_VREF 0.9 [get_iobanks 65]
|
||||
|
||||
|
||||
set_property PACKAGE_PIN E13 [get_ports c0_ddr4_act_n]
|
||||
set_property PACKAGE_PIN D14 [get_ports {c0_ddr4_adr[0]}]
|
||||
set_property PACKAGE_PIN C12 [get_ports {c0_ddr4_adr[10]}]
|
||||
set_property PACKAGE_PIN B13 [get_ports {c0_ddr4_adr[11]}]
|
||||
set_property PACKAGE_PIN C13 [get_ports {c0_ddr4_adr[12]}]
|
||||
set_property PACKAGE_PIN D15 [get_ports {c0_ddr4_adr[13]}]
|
||||
set_property PACKAGE_PIN H14 [get_ports {c0_ddr4_adr[14]}]
|
||||
set_property PACKAGE_PIN H15 [get_ports {c0_ddr4_adr[15]}]
|
||||
set_property PACKAGE_PIN F15 [get_ports {c0_ddr4_adr[16]}]
|
||||
set_property PACKAGE_PIN B15 [get_ports {c0_ddr4_adr[1]}]
|
||||
set_property PACKAGE_PIN B16 [get_ports {c0_ddr4_adr[2]}]
|
||||
set_property PACKAGE_PIN C14 [get_ports {c0_ddr4_adr[3]}]
|
||||
set_property PACKAGE_PIN C15 [get_ports {c0_ddr4_adr[4]}]
|
||||
set_property PACKAGE_PIN A13 [get_ports {c0_ddr4_adr[5]}]
|
||||
set_property PACKAGE_PIN A14 [get_ports {c0_ddr4_adr[6]}]
|
||||
set_property PACKAGE_PIN A15 [get_ports {c0_ddr4_adr[7]}]
|
||||
set_property PACKAGE_PIN A16 [get_ports {c0_ddr4_adr[8]}]
|
||||
set_property PACKAGE_PIN B12 [get_ports {c0_ddr4_adr[9]}]
|
||||
set_property PACKAGE_PIN G15 [get_ports {c0_ddr4_ba[0]}]
|
||||
set_property PACKAGE_PIN G13 [get_ports {c0_ddr4_ba[1]}]
|
||||
set_property PACKAGE_PIN H13 [get_ports {c0_ddr4_bg[0]}]
|
||||
set_property PACKAGE_PIN F14 [get_ports {c0_ddr4_ck_t[0]}]
|
||||
set_property PACKAGE_PIN E14 [get_ports {c0_ddr4_ck_c[0]}]
|
||||
set_property PACKAGE_PIN A10 [get_ports {c0_ddr4_cke[0]}]
|
||||
set_property PACKAGE_PIN F13 [get_ports {c0_ddr4_cs_n[0]}]
|
||||
set_property PACKAGE_PIN F11 [get_ports {c0_ddr4_dq[0]}]
|
||||
set_property PACKAGE_PIN M18 [get_ports {c0_ddr4_dq[10]}]
|
||||
set_property PACKAGE_PIN M17 [get_ports {c0_ddr4_dq[11]}]
|
||||
set_property PACKAGE_PIN N19 [get_ports {c0_ddr4_dq[12]}]
|
||||
set_property PACKAGE_PIN N18 [get_ports {c0_ddr4_dq[13]}]
|
||||
set_property PACKAGE_PIN N17 [get_ports {c0_ddr4_dq[14]}]
|
||||
set_property PACKAGE_PIN M16 [get_ports {c0_ddr4_dq[15]}]
|
||||
set_property PACKAGE_PIN L16 [get_ports {c0_ddr4_dq[16]}]
|
||||
set_property PACKAGE_PIN K16 [get_ports {c0_ddr4_dq[17]}]
|
||||
set_property PACKAGE_PIN L18 [get_ports {c0_ddr4_dq[18]}]
|
||||
set_property PACKAGE_PIN K18 [get_ports {c0_ddr4_dq[19]}]
|
||||
set_property PACKAGE_PIN E11 [get_ports {c0_ddr4_dq[1]}]
|
||||
set_property PACKAGE_PIN J17 [get_ports {c0_ddr4_dq[20]}]
|
||||
set_property PACKAGE_PIN H17 [get_ports {c0_ddr4_dq[21]}]
|
||||
set_property PACKAGE_PIN H19 [get_ports {c0_ddr4_dq[22]}]
|
||||
set_property PACKAGE_PIN H18 [get_ports {c0_ddr4_dq[23]}]
|
||||
set_property PACKAGE_PIN F19 [get_ports {c0_ddr4_dq[24]}]
|
||||
set_property PACKAGE_PIN F18 [get_ports {c0_ddr4_dq[25]}]
|
||||
set_property PACKAGE_PIN E19 [get_ports {c0_ddr4_dq[26]}]
|
||||
set_property PACKAGE_PIN E18 [get_ports {c0_ddr4_dq[27]}]
|
||||
set_property PACKAGE_PIN G20 [get_ports {c0_ddr4_dq[28]}]
|
||||
set_property PACKAGE_PIN F20 [get_ports {c0_ddr4_dq[29]}]
|
||||
set_property PACKAGE_PIN F10 [get_ports {c0_ddr4_dq[2]}]
|
||||
set_property PACKAGE_PIN E17 [get_ports {c0_ddr4_dq[30]}]
|
||||
set_property PACKAGE_PIN D16 [get_ports {c0_ddr4_dq[31]}]
|
||||
set_property PACKAGE_PIN D17 [get_ports {c0_ddr4_dq[32]}]
|
||||
set_property PACKAGE_PIN C17 [get_ports {c0_ddr4_dq[33]}]
|
||||
set_property PACKAGE_PIN C19 [get_ports {c0_ddr4_dq[34]}]
|
||||
set_property PACKAGE_PIN C18 [get_ports {c0_ddr4_dq[35]}]
|
||||
set_property PACKAGE_PIN D20 [get_ports {c0_ddr4_dq[36]}]
|
||||
set_property PACKAGE_PIN D19 [get_ports {c0_ddr4_dq[37]}]
|
||||
set_property PACKAGE_PIN C20 [get_ports {c0_ddr4_dq[38]}]
|
||||
set_property PACKAGE_PIN B20 [get_ports {c0_ddr4_dq[39]}]
|
||||
set_property PACKAGE_PIN F9 [get_ports {c0_ddr4_dq[3]}]
|
||||
set_property PACKAGE_PIN N23 [get_ports {c0_ddr4_dq[40]}]
|
||||
set_property PACKAGE_PIN M23 [get_ports {c0_ddr4_dq[41]}]
|
||||
set_property PACKAGE_PIN R21 [get_ports {c0_ddr4_dq[42]}]
|
||||
set_property PACKAGE_PIN P21 [get_ports {c0_ddr4_dq[43]}]
|
||||
set_property PACKAGE_PIN R22 [get_ports {c0_ddr4_dq[44]}]
|
||||
set_property PACKAGE_PIN P22 [get_ports {c0_ddr4_dq[45]}]
|
||||
set_property PACKAGE_PIN T23 [get_ports {c0_ddr4_dq[46]}]
|
||||
set_property PACKAGE_PIN R23 [get_ports {c0_ddr4_dq[47]}]
|
||||
set_property PACKAGE_PIN K24 [get_ports {c0_ddr4_dq[48]}]
|
||||
set_property PACKAGE_PIN J24 [get_ports {c0_ddr4_dq[49]}]
|
||||
set_property PACKAGE_PIN H12 [get_ports {c0_ddr4_dq[4]}]
|
||||
set_property PACKAGE_PIN M21 [get_ports {c0_ddr4_dq[50]}]
|
||||
set_property PACKAGE_PIN L21 [get_ports {c0_ddr4_dq[51]}]
|
||||
set_property PACKAGE_PIN K21 [get_ports {c0_ddr4_dq[52]}]
|
||||
set_property PACKAGE_PIN J21 [get_ports {c0_ddr4_dq[53]}]
|
||||
set_property PACKAGE_PIN K22 [get_ports {c0_ddr4_dq[54]}]
|
||||
set_property PACKAGE_PIN J22 [get_ports {c0_ddr4_dq[55]}]
|
||||
set_property PACKAGE_PIN H23 [get_ports {c0_ddr4_dq[56]}]
|
||||
set_property PACKAGE_PIN H22 [get_ports {c0_ddr4_dq[57]}]
|
||||
set_property PACKAGE_PIN E23 [get_ports {c0_ddr4_dq[58]}]
|
||||
set_property PACKAGE_PIN E22 [get_ports {c0_ddr4_dq[59]}]
|
||||
set_property PACKAGE_PIN G12 [get_ports {c0_ddr4_dq[5]}]
|
||||
set_property PACKAGE_PIN F21 [get_ports {c0_ddr4_dq[60]}]
|
||||
set_property PACKAGE_PIN E21 [get_ports {c0_ddr4_dq[61]}]
|
||||
set_property PACKAGE_PIN F24 [get_ports {c0_ddr4_dq[62]}]
|
||||
set_property PACKAGE_PIN F23 [get_ports {c0_ddr4_dq[63]}]
|
||||
set_property PACKAGE_PIN E9 [get_ports {c0_ddr4_dq[6]}]
|
||||
set_property PACKAGE_PIN D9 [get_ports {c0_ddr4_dq[7]}]
|
||||
set_property PACKAGE_PIN R19 [get_ports {c0_ddr4_dq[8]}]
|
||||
set_property PACKAGE_PIN P19 [get_ports {c0_ddr4_dq[9]}]
|
||||
set_property PACKAGE_PIN D11 [get_ports {c0_ddr4_dqs_t[0]}]
|
||||
set_property PACKAGE_PIN D10 [get_ports {c0_ddr4_dqs_c[0]}]
|
||||
set_property PACKAGE_PIN P17 [get_ports {c0_ddr4_dqs_t[1]}]
|
||||
set_property PACKAGE_PIN P16 [get_ports {c0_ddr4_dqs_c[1]}]
|
||||
set_property PACKAGE_PIN K19 [get_ports {c0_ddr4_dqs_t[2]}]
|
||||
set_property PACKAGE_PIN J19 [get_ports {c0_ddr4_dqs_c[2]}]
|
||||
set_property PACKAGE_PIN F16 [get_ports {c0_ddr4_dqs_t[3]}]
|
||||
set_property PACKAGE_PIN E16 [get_ports {c0_ddr4_dqs_c[3]}]
|
||||
set_property PACKAGE_PIN A19 [get_ports {c0_ddr4_dqs_t[4]}]
|
||||
set_property PACKAGE_PIN A18 [get_ports {c0_ddr4_dqs_c[4]}]
|
||||
set_property PACKAGE_PIN N22 [get_ports {c0_ddr4_dqs_t[5]}]
|
||||
set_property PACKAGE_PIN M22 [get_ports {c0_ddr4_dqs_c[5]}]
|
||||
set_property PACKAGE_PIN M20 [get_ports {c0_ddr4_dqs_t[6]}]
|
||||
set_property PACKAGE_PIN L20 [get_ports {c0_ddr4_dqs_c[6]}]
|
||||
set_property PACKAGE_PIN H24 [get_ports {c0_ddr4_dqs_t[7]}]
|
||||
set_property PACKAGE_PIN G23 [get_ports {c0_ddr4_dqs_c[7]}]
|
||||
set_property PACKAGE_PIN C8 [get_ports {c0_ddr4_odt[0]}]
|
||||
set_property PACKAGE_PIN N20 [get_ports c0_ddr4_reset_n]
|
||||
|
||||
|
||||
set_property PACKAGE_PIN G11 [get_ports {c0_ddr4_dm_dbi_n[0]}]
|
||||
set_property PACKAGE_PIN R18 [get_ports {c0_ddr4_dm_dbi_n[1]}]
|
||||
set_property PACKAGE_PIN K17 [get_ports {c0_ddr4_dm_dbi_n[2]}]
|
||||
set_property PACKAGE_PIN G18 [get_ports {c0_ddr4_dm_dbi_n[3]}]
|
||||
set_property PACKAGE_PIN B18 [get_ports {c0_ddr4_dm_dbi_n[4]}]
|
||||
set_property PACKAGE_PIN P20 [get_ports {c0_ddr4_dm_dbi_n[5]}]
|
||||
set_property PACKAGE_PIN L23 [get_ports {c0_ddr4_dm_dbi_n[6]}]
|
||||
set_property PACKAGE_PIN G22 [get_ports {c0_ddr4_dm_dbi_n[7]}]
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
set_max_delay -datapath_only -from [get_pins xlnx_ddr4_c0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/calDone_gated_reg/C] -to [get_pins xlnx_proc_sys_reset_0/U0/EXT_LPF/lpf_int_reg/D] 10.000
|
||||
|
||||
|
||||
set_output_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports c0_ddr4_reset_n]
|
||||
set_output_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 20.000 [get_ports c0_ddr4_reset_n]
|
||||
|
||||
|
||||
|
||||
set_max_delay -from [get_pins {xlnx_ddr4_c0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/cal_RESET_n_reg[0]/C}] -to [get_ports c0_ddr4_reset_n] 50.000
|
||||
|
||||
|
||||
264
fpga/constraints/constraints.xdc
Normal file
264
fpga/constraints/constraints.xdc
Normal file
@ -0,0 +1,264 @@
|
||||
# The main clocks are all autogenerated by the Xilinx IP
|
||||
# mmcm_clkout1 is the 22Mhz clock from the DDR4 IP used to drive wally and the AHBLite Bus.
|
||||
# mmcm_clkout0 is the clock output of the DDR4 memory interface / 4.
|
||||
# This clock is not used by wally or the AHBLite Bus. However it is used by the AXI BUS on the DD4 IP.
|
||||
|
||||
create_generated_clock -name CLKDiv64_Gen -source [get_pins wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/I0] -multiply_by 1 -divide_by 2 [get_pins wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/O]
|
||||
|
||||
##### GPI ####
|
||||
set_property PACKAGE_PIN BB24 [get_ports {GPI[0]}]
|
||||
set_property PACKAGE_PIN BF22 [get_ports {GPI[1]}]
|
||||
set_property PACKAGE_PIN BD23 [get_ports {GPI[2]}]
|
||||
set_property PACKAGE_PIN BE23 [get_ports {GPI[3]}]
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports {GPI[3]}]
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports {GPI[2]}]
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports {GPI[1]}]
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports {GPI[0]}]
|
||||
set_input_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 2.000 [get_ports {GPI[*]}]
|
||||
set_input_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 2.000 [get_ports {GPI[*]}]
|
||||
set_max_delay -from [get_ports {GPI[*]}] 10.000
|
||||
|
||||
##### GPO ####
|
||||
set_property PACKAGE_PIN AT32 [get_ports {GPO[0]}]
|
||||
set_property PACKAGE_PIN AV34 [get_ports {GPO[1]}]
|
||||
set_property PACKAGE_PIN AY30 [get_ports {GPO[2]}]
|
||||
set_property PACKAGE_PIN BF32 [get_ports {GPO[4]}]
|
||||
set_property PACKAGE_PIN BB32 [get_ports {GPO[3]}]
|
||||
set_property IOSTANDARD LVCMOS12 [get_ports {GPO[4]}]
|
||||
set_property IOSTANDARD LVCMOS12 [get_ports {GPO[3]}]
|
||||
set_property IOSTANDARD LVCMOS12 [get_ports {GPO[2]}]
|
||||
set_property IOSTANDARD LVCMOS12 [get_ports {GPO[1]}]
|
||||
set_property IOSTANDARD LVCMOS12 [get_ports {GPO[0]}]
|
||||
set_max_delay -to [get_ports {GPO[*]}] 10.000
|
||||
set_output_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports {GPO[*]}]
|
||||
set_output_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 0.000 [get_ports {GPO[*]}]
|
||||
|
||||
|
||||
##### UART #####
|
||||
set_property PACKAGE_PIN AW25 [get_ports UARTSin]
|
||||
set_property PACKAGE_PIN BB21 [get_ports UARTSout]
|
||||
set_max_delay -from [get_ports UARTSin] 10.000
|
||||
set_max_delay -to [get_ports UARTSout] 10.000
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports UARTSin]
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports UARTSout]
|
||||
set_property DRIVE 6 [get_ports UARTSout]
|
||||
set_input_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 2.000 [get_ports UARTSin]
|
||||
set_input_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 2.000 [get_ports UARTSin]
|
||||
set_output_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports UARTSout]
|
||||
set_output_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 0.000 [get_ports UARTSout]
|
||||
|
||||
|
||||
##### reset #####
|
||||
set_input_delay -clock [get_clocks default_250mhz_clk1_0_p] -min -add_delay 2.000 [get_ports reset]
|
||||
set_input_delay -clock [get_clocks default_250mhz_clk1_0_p] -max -add_delay 2.000 [get_ports reset]
|
||||
set_input_delay -clock [get_clocks mmcm_clkout0] -min -add_delay 0.000 [get_ports reset]
|
||||
set_input_delay -clock [get_clocks mmcm_clkout0] -max -add_delay 0.000 [get_ports reset]
|
||||
set_input_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports reset]
|
||||
set_input_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 0.000 [get_ports reset]
|
||||
set_max_delay -from [get_ports reset] 15.000
|
||||
set_false_path -from [get_ports reset]
|
||||
set_property PACKAGE_PIN L19 [get_ports {reset}]
|
||||
set_property IOSTANDARD LVCMOS12 [get_ports {reset}]
|
||||
|
||||
|
||||
|
||||
##### cpu_reset #####
|
||||
set_property PACKAGE_PIN AV36 [get_ports {cpu_reset}]
|
||||
set_property IOSTANDARD LVCMOS12 [get_ports {cpu_reset}]
|
||||
set_output_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports {cpu_reset}]
|
||||
set_output_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 0.000 [get_ports {cpu_reset}]
|
||||
|
||||
|
||||
##### calib #####
|
||||
set_property PACKAGE_PIN BA37 [get_ports calib]
|
||||
set_property IOSTANDARD LVCMOS12 [get_ports calib]
|
||||
set_output_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports calib]
|
||||
set_output_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 20.000 [get_ports calib]
|
||||
set_max_delay -from [get_pins xlnx_ddr4_c0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/calDone_gated_reg/C] -to [get_ports calib] 50.000
|
||||
|
||||
|
||||
##### ahblite_resetn #####
|
||||
set_property PACKAGE_PIN AU37 [get_ports {ahblite_resetn}]
|
||||
set_property IOSTANDARD LVCMOS12 [get_ports {ahblite_resetn}]
|
||||
set_output_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports {ahblite_resetn}]
|
||||
set_output_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 0.000 [get_ports {ahblite_resetn}]
|
||||
|
||||
|
||||
##### south_rst #####
|
||||
set_property PACKAGE_PIN BE22 [get_ports south_rst]
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports south_rst]
|
||||
set_input_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 2.000 [get_ports south_rst]
|
||||
set_input_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 2.000 [get_ports south_rst]
|
||||
|
||||
|
||||
##### SD Card I/O #####
|
||||
set_property PACKAGE_PIN AY14 [get_ports {SDCDat[3]}]
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports {SDCDat[3]}]
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports {SDCDat[2]}]
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports {SDCDat[1]}]
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports {SDCDat[0]}]
|
||||
set_property PACKAGE_PIN AU16 [get_ports {SDCDat[2]}]
|
||||
set_property PACKAGE_PIN AV16 [get_ports {SDCDat[1]}]
|
||||
set_property PACKAGE_PIN AW15 [get_ports {SDCDat[0]}]
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports SDCCLK]
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports {SDCCmd}]
|
||||
set_property PACKAGE_PIN AV15 [get_ports SDCCLK]
|
||||
set_property PACKAGE_PIN AY15 [get_ports {SDCCmd}]
|
||||
set_property PULLUP true [get_ports {SDCDat[3]}]
|
||||
set_property PULLUP true [get_ports {SDCDat[2]}]
|
||||
set_property PULLUP true [get_ports {SDCDat[1]}]
|
||||
set_property PULLUP true [get_ports {SDCDat[0]}]
|
||||
set_property PULLUP true [get_ports {SDCCmd}]
|
||||
|
||||
|
||||
set_input_delay -clock [get_clocks CLKDiv64_Gen] -min -add_delay 2.500 [get_ports {SDCDat[*]}]
|
||||
set_input_delay -clock [get_clocks CLKDiv64_Gen] -max -add_delay 21.000 [get_ports {SDCDat[*]}]
|
||||
|
||||
set_input_delay -clock [get_clocks CLKDiv64_Gen] -min -add_delay 2.500 [get_ports {SDCCmd}]
|
||||
set_input_delay -clock [get_clocks CLKDiv64_Gen] -max -add_delay 14.000 [get_ports {SDCCmd}]
|
||||
|
||||
|
||||
set_output_delay -clock [get_clocks CLKDiv64_Gen] -min -add_delay 2.000 [get_ports {SDCCmd}]
|
||||
set_output_delay -clock [get_clocks CLKDiv64_Gen] -max -add_delay 6.000 [get_ports {SDCCmd}]
|
||||
|
||||
set_output_delay -clock [get_clocks CLKDiv64_Gen] 0.000 [get_ports SDCCLK]
|
||||
|
||||
|
||||
|
||||
set_property DCI_CASCADE {64} [get_iobanks 65]
|
||||
set_property INTERNAL_VREF 0.9 [get_iobanks 65]
|
||||
|
||||
|
||||
set_property PACKAGE_PIN E13 [get_ports c0_ddr4_act_n]
|
||||
set_property PACKAGE_PIN D14 [get_ports {c0_ddr4_adr[0]}]
|
||||
set_property PACKAGE_PIN C12 [get_ports {c0_ddr4_adr[10]}]
|
||||
set_property PACKAGE_PIN B13 [get_ports {c0_ddr4_adr[11]}]
|
||||
set_property PACKAGE_PIN C13 [get_ports {c0_ddr4_adr[12]}]
|
||||
set_property PACKAGE_PIN D15 [get_ports {c0_ddr4_adr[13]}]
|
||||
set_property PACKAGE_PIN H14 [get_ports {c0_ddr4_adr[14]}]
|
||||
set_property PACKAGE_PIN H15 [get_ports {c0_ddr4_adr[15]}]
|
||||
set_property PACKAGE_PIN F15 [get_ports {c0_ddr4_adr[16]}]
|
||||
set_property PACKAGE_PIN B15 [get_ports {c0_ddr4_adr[1]}]
|
||||
set_property PACKAGE_PIN B16 [get_ports {c0_ddr4_adr[2]}]
|
||||
set_property PACKAGE_PIN C14 [get_ports {c0_ddr4_adr[3]}]
|
||||
set_property PACKAGE_PIN C15 [get_ports {c0_ddr4_adr[4]}]
|
||||
set_property PACKAGE_PIN A13 [get_ports {c0_ddr4_adr[5]}]
|
||||
set_property PACKAGE_PIN A14 [get_ports {c0_ddr4_adr[6]}]
|
||||
set_property PACKAGE_PIN A15 [get_ports {c0_ddr4_adr[7]}]
|
||||
set_property PACKAGE_PIN A16 [get_ports {c0_ddr4_adr[8]}]
|
||||
set_property PACKAGE_PIN B12 [get_ports {c0_ddr4_adr[9]}]
|
||||
set_property PACKAGE_PIN G15 [get_ports {c0_ddr4_ba[0]}]
|
||||
set_property PACKAGE_PIN G13 [get_ports {c0_ddr4_ba[1]}]
|
||||
set_property PACKAGE_PIN H13 [get_ports {c0_ddr4_bg[0]}]
|
||||
set_property PACKAGE_PIN F14 [get_ports {c0_ddr4_ck_t[0]}]
|
||||
set_property PACKAGE_PIN E14 [get_ports {c0_ddr4_ck_c[0]}]
|
||||
set_property PACKAGE_PIN A10 [get_ports {c0_ddr4_cke[0]}]
|
||||
set_property PACKAGE_PIN F13 [get_ports {c0_ddr4_cs_n[0]}]
|
||||
set_property PACKAGE_PIN F11 [get_ports {c0_ddr4_dq[0]}]
|
||||
set_property PACKAGE_PIN M18 [get_ports {c0_ddr4_dq[10]}]
|
||||
set_property PACKAGE_PIN M17 [get_ports {c0_ddr4_dq[11]}]
|
||||
set_property PACKAGE_PIN N19 [get_ports {c0_ddr4_dq[12]}]
|
||||
set_property PACKAGE_PIN N18 [get_ports {c0_ddr4_dq[13]}]
|
||||
set_property PACKAGE_PIN N17 [get_ports {c0_ddr4_dq[14]}]
|
||||
set_property PACKAGE_PIN M16 [get_ports {c0_ddr4_dq[15]}]
|
||||
set_property PACKAGE_PIN L16 [get_ports {c0_ddr4_dq[16]}]
|
||||
set_property PACKAGE_PIN K16 [get_ports {c0_ddr4_dq[17]}]
|
||||
set_property PACKAGE_PIN L18 [get_ports {c0_ddr4_dq[18]}]
|
||||
set_property PACKAGE_PIN K18 [get_ports {c0_ddr4_dq[19]}]
|
||||
set_property PACKAGE_PIN E11 [get_ports {c0_ddr4_dq[1]}]
|
||||
set_property PACKAGE_PIN J17 [get_ports {c0_ddr4_dq[20]}]
|
||||
set_property PACKAGE_PIN H17 [get_ports {c0_ddr4_dq[21]}]
|
||||
set_property PACKAGE_PIN H19 [get_ports {c0_ddr4_dq[22]}]
|
||||
set_property PACKAGE_PIN H18 [get_ports {c0_ddr4_dq[23]}]
|
||||
set_property PACKAGE_PIN F19 [get_ports {c0_ddr4_dq[24]}]
|
||||
set_property PACKAGE_PIN F18 [get_ports {c0_ddr4_dq[25]}]
|
||||
set_property PACKAGE_PIN E19 [get_ports {c0_ddr4_dq[26]}]
|
||||
set_property PACKAGE_PIN E18 [get_ports {c0_ddr4_dq[27]}]
|
||||
set_property PACKAGE_PIN G20 [get_ports {c0_ddr4_dq[28]}]
|
||||
set_property PACKAGE_PIN F20 [get_ports {c0_ddr4_dq[29]}]
|
||||
set_property PACKAGE_PIN F10 [get_ports {c0_ddr4_dq[2]}]
|
||||
set_property PACKAGE_PIN E17 [get_ports {c0_ddr4_dq[30]}]
|
||||
set_property PACKAGE_PIN D16 [get_ports {c0_ddr4_dq[31]}]
|
||||
set_property PACKAGE_PIN D17 [get_ports {c0_ddr4_dq[32]}]
|
||||
set_property PACKAGE_PIN C17 [get_ports {c0_ddr4_dq[33]}]
|
||||
set_property PACKAGE_PIN C19 [get_ports {c0_ddr4_dq[34]}]
|
||||
set_property PACKAGE_PIN C18 [get_ports {c0_ddr4_dq[35]}]
|
||||
set_property PACKAGE_PIN D20 [get_ports {c0_ddr4_dq[36]}]
|
||||
set_property PACKAGE_PIN D19 [get_ports {c0_ddr4_dq[37]}]
|
||||
set_property PACKAGE_PIN C20 [get_ports {c0_ddr4_dq[38]}]
|
||||
set_property PACKAGE_PIN B20 [get_ports {c0_ddr4_dq[39]}]
|
||||
set_property PACKAGE_PIN F9 [get_ports {c0_ddr4_dq[3]}]
|
||||
set_property PACKAGE_PIN N23 [get_ports {c0_ddr4_dq[40]}]
|
||||
set_property PACKAGE_PIN M23 [get_ports {c0_ddr4_dq[41]}]
|
||||
set_property PACKAGE_PIN R21 [get_ports {c0_ddr4_dq[42]}]
|
||||
set_property PACKAGE_PIN P21 [get_ports {c0_ddr4_dq[43]}]
|
||||
set_property PACKAGE_PIN R22 [get_ports {c0_ddr4_dq[44]}]
|
||||
set_property PACKAGE_PIN P22 [get_ports {c0_ddr4_dq[45]}]
|
||||
set_property PACKAGE_PIN T23 [get_ports {c0_ddr4_dq[46]}]
|
||||
set_property PACKAGE_PIN R23 [get_ports {c0_ddr4_dq[47]}]
|
||||
set_property PACKAGE_PIN K24 [get_ports {c0_ddr4_dq[48]}]
|
||||
set_property PACKAGE_PIN J24 [get_ports {c0_ddr4_dq[49]}]
|
||||
set_property PACKAGE_PIN H12 [get_ports {c0_ddr4_dq[4]}]
|
||||
set_property PACKAGE_PIN M21 [get_ports {c0_ddr4_dq[50]}]
|
||||
set_property PACKAGE_PIN L21 [get_ports {c0_ddr4_dq[51]}]
|
||||
set_property PACKAGE_PIN K21 [get_ports {c0_ddr4_dq[52]}]
|
||||
set_property PACKAGE_PIN J21 [get_ports {c0_ddr4_dq[53]}]
|
||||
set_property PACKAGE_PIN K22 [get_ports {c0_ddr4_dq[54]}]
|
||||
set_property PACKAGE_PIN J22 [get_ports {c0_ddr4_dq[55]}]
|
||||
set_property PACKAGE_PIN H23 [get_ports {c0_ddr4_dq[56]}]
|
||||
set_property PACKAGE_PIN H22 [get_ports {c0_ddr4_dq[57]}]
|
||||
set_property PACKAGE_PIN E23 [get_ports {c0_ddr4_dq[58]}]
|
||||
set_property PACKAGE_PIN E22 [get_ports {c0_ddr4_dq[59]}]
|
||||
set_property PACKAGE_PIN G12 [get_ports {c0_ddr4_dq[5]}]
|
||||
set_property PACKAGE_PIN F21 [get_ports {c0_ddr4_dq[60]}]
|
||||
set_property PACKAGE_PIN E21 [get_ports {c0_ddr4_dq[61]}]
|
||||
set_property PACKAGE_PIN F24 [get_ports {c0_ddr4_dq[62]}]
|
||||
set_property PACKAGE_PIN F23 [get_ports {c0_ddr4_dq[63]}]
|
||||
set_property PACKAGE_PIN E9 [get_ports {c0_ddr4_dq[6]}]
|
||||
set_property PACKAGE_PIN D9 [get_ports {c0_ddr4_dq[7]}]
|
||||
set_property PACKAGE_PIN R19 [get_ports {c0_ddr4_dq[8]}]
|
||||
set_property PACKAGE_PIN P19 [get_ports {c0_ddr4_dq[9]}]
|
||||
set_property PACKAGE_PIN D11 [get_ports {c0_ddr4_dqs_t[0]}]
|
||||
set_property PACKAGE_PIN D10 [get_ports {c0_ddr4_dqs_c[0]}]
|
||||
set_property PACKAGE_PIN P17 [get_ports {c0_ddr4_dqs_t[1]}]
|
||||
set_property PACKAGE_PIN P16 [get_ports {c0_ddr4_dqs_c[1]}]
|
||||
set_property PACKAGE_PIN K19 [get_ports {c0_ddr4_dqs_t[2]}]
|
||||
set_property PACKAGE_PIN J19 [get_ports {c0_ddr4_dqs_c[2]}]
|
||||
set_property PACKAGE_PIN F16 [get_ports {c0_ddr4_dqs_t[3]}]
|
||||
set_property PACKAGE_PIN E16 [get_ports {c0_ddr4_dqs_c[3]}]
|
||||
set_property PACKAGE_PIN A19 [get_ports {c0_ddr4_dqs_t[4]}]
|
||||
set_property PACKAGE_PIN A18 [get_ports {c0_ddr4_dqs_c[4]}]
|
||||
set_property PACKAGE_PIN N22 [get_ports {c0_ddr4_dqs_t[5]}]
|
||||
set_property PACKAGE_PIN M22 [get_ports {c0_ddr4_dqs_c[5]}]
|
||||
set_property PACKAGE_PIN M20 [get_ports {c0_ddr4_dqs_t[6]}]
|
||||
set_property PACKAGE_PIN L20 [get_ports {c0_ddr4_dqs_c[6]}]
|
||||
set_property PACKAGE_PIN H24 [get_ports {c0_ddr4_dqs_t[7]}]
|
||||
set_property PACKAGE_PIN G23 [get_ports {c0_ddr4_dqs_c[7]}]
|
||||
set_property PACKAGE_PIN C8 [get_ports {c0_ddr4_odt[0]}]
|
||||
set_property PACKAGE_PIN N20 [get_ports c0_ddr4_reset_n]
|
||||
|
||||
|
||||
set_property PACKAGE_PIN G11 [get_ports {c0_ddr4_dm_dbi_n[0]}]
|
||||
set_property PACKAGE_PIN R18 [get_ports {c0_ddr4_dm_dbi_n[1]}]
|
||||
set_property PACKAGE_PIN K17 [get_ports {c0_ddr4_dm_dbi_n[2]}]
|
||||
set_property PACKAGE_PIN G18 [get_ports {c0_ddr4_dm_dbi_n[3]}]
|
||||
set_property PACKAGE_PIN B18 [get_ports {c0_ddr4_dm_dbi_n[4]}]
|
||||
set_property PACKAGE_PIN P20 [get_ports {c0_ddr4_dm_dbi_n[5]}]
|
||||
set_property PACKAGE_PIN L23 [get_ports {c0_ddr4_dm_dbi_n[6]}]
|
||||
set_property PACKAGE_PIN G22 [get_ports {c0_ddr4_dm_dbi_n[7]}]
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
set_max_delay -datapath_only -from [get_pins xlnx_ddr4_c0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/calDone_gated_reg/C] -to [get_pins xlnx_proc_sys_reset_0/U0/EXT_LPF/lpf_int_reg/D] 10.000
|
||||
|
||||
|
||||
set_output_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports c0_ddr4_reset_n]
|
||||
set_output_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 20.000 [get_ports c0_ddr4_reset_n]
|
||||
|
||||
|
||||
|
||||
set_max_delay -from [get_pins {xlnx_ddr4_c0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/cal_RESET_n_reg[0]/C}] -to [get_ports c0_ddr4_reset_n] 50.000
|
||||
|
||||
|
||||
File diff suppressed because one or more lines are too long
@ -1,894 +0,0 @@
|
||||
create_debug_core u_ila_0 ila
|
||||
|
||||
set_property C_DATA_DEPTH 16384 [get_debug_cores u_ila_0]
|
||||
set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
|
||||
set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
|
||||
set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
|
||||
set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
|
||||
set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
|
||||
set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
|
||||
set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
|
||||
startgroup
|
||||
set_property C_EN_STRG_QUAL true [get_debug_cores u_ila_0 ]
|
||||
set_property C_ADV_TRIGGER true [get_debug_cores u_ila_0 ]
|
||||
set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0 ]
|
||||
set_property ALL_PROBE_SAME_MU_CNT 4 [get_debug_cores u_ila_0 ]
|
||||
endgroup
|
||||
connect_debug_port u_ila_0/clk [get_nets [list xlnx_ddr4_c0/inst/u_ddr4_infrastructure/addn_ui_clkout1 ]]
|
||||
set_property port_width 64 [get_debug_ports u_ila_0/probe0]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
|
||||
connect_debug_port u_ila_0/probe0 [get_nets [list {wallypipelinedsoc/core/lsu/LSUHWDATA[0]} {wallypipelinedsoc/core/lsu/LSUHWDATA[1]} {wallypipelinedsoc/core/lsu/LSUHWDATA[2]} {wallypipelinedsoc/core/lsu/LSUHWDATA[3]} {wallypipelinedsoc/core/lsu/LSUHWDATA[4]} {wallypipelinedsoc/core/lsu/LSUHWDATA[5]} {wallypipelinedsoc/core/lsu/LSUHWDATA[6]} {wallypipelinedsoc/core/lsu/LSUHWDATA[7]} {wallypipelinedsoc/core/lsu/LSUHWDATA[8]} {wallypipelinedsoc/core/lsu/LSUHWDATA[9]} {wallypipelinedsoc/core/lsu/LSUHWDATA[10]} {wallypipelinedsoc/core/lsu/LSUHWDATA[11]} {wallypipelinedsoc/core/lsu/LSUHWDATA[12]} {wallypipelinedsoc/core/lsu/LSUHWDATA[13]} {wallypipelinedsoc/core/lsu/LSUHWDATA[14]} {wallypipelinedsoc/core/lsu/LSUHWDATA[15]} {wallypipelinedsoc/core/lsu/LSUHWDATA[16]} {wallypipelinedsoc/core/lsu/LSUHWDATA[17]} {wallypipelinedsoc/core/lsu/LSUHWDATA[18]} {wallypipelinedsoc/core/lsu/LSUHWDATA[19]} {wallypipelinedsoc/core/lsu/LSUHWDATA[20]} {wallypipelinedsoc/core/lsu/LSUHWDATA[21]} {wallypipelinedsoc/core/lsu/LSUHWDATA[22]} {wallypipelinedsoc/core/lsu/LSUHWDATA[23]} {wallypipelinedsoc/core/lsu/LSUHWDATA[24]} {wallypipelinedsoc/core/lsu/LSUHWDATA[25]} {wallypipelinedsoc/core/lsu/LSUHWDATA[26]} {wallypipelinedsoc/core/lsu/LSUHWDATA[27]} {wallypipelinedsoc/core/lsu/LSUHWDATA[28]} {wallypipelinedsoc/core/lsu/LSUHWDATA[29]} {wallypipelinedsoc/core/lsu/LSUHWDATA[30]} {wallypipelinedsoc/core/lsu/LSUHWDATA[31]} {wallypipelinedsoc/core/lsu/LSUHWDATA[32]} {wallypipelinedsoc/core/lsu/LSUHWDATA[33]} {wallypipelinedsoc/core/lsu/LSUHWDATA[34]} {wallypipelinedsoc/core/lsu/LSUHWDATA[35]} {wallypipelinedsoc/core/lsu/LSUHWDATA[36]} {wallypipelinedsoc/core/lsu/LSUHWDATA[37]} {wallypipelinedsoc/core/lsu/LSUHWDATA[38]} {wallypipelinedsoc/core/lsu/LSUHWDATA[39]} {wallypipelinedsoc/core/lsu/LSUHWDATA[40]} {wallypipelinedsoc/core/lsu/LSUHWDATA[41]} {wallypipelinedsoc/core/lsu/LSUHWDATA[42]} {wallypipelinedsoc/core/lsu/LSUHWDATA[43]} {wallypipelinedsoc/core/lsu/LSUHWDATA[44]} {wallypipelinedsoc/core/lsu/LSUHWDATA[45]} {wallypipelinedsoc/core/lsu/LSUHWDATA[46]} {wallypipelinedsoc/core/lsu/LSUHWDATA[47]} {wallypipelinedsoc/core/lsu/LSUHWDATA[48]} {wallypipelinedsoc/core/lsu/LSUHWDATA[49]} {wallypipelinedsoc/core/lsu/LSUHWDATA[50]} {wallypipelinedsoc/core/lsu/LSUHWDATA[51]} {wallypipelinedsoc/core/lsu/LSUHWDATA[52]} {wallypipelinedsoc/core/lsu/LSUHWDATA[53]} {wallypipelinedsoc/core/lsu/LSUHWDATA[54]} {wallypipelinedsoc/core/lsu/LSUHWDATA[55]} {wallypipelinedsoc/core/lsu/LSUHWDATA[56]} {wallypipelinedsoc/core/lsu/LSUHWDATA[57]} {wallypipelinedsoc/core/lsu/LSUHWDATA[58]} {wallypipelinedsoc/core/lsu/LSUHWDATA[59]} {wallypipelinedsoc/core/lsu/LSUHWDATA[60]} {wallypipelinedsoc/core/lsu/LSUHWDATA[61]} {wallypipelinedsoc/core/lsu/LSUHWDATA[62]} {wallypipelinedsoc/core/lsu/LSUHWDATA[63]} ]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 64 [get_debug_ports u_ila_0/probe1]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
|
||||
connect_debug_port u_ila_0/probe1 [get_nets [list {wallypipelinedsoc/core/HRDATA[0]} {wallypipelinedsoc/core/HRDATA[1]} {wallypipelinedsoc/core/HRDATA[2]} {wallypipelinedsoc/core/HRDATA[3]} {wallypipelinedsoc/core/HRDATA[4]} {wallypipelinedsoc/core/HRDATA[5]} {wallypipelinedsoc/core/HRDATA[6]} {wallypipelinedsoc/core/HRDATA[7]} {wallypipelinedsoc/core/HRDATA[8]} {wallypipelinedsoc/core/HRDATA[9]} {wallypipelinedsoc/core/HRDATA[10]} {wallypipelinedsoc/core/HRDATA[11]} {wallypipelinedsoc/core/HRDATA[12]} {wallypipelinedsoc/core/HRDATA[13]} {wallypipelinedsoc/core/HRDATA[14]} {wallypipelinedsoc/core/HRDATA[15]} {wallypipelinedsoc/core/HRDATA[16]} {wallypipelinedsoc/core/HRDATA[17]} {wallypipelinedsoc/core/HRDATA[18]} {wallypipelinedsoc/core/HRDATA[19]} {wallypipelinedsoc/core/HRDATA[20]} {wallypipelinedsoc/core/HRDATA[21]} {wallypipelinedsoc/core/HRDATA[22]} {wallypipelinedsoc/core/HRDATA[23]} {wallypipelinedsoc/core/HRDATA[24]} {wallypipelinedsoc/core/HRDATA[25]} {wallypipelinedsoc/core/HRDATA[26]} {wallypipelinedsoc/core/HRDATA[27]} {wallypipelinedsoc/core/HRDATA[28]} {wallypipelinedsoc/core/HRDATA[29]} {wallypipelinedsoc/core/HRDATA[30]} {wallypipelinedsoc/core/HRDATA[31]} {wallypipelinedsoc/core/HRDATA[32]} {wallypipelinedsoc/core/HRDATA[33]} {wallypipelinedsoc/core/HRDATA[34]} {wallypipelinedsoc/core/HRDATA[35]} {wallypipelinedsoc/core/HRDATA[36]} {wallypipelinedsoc/core/HRDATA[37]} {wallypipelinedsoc/core/HRDATA[38]} {wallypipelinedsoc/core/HRDATA[39]} {wallypipelinedsoc/core/HRDATA[40]} {wallypipelinedsoc/core/HRDATA[41]} {wallypipelinedsoc/core/HRDATA[42]} {wallypipelinedsoc/core/HRDATA[43]} {wallypipelinedsoc/core/HRDATA[44]} {wallypipelinedsoc/core/HRDATA[45]} {wallypipelinedsoc/core/HRDATA[46]} {wallypipelinedsoc/core/HRDATA[47]} {wallypipelinedsoc/core/HRDATA[48]} {wallypipelinedsoc/core/HRDATA[49]} {wallypipelinedsoc/core/HRDATA[50]} {wallypipelinedsoc/core/HRDATA[51]} {wallypipelinedsoc/core/HRDATA[52]} {wallypipelinedsoc/core/HRDATA[53]} {wallypipelinedsoc/core/HRDATA[54]} {wallypipelinedsoc/core/HRDATA[55]} {wallypipelinedsoc/core/HRDATA[56]} {wallypipelinedsoc/core/HRDATA[57]} {wallypipelinedsoc/core/HRDATA[58]} {wallypipelinedsoc/core/HRDATA[59]} {wallypipelinedsoc/core/HRDATA[60]} {wallypipelinedsoc/core/HRDATA[61]} {wallypipelinedsoc/core/HRDATA[62]} {wallypipelinedsoc/core/HRDATA[63]} ]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 32 [get_debug_ports u_ila_0/probe2]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
|
||||
connect_debug_port u_ila_0/probe2 [get_nets [list {wallypipelinedsoc/core/lsu/LSUHADDR[0]} {wallypipelinedsoc/core/lsu/LSUHADDR[1]} {wallypipelinedsoc/core/lsu/LSUHADDR[2]} {wallypipelinedsoc/core/lsu/LSUHADDR[3]} {wallypipelinedsoc/core/lsu/LSUHADDR[4]} {wallypipelinedsoc/core/lsu/LSUHADDR[5]} {wallypipelinedsoc/core/lsu/LSUHADDR[6]} {wallypipelinedsoc/core/lsu/LSUHADDR[7]} {wallypipelinedsoc/core/lsu/LSUHADDR[8]} {wallypipelinedsoc/core/lsu/LSUHADDR[9]} {wallypipelinedsoc/core/lsu/LSUHADDR[10]} {wallypipelinedsoc/core/lsu/LSUHADDR[11]} {wallypipelinedsoc/core/lsu/LSUHADDR[12]} {wallypipelinedsoc/core/lsu/LSUHADDR[13]} {wallypipelinedsoc/core/lsu/LSUHADDR[14]} {wallypipelinedsoc/core/lsu/LSUHADDR[15]} {wallypipelinedsoc/core/lsu/LSUHADDR[16]} {wallypipelinedsoc/core/lsu/LSUHADDR[17]} {wallypipelinedsoc/core/lsu/LSUHADDR[18]} {wallypipelinedsoc/core/lsu/LSUHADDR[19]} {wallypipelinedsoc/core/lsu/LSUHADDR[20]} {wallypipelinedsoc/core/lsu/LSUHADDR[21]} {wallypipelinedsoc/core/lsu/LSUHADDR[22]} {wallypipelinedsoc/core/lsu/LSUHADDR[23]} {wallypipelinedsoc/core/lsu/LSUHADDR[24]} {wallypipelinedsoc/core/lsu/LSUHADDR[25]} {wallypipelinedsoc/core/lsu/LSUHADDR[26]} {wallypipelinedsoc/core/lsu/LSUHADDR[27]} {wallypipelinedsoc/core/lsu/LSUHADDR[28]} {wallypipelinedsoc/core/lsu/LSUHADDR[29]} {wallypipelinedsoc/core/lsu/LSUHADDR[30]} {wallypipelinedsoc/core/lsu/LSUHADDR[31]} ]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 6 [get_debug_ports u_ila_0/probe3]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
|
||||
connect_debug_port u_ila_0/probe3 [get_nets [list {wallypipelinedsoc/core/priv.priv/trap/MIP_REGW[1]} {wallypipelinedsoc/core/priv.priv/trap/MIP_REGW[3]} {wallypipelinedsoc/core/priv.priv/trap/MIP_REGW[5]} {wallypipelinedsoc/core/priv.priv/trap/MIP_REGW[7]} {wallypipelinedsoc/core/priv.priv/trap/MIP_REGW[9]} {wallypipelinedsoc/core/priv.priv/trap/MIP_REGW[11]} ]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 64 [get_debug_ports u_ila_0/probe4]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
|
||||
connect_debug_port u_ila_0/probe4 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[63]} ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 64 [get_debug_ports u_ila_0/probe5]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
|
||||
connect_debug_port u_ila_0/probe5 [get_nets [list {wallypipelinedsoc/core/lsu/ReadDataM[0]} {wallypipelinedsoc/core/lsu/ReadDataM[1]} {wallypipelinedsoc/core/lsu/ReadDataM[2]} {wallypipelinedsoc/core/lsu/ReadDataM[3]} {wallypipelinedsoc/core/lsu/ReadDataM[4]} {wallypipelinedsoc/core/lsu/ReadDataM[5]} {wallypipelinedsoc/core/lsu/ReadDataM[6]} {wallypipelinedsoc/core/lsu/ReadDataM[7]} {wallypipelinedsoc/core/lsu/ReadDataM[8]} {wallypipelinedsoc/core/lsu/ReadDataM[9]} {wallypipelinedsoc/core/lsu/ReadDataM[10]} {wallypipelinedsoc/core/lsu/ReadDataM[11]} {wallypipelinedsoc/core/lsu/ReadDataM[12]} {wallypipelinedsoc/core/lsu/ReadDataM[13]} {wallypipelinedsoc/core/lsu/ReadDataM[14]} {wallypipelinedsoc/core/lsu/ReadDataM[15]} {wallypipelinedsoc/core/lsu/ReadDataM[16]} {wallypipelinedsoc/core/lsu/ReadDataM[17]} {wallypipelinedsoc/core/lsu/ReadDataM[18]} {wallypipelinedsoc/core/lsu/ReadDataM[19]} {wallypipelinedsoc/core/lsu/ReadDataM[20]} {wallypipelinedsoc/core/lsu/ReadDataM[21]} {wallypipelinedsoc/core/lsu/ReadDataM[22]} {wallypipelinedsoc/core/lsu/ReadDataM[23]} {wallypipelinedsoc/core/lsu/ReadDataM[24]} {wallypipelinedsoc/core/lsu/ReadDataM[25]} {wallypipelinedsoc/core/lsu/ReadDataM[26]} {wallypipelinedsoc/core/lsu/ReadDataM[27]} {wallypipelinedsoc/core/lsu/ReadDataM[28]} {wallypipelinedsoc/core/lsu/ReadDataM[29]} {wallypipelinedsoc/core/lsu/ReadDataM[30]} {wallypipelinedsoc/core/lsu/ReadDataM[31]} {wallypipelinedsoc/core/lsu/ReadDataM[32]} {wallypipelinedsoc/core/lsu/ReadDataM[33]} {wallypipelinedsoc/core/lsu/ReadDataM[34]} {wallypipelinedsoc/core/lsu/ReadDataM[35]} {wallypipelinedsoc/core/lsu/ReadDataM[36]} {wallypipelinedsoc/core/lsu/ReadDataM[37]} {wallypipelinedsoc/core/lsu/ReadDataM[38]} {wallypipelinedsoc/core/lsu/ReadDataM[39]} {wallypipelinedsoc/core/lsu/ReadDataM[40]} {wallypipelinedsoc/core/lsu/ReadDataM[41]} {wallypipelinedsoc/core/lsu/ReadDataM[42]} {wallypipelinedsoc/core/lsu/ReadDataM[43]} {wallypipelinedsoc/core/lsu/ReadDataM[44]} {wallypipelinedsoc/core/lsu/ReadDataM[45]} {wallypipelinedsoc/core/lsu/ReadDataM[46]} {wallypipelinedsoc/core/lsu/ReadDataM[47]} {wallypipelinedsoc/core/lsu/ReadDataM[48]} {wallypipelinedsoc/core/lsu/ReadDataM[49]} {wallypipelinedsoc/core/lsu/ReadDataM[50]} {wallypipelinedsoc/core/lsu/ReadDataM[51]} {wallypipelinedsoc/core/lsu/ReadDataM[52]} {wallypipelinedsoc/core/lsu/ReadDataM[53]} {wallypipelinedsoc/core/lsu/ReadDataM[54]} {wallypipelinedsoc/core/lsu/ReadDataM[55]} {wallypipelinedsoc/core/lsu/ReadDataM[56]} {wallypipelinedsoc/core/lsu/ReadDataM[57]} {wallypipelinedsoc/core/lsu/ReadDataM[58]} {wallypipelinedsoc/core/lsu/ReadDataM[59]} {wallypipelinedsoc/core/lsu/ReadDataM[60]} {wallypipelinedsoc/core/lsu/ReadDataM[61]} {wallypipelinedsoc/core/lsu/ReadDataM[62]} {wallypipelinedsoc/core/lsu/ReadDataM[63]} ]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 64 [get_debug_ports u_ila_0/probe6]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
|
||||
connect_debug_port u_ila_0/probe6 [get_nets [list {wallypipelinedsoc/core/lsu/WriteDataM[0]} {wallypipelinedsoc/core/lsu/WriteDataM[1]} {wallypipelinedsoc/core/lsu/WriteDataM[2]} {wallypipelinedsoc/core/lsu/WriteDataM[3]} {wallypipelinedsoc/core/lsu/WriteDataM[4]} {wallypipelinedsoc/core/lsu/WriteDataM[5]} {wallypipelinedsoc/core/lsu/WriteDataM[6]} {wallypipelinedsoc/core/lsu/WriteDataM[7]} {wallypipelinedsoc/core/lsu/WriteDataM[8]} {wallypipelinedsoc/core/lsu/WriteDataM[9]} {wallypipelinedsoc/core/lsu/WriteDataM[10]} {wallypipelinedsoc/core/lsu/WriteDataM[11]} {wallypipelinedsoc/core/lsu/WriteDataM[12]} {wallypipelinedsoc/core/lsu/WriteDataM[13]} {wallypipelinedsoc/core/lsu/WriteDataM[14]} {wallypipelinedsoc/core/lsu/WriteDataM[15]} {wallypipelinedsoc/core/lsu/WriteDataM[16]} {wallypipelinedsoc/core/lsu/WriteDataM[17]} {wallypipelinedsoc/core/lsu/WriteDataM[18]} {wallypipelinedsoc/core/lsu/WriteDataM[19]} {wallypipelinedsoc/core/lsu/WriteDataM[20]} {wallypipelinedsoc/core/lsu/WriteDataM[21]} {wallypipelinedsoc/core/lsu/WriteDataM[22]} {wallypipelinedsoc/core/lsu/WriteDataM[23]} {wallypipelinedsoc/core/lsu/WriteDataM[24]} {wallypipelinedsoc/core/lsu/WriteDataM[25]} {wallypipelinedsoc/core/lsu/WriteDataM[26]} {wallypipelinedsoc/core/lsu/WriteDataM[27]} {wallypipelinedsoc/core/lsu/WriteDataM[28]} {wallypipelinedsoc/core/lsu/WriteDataM[29]} {wallypipelinedsoc/core/lsu/WriteDataM[30]} {wallypipelinedsoc/core/lsu/WriteDataM[31]} {wallypipelinedsoc/core/lsu/WriteDataM[32]} {wallypipelinedsoc/core/lsu/WriteDataM[33]} {wallypipelinedsoc/core/lsu/WriteDataM[34]} {wallypipelinedsoc/core/lsu/WriteDataM[35]} {wallypipelinedsoc/core/lsu/WriteDataM[36]} {wallypipelinedsoc/core/lsu/WriteDataM[37]} {wallypipelinedsoc/core/lsu/WriteDataM[38]} {wallypipelinedsoc/core/lsu/WriteDataM[39]} {wallypipelinedsoc/core/lsu/WriteDataM[40]} {wallypipelinedsoc/core/lsu/WriteDataM[41]} {wallypipelinedsoc/core/lsu/WriteDataM[42]} {wallypipelinedsoc/core/lsu/WriteDataM[43]} {wallypipelinedsoc/core/lsu/WriteDataM[44]} {wallypipelinedsoc/core/lsu/WriteDataM[45]} {wallypipelinedsoc/core/lsu/WriteDataM[46]} {wallypipelinedsoc/core/lsu/WriteDataM[47]} {wallypipelinedsoc/core/lsu/WriteDataM[48]} {wallypipelinedsoc/core/lsu/WriteDataM[49]} {wallypipelinedsoc/core/lsu/WriteDataM[50]} {wallypipelinedsoc/core/lsu/WriteDataM[51]} {wallypipelinedsoc/core/lsu/WriteDataM[52]} {wallypipelinedsoc/core/lsu/WriteDataM[53]} {wallypipelinedsoc/core/lsu/WriteDataM[54]} {wallypipelinedsoc/core/lsu/WriteDataM[55]} {wallypipelinedsoc/core/lsu/WriteDataM[56]} {wallypipelinedsoc/core/lsu/WriteDataM[57]} {wallypipelinedsoc/core/lsu/WriteDataM[58]} {wallypipelinedsoc/core/lsu/WriteDataM[59]} {wallypipelinedsoc/core/lsu/WriteDataM[60]} {wallypipelinedsoc/core/lsu/WriteDataM[61]} {wallypipelinedsoc/core/lsu/WriteDataM[62]} {wallypipelinedsoc/core/lsu/WriteDataM[63]} ]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 64 [get_debug_ports u_ila_0/probe7]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7]
|
||||
connect_debug_port u_ila_0/probe7 [get_nets [list {wallypipelinedsoc/core/PCM[0]} {wallypipelinedsoc/core/PCM[1]} {wallypipelinedsoc/core/PCM[2]} {wallypipelinedsoc/core/PCM[3]} {wallypipelinedsoc/core/PCM[4]} {wallypipelinedsoc/core/PCM[5]} {wallypipelinedsoc/core/PCM[6]} {wallypipelinedsoc/core/PCM[7]} {wallypipelinedsoc/core/PCM[8]} {wallypipelinedsoc/core/PCM[9]} {wallypipelinedsoc/core/PCM[10]} {wallypipelinedsoc/core/PCM[11]} {wallypipelinedsoc/core/PCM[12]} {wallypipelinedsoc/core/PCM[13]} {wallypipelinedsoc/core/PCM[14]} {wallypipelinedsoc/core/PCM[15]} {wallypipelinedsoc/core/PCM[16]} {wallypipelinedsoc/core/PCM[17]} {wallypipelinedsoc/core/PCM[18]} {wallypipelinedsoc/core/PCM[19]} {wallypipelinedsoc/core/PCM[20]} {wallypipelinedsoc/core/PCM[21]} {wallypipelinedsoc/core/PCM[22]} {wallypipelinedsoc/core/PCM[23]} {wallypipelinedsoc/core/PCM[24]} {wallypipelinedsoc/core/PCM[25]} {wallypipelinedsoc/core/PCM[26]} {wallypipelinedsoc/core/PCM[27]} {wallypipelinedsoc/core/PCM[28]} {wallypipelinedsoc/core/PCM[29]} {wallypipelinedsoc/core/PCM[30]} {wallypipelinedsoc/core/PCM[31]} {wallypipelinedsoc/core/PCM[32]} {wallypipelinedsoc/core/PCM[33]} {wallypipelinedsoc/core/PCM[34]} {wallypipelinedsoc/core/PCM[35]} {wallypipelinedsoc/core/PCM[36]} {wallypipelinedsoc/core/PCM[37]} {wallypipelinedsoc/core/PCM[38]} {wallypipelinedsoc/core/PCM[39]} {wallypipelinedsoc/core/PCM[40]} {wallypipelinedsoc/core/PCM[41]} {wallypipelinedsoc/core/PCM[42]} {wallypipelinedsoc/core/PCM[43]} {wallypipelinedsoc/core/PCM[44]} {wallypipelinedsoc/core/PCM[45]} {wallypipelinedsoc/core/PCM[46]} {wallypipelinedsoc/core/PCM[47]} {wallypipelinedsoc/core/PCM[48]} {wallypipelinedsoc/core/PCM[49]} {wallypipelinedsoc/core/PCM[50]} {wallypipelinedsoc/core/PCM[51]} {wallypipelinedsoc/core/PCM[52]} {wallypipelinedsoc/core/PCM[53]} {wallypipelinedsoc/core/PCM[54]} {wallypipelinedsoc/core/PCM[55]} {wallypipelinedsoc/core/PCM[56]} {wallypipelinedsoc/core/PCM[57]} {wallypipelinedsoc/core/PCM[58]} {wallypipelinedsoc/core/PCM[59]} {wallypipelinedsoc/core/PCM[60]} {wallypipelinedsoc/core/PCM[61]} {wallypipelinedsoc/core/PCM[62]} {wallypipelinedsoc/core/PCM[63]} ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 64 [get_debug_ports u_ila_0/probe8]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8]
|
||||
connect_debug_port u_ila_0/probe8 [get_nets [list {wallypipelinedsoc/core/IEUAdrM[0]} {wallypipelinedsoc/core/IEUAdrM[1]} {wallypipelinedsoc/core/IEUAdrM[2]} {wallypipelinedsoc/core/IEUAdrM[3]} {wallypipelinedsoc/core/IEUAdrM[4]} {wallypipelinedsoc/core/IEUAdrM[5]} {wallypipelinedsoc/core/IEUAdrM[6]} {wallypipelinedsoc/core/IEUAdrM[7]} {wallypipelinedsoc/core/IEUAdrM[8]} {wallypipelinedsoc/core/IEUAdrM[9]} {wallypipelinedsoc/core/IEUAdrM[10]} {wallypipelinedsoc/core/IEUAdrM[11]} {wallypipelinedsoc/core/IEUAdrM[12]} {wallypipelinedsoc/core/IEUAdrM[13]} {wallypipelinedsoc/core/IEUAdrM[14]} {wallypipelinedsoc/core/IEUAdrM[15]} {wallypipelinedsoc/core/IEUAdrM[16]} {wallypipelinedsoc/core/IEUAdrM[17]} {wallypipelinedsoc/core/IEUAdrM[18]} {wallypipelinedsoc/core/IEUAdrM[19]} {wallypipelinedsoc/core/IEUAdrM[20]} {wallypipelinedsoc/core/IEUAdrM[21]} {wallypipelinedsoc/core/IEUAdrM[22]} {wallypipelinedsoc/core/IEUAdrM[23]} {wallypipelinedsoc/core/IEUAdrM[24]} {wallypipelinedsoc/core/IEUAdrM[25]} {wallypipelinedsoc/core/IEUAdrM[26]} {wallypipelinedsoc/core/IEUAdrM[27]} {wallypipelinedsoc/core/IEUAdrM[28]} {wallypipelinedsoc/core/IEUAdrM[29]} {wallypipelinedsoc/core/IEUAdrM[30]} {wallypipelinedsoc/core/IEUAdrM[31]} {wallypipelinedsoc/core/IEUAdrM[32]} {wallypipelinedsoc/core/IEUAdrM[33]} {wallypipelinedsoc/core/IEUAdrM[34]} {wallypipelinedsoc/core/IEUAdrM[35]} {wallypipelinedsoc/core/IEUAdrM[36]} {wallypipelinedsoc/core/IEUAdrM[37]} {wallypipelinedsoc/core/IEUAdrM[38]} {wallypipelinedsoc/core/IEUAdrM[39]} {wallypipelinedsoc/core/IEUAdrM[40]} {wallypipelinedsoc/core/IEUAdrM[41]} {wallypipelinedsoc/core/IEUAdrM[42]} {wallypipelinedsoc/core/IEUAdrM[43]} {wallypipelinedsoc/core/IEUAdrM[44]} {wallypipelinedsoc/core/IEUAdrM[45]} {wallypipelinedsoc/core/IEUAdrM[46]} {wallypipelinedsoc/core/IEUAdrM[47]} {wallypipelinedsoc/core/IEUAdrM[48]} {wallypipelinedsoc/core/IEUAdrM[49]} {wallypipelinedsoc/core/IEUAdrM[50]} {wallypipelinedsoc/core/IEUAdrM[51]} {wallypipelinedsoc/core/IEUAdrM[52]} {wallypipelinedsoc/core/IEUAdrM[53]} {wallypipelinedsoc/core/IEUAdrM[54]} {wallypipelinedsoc/core/IEUAdrM[55]} {wallypipelinedsoc/core/IEUAdrM[56]} {wallypipelinedsoc/core/IEUAdrM[57]} {wallypipelinedsoc/core/IEUAdrM[58]} {wallypipelinedsoc/core/IEUAdrM[59]} {wallypipelinedsoc/core/IEUAdrM[60]} {wallypipelinedsoc/core/IEUAdrM[61]} {wallypipelinedsoc/core/IEUAdrM[62]} {wallypipelinedsoc/core/IEUAdrM[63]} ]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 32 [get_debug_ports u_ila_0/probe9]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9]
|
||||
connect_debug_port u_ila_0/probe9 [get_nets [list {wallypipelinedsoc/core/InstrM[0]} {wallypipelinedsoc/core/InstrM[1]} {wallypipelinedsoc/core/InstrM[2]} {wallypipelinedsoc/core/InstrM[3]} {wallypipelinedsoc/core/InstrM[4]} {wallypipelinedsoc/core/InstrM[5]} {wallypipelinedsoc/core/InstrM[6]} {wallypipelinedsoc/core/InstrM[7]} {wallypipelinedsoc/core/InstrM[8]} {wallypipelinedsoc/core/InstrM[9]} {wallypipelinedsoc/core/InstrM[10]} {wallypipelinedsoc/core/InstrM[11]} {wallypipelinedsoc/core/InstrM[12]} {wallypipelinedsoc/core/InstrM[13]} {wallypipelinedsoc/core/InstrM[14]} {wallypipelinedsoc/core/InstrM[15]} {wallypipelinedsoc/core/InstrM[16]} {wallypipelinedsoc/core/InstrM[17]} {wallypipelinedsoc/core/InstrM[18]} {wallypipelinedsoc/core/InstrM[19]} {wallypipelinedsoc/core/InstrM[20]} {wallypipelinedsoc/core/InstrM[21]} {wallypipelinedsoc/core/InstrM[22]} {wallypipelinedsoc/core/InstrM[23]} {wallypipelinedsoc/core/InstrM[24]} {wallypipelinedsoc/core/InstrM[25]} {wallypipelinedsoc/core/InstrM[26]} {wallypipelinedsoc/core/InstrM[27]} {wallypipelinedsoc/core/InstrM[28]} {wallypipelinedsoc/core/InstrM[29]} {wallypipelinedsoc/core/InstrM[30]} {wallypipelinedsoc/core/InstrM[31]} ]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 2 [get_debug_ports u_ila_0/probe10]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10]
|
||||
connect_debug_port u_ila_0/probe10 [get_nets [list {wallypipelinedsoc/core/MemRWM[0]} {wallypipelinedsoc/core/MemRWM[1]} ]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 6 [get_debug_ports u_ila_0/probe11]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11]
|
||||
connect_debug_port u_ila_0/probe11 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW[11]} ]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 64 [get_debug_ports u_ila_0/probe12]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12]
|
||||
connect_debug_port u_ila_0/probe12 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[63]} ]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 6 [get_debug_ports u_ila_0/probe13]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13]
|
||||
connect_debug_port u_ila_0/probe13 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrm/MIP_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIP_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIP_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIP_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIP_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIP_REGW[11]} ]]
|
||||
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 4 [get_debug_ports u_ila_0/probe14]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe14]
|
||||
connect_debug_port u_ila_0/probe14 [get_nets [list {wallypipelinedsoc/core/lsu/bus.dcache.dcache/cachefsm/CurrState[0]} {wallypipelinedsoc/core/lsu/bus.dcache.dcache/cachefsm/CurrState[1]} {wallypipelinedsoc/core/lsu/bus.dcache.dcache/cachefsm/CurrState[2]} {wallypipelinedsoc/core/lsu/bus.dcache.dcache/cachefsm/CurrState[3]} ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 64 [get_debug_ports u_ila_0/probe15]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe15]
|
||||
connect_debug_port u_ila_0/probe15 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[63]} ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 64 [get_debug_ports u_ila_0/probe16]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe16]
|
||||
connect_debug_port u_ila_0/probe16 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[63]} ]]
|
||||
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 5 [get_debug_ports u_ila_0/probe17]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe17]
|
||||
connect_debug_port u_ila_0/probe17 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/MCR[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/MCR[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/MCR[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/MCR[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/MCR[4]} ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 8 [get_debug_ports u_ila_0/probe18]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe18]
|
||||
connect_debug_port u_ila_0/probe18 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[7]} ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 64 [get_debug_ports u_ila_0/probe19]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe19]
|
||||
connect_debug_port u_ila_0/probe19 [get_nets [list {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[0]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[1]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[2]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[3]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[4]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[5]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[6]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[7]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[8]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[9]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[10]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[11]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[12]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[13]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[14]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[15]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[16]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[17]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[18]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[19]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[20]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[21]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[22]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[23]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[24]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[25]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[26]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[27]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[28]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[29]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[30]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[31]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[32]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[33]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[34]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[35]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[36]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[37]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[38]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[39]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[40]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[41]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[42]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[43]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[44]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[45]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[46]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[47]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[48]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[49]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[50]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[51]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[52]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[53]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[54]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[55]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[56]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[57]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[58]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[59]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[60]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[61]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[62]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[63]} ]]
|
||||
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 63 [get_debug_ports u_ila_0/probe20]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe20]
|
||||
connect_debug_port u_ila_0/probe20 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[63]} ]]
|
||||
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 4 [get_debug_ports u_ila_0/probe21]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe21]
|
||||
connect_debug_port u_ila_0/probe21 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/MSR[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/MSR[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/MSR[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/MSR[3]} ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 6 [get_debug_ports u_ila_0/probe22]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe22]
|
||||
connect_debug_port u_ila_0/probe22 [get_nets [list {wallypipelinedsoc/core/priv.priv/trap/MIE_REGW[1]} {wallypipelinedsoc/core/priv.priv/trap/MIE_REGW[3]} {wallypipelinedsoc/core/priv.priv/trap/MIE_REGW[5]} {wallypipelinedsoc/core/priv.priv/trap/MIE_REGW[7]} {wallypipelinedsoc/core/priv.priv/trap/MIE_REGW[9]} {wallypipelinedsoc/core/priv.priv/trap/MIE_REGW[11]} ]]
|
||||
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 2 [get_debug_ports u_ila_0/probe23]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe23]
|
||||
connect_debug_port u_ila_0/probe23 [get_nets [list {wallypipelinedsoc/core/lsu/LSUHSIZE[0]} {wallypipelinedsoc/core/lsu/LSUHSIZE[1]} ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe24]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe24]
|
||||
connect_debug_port u_ila_0/probe24 [get_nets [list wallypipelinedsoc/core/lsu/LSUHREADY ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe25]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe25]
|
||||
connect_debug_port u_ila_0/probe25 [get_nets [list wallypipelinedsoc/core/lsu/LSUHWRITE ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 3 [get_debug_ports u_ila_0/probe26]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe26]
|
||||
connect_debug_port u_ila_0/probe26 [get_nets [list {wallypipelinedsoc/core/lsu/LSUHBURST[0]} wallypipelinedsoc/core/lsu/LSUHBURST[1] wallypipelinedsoc/core/lsu/LSUHBURST[2] ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe27]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe27]
|
||||
connect_debug_port u_ila_0/probe27 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/BreakpointFaultM ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe28]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe28]
|
||||
connect_debug_port u_ila_0/probe28 [get_nets [list wallypipelinedsoc/uncore.uncore/uart.uart/DTRb ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe29]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe29]
|
||||
connect_debug_port u_ila_0/probe29 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/EcallFaultM ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe30]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe30]
|
||||
connect_debug_port u_ila_0/probe30 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/IllegalInstrFaultM ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe31]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe31]
|
||||
connect_debug_port u_ila_0/probe31 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/InstrAccessFaultM ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe32]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe32]
|
||||
connect_debug_port u_ila_0/probe32 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/InstrPageFaultM ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe33]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe33]
|
||||
connect_debug_port u_ila_0/probe33 [get_nets [list wallypipelinedsoc/core/InstrValidM ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe34]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe34]
|
||||
connect_debug_port u_ila_0/probe34 [get_nets [list wallypipelinedsoc/uncore.uncore/uart.uart/INTR ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe35]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe35]
|
||||
connect_debug_port u_ila_0/probe35 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/LoadAccessFaultM ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe36]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe36]
|
||||
connect_debug_port u_ila_0/probe36 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/LoadMisalignedFaultM ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe37]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe37]
|
||||
connect_debug_port u_ila_0/probe37 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/LoadPageFaultM ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe38]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe38]
|
||||
connect_debug_port u_ila_0/probe38 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/mretM ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe39]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe39]
|
||||
connect_debug_port u_ila_0/probe39 [get_nets [list wallypipelinedsoc/uncore.uncore/uart.uart/OUT1b ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe40]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe40]
|
||||
connect_debug_port u_ila_0/probe40 [get_nets [list wallypipelinedsoc/uncore.uncore/uart.uart/OUT2b ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe41]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe41]
|
||||
connect_debug_port u_ila_0/probe41 [get_nets [list wallypipelinedsoc/uncore.uncore/uart.uart/RTSb ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe42]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe42]
|
||||
connect_debug_port u_ila_0/probe42 [get_nets [list wallypipelinedsoc/uncore.uncore/uart.uart/RXRDYb ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe43]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe43]
|
||||
connect_debug_port u_ila_0/probe43 [get_nets [list wallypipelinedsoc/uncore.uncore/uart.uart/SIN ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe44]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe44]
|
||||
connect_debug_port u_ila_0/probe44 [get_nets [list wallypipelinedsoc/uncore.uncore/uart.uart/SOUT ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe45]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe45]
|
||||
connect_debug_port u_ila_0/probe45 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/sretM ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe46]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe46]
|
||||
connect_debug_port u_ila_0/probe46 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/StoreAmoAccessFaultM ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe47]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe47]
|
||||
connect_debug_port u_ila_0/probe47 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/StoreAmoMisalignedFaultM ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe48]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe48]
|
||||
connect_debug_port u_ila_0/probe48 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/StoreAmoPageFaultM ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe49]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe49]
|
||||
connect_debug_port u_ila_0/probe49 [get_nets [list wallypipelinedsoc/core/TrapM ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe50]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe50]
|
||||
connect_debug_port u_ila_0/probe50 [get_nets [list wallypipelinedsoc/uncore.uncore/uart.uart/TXRDYb ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe51]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe51]
|
||||
connect_debug_port u_ila_0/probe51 [get_nets [list wallypipelinedsoc/core/hzu/BPWrongE ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe52]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe52]
|
||||
connect_debug_port u_ila_0/probe52 [get_nets [list wallypipelinedsoc/core/hzu/CSRWriteFenceM ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe53]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe53]
|
||||
connect_debug_port u_ila_0/probe53 [get_nets [list wallypipelinedsoc/core/hzu/RetM ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe54]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe54]
|
||||
connect_debug_port u_ila_0/probe54 [get_nets [list wallypipelinedsoc/core/TrapM ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe55]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe55]
|
||||
connect_debug_port u_ila_0/probe55 [get_nets [list wallypipelinedsoc/core/hzu/LoadStallD ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe56]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe56]
|
||||
connect_debug_port u_ila_0/probe56 [get_nets [list wallypipelinedsoc/core/hzu/StoreStallD ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe57]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe57]
|
||||
connect_debug_port u_ila_0/probe57 [get_nets [list wallypipelinedsoc/core/hzu/MDUStallD ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe58]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe58]
|
||||
connect_debug_port u_ila_0/probe58 [get_nets [list wallypipelinedsoc/core/hzu/CSRRdStallD ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe59]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe59]
|
||||
connect_debug_port u_ila_0/probe59 [get_nets [list wallypipelinedsoc/core/hzu/LSUStallM ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe60]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe60]
|
||||
connect_debug_port u_ila_0/probe60 [get_nets [list wallypipelinedsoc/core/hzu/IFUStallF ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe61]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe61]
|
||||
connect_debug_port u_ila_0/probe61 [get_nets [list wallypipelinedsoc/core/hzu/FPUStallD ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe62]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe62]
|
||||
connect_debug_port u_ila_0/probe62 [get_nets [list wallypipelinedsoc/core/hzu/FCvtIntStallD ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 7 [get_debug_ports u_ila_0/probe63]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe63]
|
||||
connect_debug_port u_ila_0/probe63 [get_nets [list {wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[0][1]} {wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[0][2]} {wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[0][3]} {wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[0][4]} {wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[0][5]} {wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[0][6]} {wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[0][7]} ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe64]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe64]
|
||||
connect_debug_port u_ila_0/probe64 [get_nets [list wallypipelinedsoc/core/hzu/FDivBusyE ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe65]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe65]
|
||||
connect_debug_port u_ila_0/probe65 [get_nets [list wallypipelinedsoc/core/hzu/EcallFaultM ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe66]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe66]
|
||||
connect_debug_port u_ila_0/probe66 [get_nets [list wallypipelinedsoc/core/hzu/BreakpointFaultM ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe67]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe67]
|
||||
connect_debug_port u_ila_0/probe67 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrIP} ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe68]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe68]
|
||||
connect_debug_port u_ila_0/probe68 [get_nets [list wallypipelinedsoc/core/hzu/StallF ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe69]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe69]
|
||||
connect_debug_port u_ila_0/probe69 [get_nets [list wallypipelinedsoc/core/hzu/StallDCause]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe70]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe70]
|
||||
connect_debug_port u_ila_0/probe70 [get_nets [list wallypipelinedsoc/core/hzu/StallE ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe71]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe71]
|
||||
connect_debug_port u_ila_0/probe71 [get_nets [list wallypipelinedsoc/core/hzu/StallM ]]
|
||||
|
||||
# StallW is StallM. trying to connect to StallW causes issues.
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe72]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe72]
|
||||
connect_debug_port u_ila_0/probe72 [get_nets [list wallypipelinedsoc/core/hzu/StallM ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe73]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe73]
|
||||
connect_debug_port u_ila_0/probe73 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrIP} ]]
|
||||
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe74]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe74]
|
||||
connect_debug_port u_ila_0/probe74 [get_nets [list wallypipelinedsoc/core/hzu/FlushD ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe75]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe75]
|
||||
connect_debug_port u_ila_0/probe75 [get_nets [list wallypipelinedsoc/core/hzu/FlushE ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe76]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe76]
|
||||
connect_debug_port u_ila_0/probe76 [get_nets [list wallypipelinedsoc/core/hzu/FlushM ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe77]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe77]
|
||||
connect_debug_port u_ila_0/probe77 [get_nets [list wallypipelinedsoc/core/hzu/FlushW ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 4 [get_debug_ports u_ila_0/probe78]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe78]
|
||||
connect_debug_port u_ila_0/probe78 [get_nets [list {wallypipelinedsoc/core/ifu/bus.icache.icache/cachefsm/CurrState[0]} {wallypipelinedsoc/core/ifu/bus.icache.icache/cachefsm/CurrState[1]} {wallypipelinedsoc/core/ifu/bus.icache.icache/cachefsm/CurrState[2]} {wallypipelinedsoc/core/ifu/bus.icache.icache/cachefsm/CurrState[3]}]]
|
||||
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 2 [get_debug_ports u_ila_0/probe79]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe79]
|
||||
connect_debug_port u_ila_0/probe79 [get_nets [list {wallypipelinedsoc/core/ebu.ebu/HTRANS[0]} {wallypipelinedsoc/core/ebu.ebu/HTRANS[1]}]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe80]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe80]
|
||||
connect_debug_port u_ila_0/probe80 [get_nets [list wallypipelinedsoc/core/ifu/IFUHREADY ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 32 [get_debug_ports u_ila_0/probe81]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe81]
|
||||
connect_debug_port u_ila_0/probe81 [get_nets [list {wallypipelinedsoc/core/ifu/IFUHADDR[0]} {wallypipelinedsoc/core/ifu/IFUHADDR[1]} {wallypipelinedsoc/core/ifu/IFUHADDR[2]} {wallypipelinedsoc/core/ifu/IFUHADDR[3]} {wallypipelinedsoc/core/ifu/IFUHADDR[4]} {wallypipelinedsoc/core/ifu/IFUHADDR[5]} {wallypipelinedsoc/core/ifu/IFUHADDR[6]} {wallypipelinedsoc/core/ifu/IFUHADDR[7]} {wallypipelinedsoc/core/ifu/IFUHADDR[8]} {wallypipelinedsoc/core/ifu/IFUHADDR[9]} {wallypipelinedsoc/core/ifu/IFUHADDR[10]} {wallypipelinedsoc/core/ifu/IFUHADDR[11]} {wallypipelinedsoc/core/ifu/IFUHADDR[12]} {wallypipelinedsoc/core/ifu/IFUHADDR[13]} {wallypipelinedsoc/core/ifu/IFUHADDR[14]} {wallypipelinedsoc/core/ifu/IFUHADDR[15]} {wallypipelinedsoc/core/ifu/IFUHADDR[16]} {wallypipelinedsoc/core/ifu/IFUHADDR[17]} {wallypipelinedsoc/core/ifu/IFUHADDR[18]} {wallypipelinedsoc/core/ifu/IFUHADDR[19]} {wallypipelinedsoc/core/ifu/IFUHADDR[20]} {wallypipelinedsoc/core/ifu/IFUHADDR[21]} {wallypipelinedsoc/core/ifu/IFUHADDR[22]} {wallypipelinedsoc/core/ifu/IFUHADDR[23]} {wallypipelinedsoc/core/ifu/IFUHADDR[24]} {wallypipelinedsoc/core/ifu/IFUHADDR[25]} {wallypipelinedsoc/core/ifu/IFUHADDR[26]} {wallypipelinedsoc/core/ifu/IFUHADDR[27]} {wallypipelinedsoc/core/ifu/IFUHADDR[28]} {wallypipelinedsoc/core/ifu/IFUHADDR[29]} {wallypipelinedsoc/core/ifu/IFUHADDR[30]} {wallypipelinedsoc/core/ifu/IFUHADDR[31]}]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 2 [get_debug_ports u_ila_0/probe82]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe82]
|
||||
connect_debug_port u_ila_0/probe82 [get_nets [list {wallypipelinedsoc/core/ifu/IFUHTRANS[0]} {wallypipelinedsoc/core/ifu/IFUHTRANS[0]}]]
|
||||
|
||||
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 2 [get_debug_ports u_ila_0/probe83]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe83]
|
||||
connect_debug_port u_ila_0/probe83 [get_nets [list {wallypipelinedsoc/core/ebu.ebu/HTRANS[0]} {wallypipelinedsoc/core/ebu.ebu/HTRANS[1]}]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 53 [get_debug_ports u_ila_0/probe84]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe84]
|
||||
connect_debug_port u_ila_0/probe84 [get_nets [list {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][1]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][2]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][3]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][4]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][5]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][6]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][7]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][8]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][9]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][10]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][11]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][12]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][13]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][14]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][15]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][16]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][17]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][18]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][19]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][20]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][21]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][22]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][23]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][24]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][25]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][26]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][27]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][28]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][29]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][30]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][31]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][32]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][33]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][34]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][35]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][36]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][37]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][38]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][39]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][40]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][41]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][42]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][43]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][44]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][45]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][46]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][47]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][48]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][49]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][50]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][51]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][52]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][53]} ]]
|
||||
|
||||
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 32 [get_debug_ports u_ila_0/probe85]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe85]
|
||||
connect_debug_port u_ila_0/probe85 [get_nets [list {wallypipelinedsoc/core/ebu.ebu/HADDR[0]} {wallypipelinedsoc/core/ebu.ebu/HADDR[1]} {wallypipelinedsoc/core/ebu.ebu/HADDR[2]} {wallypipelinedsoc/core/ebu.ebu/HADDR[3]} {wallypipelinedsoc/core/ebu.ebu/HADDR[4]} {wallypipelinedsoc/core/ebu.ebu/HADDR[5]} {wallypipelinedsoc/core/ebu.ebu/HADDR[6]} {wallypipelinedsoc/core/ebu.ebu/HADDR[7]} {wallypipelinedsoc/core/ebu.ebu/HADDR[8]} {wallypipelinedsoc/core/ebu.ebu/HADDR[9]} {wallypipelinedsoc/core/ebu.ebu/HADDR[10]} {wallypipelinedsoc/core/ebu.ebu/HADDR[11]} {wallypipelinedsoc/core/ebu.ebu/HADDR[12]} {wallypipelinedsoc/core/ebu.ebu/HADDR[13]} {wallypipelinedsoc/core/ebu.ebu/HADDR[14]} {wallypipelinedsoc/core/ebu.ebu/HADDR[15]} {wallypipelinedsoc/core/ebu.ebu/HADDR[16]} {wallypipelinedsoc/core/ebu.ebu/HADDR[17]} {wallypipelinedsoc/core/ebu.ebu/HADDR[18]} {wallypipelinedsoc/core/ebu.ebu/HADDR[19]} {wallypipelinedsoc/core/ebu.ebu/HADDR[20]} {wallypipelinedsoc/core/ebu.ebu/HADDR[21]} {wallypipelinedsoc/core/ebu.ebu/HADDR[22]} {wallypipelinedsoc/core/ebu.ebu/HADDR[23]} {wallypipelinedsoc/core/ebu.ebu/HADDR[24]} {wallypipelinedsoc/core/ebu.ebu/HADDR[25]} {wallypipelinedsoc/core/ebu.ebu/HADDR[26]} {wallypipelinedsoc/core/ebu.ebu/HADDR[27]} {wallypipelinedsoc/core/ebu.ebu/HADDR[28]} {wallypipelinedsoc/core/ebu.ebu/HADDR[29]} {wallypipelinedsoc/core/ebu.ebu/HADDR[30]} {wallypipelinedsoc/core/ebu.ebu/HADDR[31]}]]
|
||||
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe86]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe86]
|
||||
connect_debug_port u_ila_0/probe86 [get_nets [list {wallypipelinedsoc/core/ebu.ebu/HREADY}]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe87]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe87]
|
||||
connect_debug_port u_ila_0/probe87 [get_nets [list {wallypipelinedsoc/core/ebu.ebu/HRESP}]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe88]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe88]
|
||||
connect_debug_port u_ila_0/probe88 [get_nets [list {wallypipelinedsoc/core/ebu.ebu/HWRITE}]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 3 [get_debug_ports u_ila_0/probe89]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe89]
|
||||
connect_debug_port u_ila_0/probe89 [get_nets [list {wallypipelinedsoc/core/ebu.ebu/HSIZE[0]} {wallypipelinedsoc/core/ebu.ebu/HSIZE[1]} {wallypipelinedsoc/core/ebu.ebu/HSIZE[2]}]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 3 [get_debug_ports u_ila_0/probe90]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe90]
|
||||
connect_debug_port u_ila_0/probe90 [get_nets [list {wallypipelinedsoc/core/ebu.ebu/HBURST[0]} {wallypipelinedsoc/core/ebu.ebu/HBURST[1]} {wallypipelinedsoc/core/ebu.ebu/HBURST[2]}]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 4 [get_debug_ports u_ila_0/probe91]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe91]
|
||||
connect_debug_port u_ila_0/probe91 [get_nets [list {wallypipelinedsoc/core/ebu.ebu/HPROT[0]} {wallypipelinedsoc/core/ebu.ebu/HPROT[1]} {wallypipelinedsoc/core/ebu.ebu/HPROT[2]} {wallypipelinedsoc/core/ebu.ebu/HPROT[3]}]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 4 [get_debug_ports u_ila_0/probe92]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe92]
|
||||
connect_debug_port u_ila_0/probe92 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/IER[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/IER[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/IER[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/IER[3]} ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe93]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe93]
|
||||
connect_debug_port u_ila_0/probe93 [get_nets [list {wallypipelinedsoc/core/priv.priv/InterruptM}]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe94]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe94]
|
||||
connect_debug_port u_ila_0/probe94 [get_nets [list wallypipelinedsoc/core/lsu/ITLBMissF]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe95]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe95]
|
||||
connect_debug_port u_ila_0/probe95 [get_nets [list wallypipelinedsoc/core/lsu/DTLBMissM]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe96]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe96]
|
||||
connect_debug_port u_ila_0/probe96 [get_nets [list wallypipelinedsoc/core/lsu/ITLBWriteF]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe97]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe97]
|
||||
connect_debug_port u_ila_0/probe97 [get_nets [list wallypipelinedsoc/core/lsu/DTLBWriteM]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 4 [get_debug_ports u_ila_0/probe98]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe98]
|
||||
connect_debug_port u_ila_0/probe98 [get_nets [list {wallypipelinedsoc/core/lsu/hptw.hptw/WalkerState[0]} {wallypipelinedsoc/core/lsu/hptw.hptw/WalkerState[1]} {wallypipelinedsoc/core/lsu/hptw.hptw/WalkerState[2]} {wallypipelinedsoc/core/lsu/hptw.hptw/WalkerState[3]}]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 64 [get_debug_ports u_ila_0/probe99]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe99]
|
||||
connect_debug_port u_ila_0/probe99 [get_nets [list {wallypipelinedsoc/core/SrcAM[0]} {wallypipelinedsoc/core/SrcAM[1]} {wallypipelinedsoc/core/SrcAM[2]} {wallypipelinedsoc/core/SrcAM[3]} {wallypipelinedsoc/core/SrcAM[4]} {wallypipelinedsoc/core/SrcAM[5]} {wallypipelinedsoc/core/SrcAM[6]} {wallypipelinedsoc/core/SrcAM[7]} {wallypipelinedsoc/core/SrcAM[8]} {wallypipelinedsoc/core/SrcAM[9]} {wallypipelinedsoc/core/SrcAM[10]} {wallypipelinedsoc/core/SrcAM[11]} {wallypipelinedsoc/core/SrcAM[12]} {wallypipelinedsoc/core/SrcAM[13]} {wallypipelinedsoc/core/SrcAM[14]} {wallypipelinedsoc/core/SrcAM[15]} {wallypipelinedsoc/core/SrcAM[16]} {wallypipelinedsoc/core/SrcAM[17]} {wallypipelinedsoc/core/SrcAM[18]} {wallypipelinedsoc/core/SrcAM[19]} {wallypipelinedsoc/core/SrcAM[20]} {wallypipelinedsoc/core/SrcAM[21]} {wallypipelinedsoc/core/SrcAM[22]} {wallypipelinedsoc/core/SrcAM[23]} {wallypipelinedsoc/core/SrcAM[24]} {wallypipelinedsoc/core/SrcAM[25]} {wallypipelinedsoc/core/SrcAM[26]} {wallypipelinedsoc/core/SrcAM[27]} {wallypipelinedsoc/core/SrcAM[28]} {wallypipelinedsoc/core/SrcAM[29]} {wallypipelinedsoc/core/SrcAM[30]} {wallypipelinedsoc/core/SrcAM[31]} {wallypipelinedsoc/core/SrcAM[32]} {wallypipelinedsoc/core/SrcAM[33]} {wallypipelinedsoc/core/SrcAM[34]} {wallypipelinedsoc/core/SrcAM[35]} {wallypipelinedsoc/core/SrcAM[36]} {wallypipelinedsoc/core/SrcAM[37]} {wallypipelinedsoc/core/SrcAM[38]} {wallypipelinedsoc/core/SrcAM[39]} {wallypipelinedsoc/core/SrcAM[40]} {wallypipelinedsoc/core/SrcAM[41]} {wallypipelinedsoc/core/SrcAM[42]} {wallypipelinedsoc/core/SrcAM[43]} {wallypipelinedsoc/core/SrcAM[44]} {wallypipelinedsoc/core/SrcAM[45]} {wallypipelinedsoc/core/SrcAM[46]} {wallypipelinedsoc/core/SrcAM[47]} {wallypipelinedsoc/core/SrcAM[48]} {wallypipelinedsoc/core/SrcAM[49]} {wallypipelinedsoc/core/SrcAM[50]} {wallypipelinedsoc/core/SrcAM[51]} {wallypipelinedsoc/core/SrcAM[52]} {wallypipelinedsoc/core/SrcAM[53]} {wallypipelinedsoc/core/SrcAM[54]} {wallypipelinedsoc/core/SrcAM[55]} {wallypipelinedsoc/core/SrcAM[56]} {wallypipelinedsoc/core/SrcAM[57]} {wallypipelinedsoc/core/SrcAM[58]} {wallypipelinedsoc/core/SrcAM[59]} {wallypipelinedsoc/core/SrcAM[60]} {wallypipelinedsoc/core/SrcAM[61]} {wallypipelinedsoc/core/SrcAM[62]} {wallypipelinedsoc/core/SrcAM[63]}]]
|
||||
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 56 [get_debug_ports u_ila_0/probe100]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe100]
|
||||
connect_debug_port u_ila_0/probe100 [get_nets [list {wallypipelinedsoc/core/ifu/PCPF[0]} {wallypipelinedsoc/core/ifu/PCPF[1]} {wallypipelinedsoc/core/ifu/PCPF[2]} {wallypipelinedsoc/core/ifu/PCPF[3]} {wallypipelinedsoc/core/ifu/PCPF[4]} {wallypipelinedsoc/core/ifu/PCPF[5]} {wallypipelinedsoc/core/ifu/PCPF[6]} {wallypipelinedsoc/core/ifu/PCPF[7]} {wallypipelinedsoc/core/ifu/PCPF[8]} {wallypipelinedsoc/core/ifu/PCPF[9]} {wallypipelinedsoc/core/ifu/PCPF[10]} {wallypipelinedsoc/core/ifu/PCPF[11]} {wallypipelinedsoc/core/ifu/PCPF[12]} {wallypipelinedsoc/core/ifu/PCPF[13]} {wallypipelinedsoc/core/ifu/PCPF[14]} {wallypipelinedsoc/core/ifu/PCPF[15]} {wallypipelinedsoc/core/ifu/PCPF[16]} {wallypipelinedsoc/core/ifu/PCPF[17]} {wallypipelinedsoc/core/ifu/PCPF[18]} {wallypipelinedsoc/core/ifu/PCPF[19]} {wallypipelinedsoc/core/ifu/PCPF[20]} {wallypipelinedsoc/core/ifu/PCPF[21]} {wallypipelinedsoc/core/ifu/PCPF[22]} {wallypipelinedsoc/core/ifu/PCPF[23]} {wallypipelinedsoc/core/ifu/PCPF[24]} {wallypipelinedsoc/core/ifu/PCPF[25]} {wallypipelinedsoc/core/ifu/PCPF[26]} {wallypipelinedsoc/core/ifu/PCPF[27]} {wallypipelinedsoc/core/ifu/PCPF[28]} {wallypipelinedsoc/core/ifu/PCPF[29]} {wallypipelinedsoc/core/ifu/PCPF[30]} {wallypipelinedsoc/core/ifu/PCPF[31]} {wallypipelinedsoc/core/ifu/PCPF[32]} {wallypipelinedsoc/core/ifu/PCPF[33]} {wallypipelinedsoc/core/ifu/PCPF[34]} {wallypipelinedsoc/core/ifu/PCPF[35]} {wallypipelinedsoc/core/ifu/PCPF[36]} {wallypipelinedsoc/core/ifu/PCPF[37]} {wallypipelinedsoc/core/ifu/PCPF[38]} {wallypipelinedsoc/core/ifu/PCPF[39]} {wallypipelinedsoc/core/ifu/PCPF[40]} {wallypipelinedsoc/core/ifu/PCPF[41]} {wallypipelinedsoc/core/ifu/PCPF[42]} {wallypipelinedsoc/core/ifu/PCPF[43]} {wallypipelinedsoc/core/ifu/PCPF[44]} {wallypipelinedsoc/core/ifu/PCPF[45]} {wallypipelinedsoc/core/ifu/PCPF[46]} {wallypipelinedsoc/core/ifu/PCPF[47]} {wallypipelinedsoc/core/ifu/PCPF[48]} {wallypipelinedsoc/core/ifu/PCPF[49]} {wallypipelinedsoc/core/ifu/PCPF[50]} {wallypipelinedsoc/core/ifu/PCPF[51]} {wallypipelinedsoc/core/ifu/PCPF[52]} {wallypipelinedsoc/core/ifu/PCPF[53]} {wallypipelinedsoc/core/ifu/PCPF[54]} {wallypipelinedsoc/core/ifu/PCPF[55]} ]]
|
||||
|
||||
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 3 [get_debug_ports u_ila_0/probe101]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe101]
|
||||
connect_debug_port u_ila_0/probe101 [get_nets [list {wallypipelinedsoc/core/ifu/bus.icache.ahbcacheinterface/AHBBuscachefsm/CurrState[0]} {wallypipelinedsoc/core/ifu/bus.icache.ahbcacheinterface/AHBBuscachefsm/CurrState[1]} {wallypipelinedsoc/core/ifu/bus.icache.ahbcacheinterface/AHBBuscachefsm/CurrState[2]} ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe102]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe102]
|
||||
connect_debug_port u_ila_0/probe102 [get_nets [list wallypipelinedsoc/core/ifu/Spill.spill/CurrState[0] ]]
|
||||
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 3 [get_debug_ports u_ila_0/probe103]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe103]
|
||||
connect_debug_port u_ila_0/probe103 [get_nets [list {wallypipelinedsoc/core/lsu/bus.dcache.ahbcacheinterface/AHBBuscachefsm/CurrState[0]} {wallypipelinedsoc/core/lsu/bus.dcache.ahbcacheinterface/AHBBuscachefsm/CurrState[1]} {wallypipelinedsoc/core/lsu/bus.dcache.ahbcacheinterface/AHBBuscachefsm/CurrState[2]} ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 7 [get_debug_ports u_ila_0/probe104]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe104]
|
||||
connect_debug_port u_ila_0/probe104 [get_nets [list {wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[1][1]} {wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[1][2]} {wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[1][3]} {wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[1][4]} {wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[1][5]} {wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[1][6]} {wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[1][7]} ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 64 [get_debug_ports u_ila_0/probe105]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe105]
|
||||
connect_debug_port u_ila_0/probe105 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[0]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[1]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[2]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[3]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[4]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[5]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[6]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[7]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[8]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[9]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[10]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[11]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[12]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[13]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[14]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[15]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[16]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[17]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[18]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[19]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[20]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[21]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[22]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[23]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[24]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[25]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[26]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[27]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[28]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[29]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[30]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[31]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[32]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[33]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[34]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[35]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[36]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[37]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[38]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[39]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[40]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[41]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[42]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[43]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[44]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[45]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[46]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[47]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[48]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[49]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[50]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[51]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[52]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[53]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[54]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[55]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[56]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[57]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[58]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[59]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[60]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[61]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[62]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[63]} ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 64 [get_debug_ports u_ila_0/probe106]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe106]
|
||||
connect_debug_port u_ila_0/probe106 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[0]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[1]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[2]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[3]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[4]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[5]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[6]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[7]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[8]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[9]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[10]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[11]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[12]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[13]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[14]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[15]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[16]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[17]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[18]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[19]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[20]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[21]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[22]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[23]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[24]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[25]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[26]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[27]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[28]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[29]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[30]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[31]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[32]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[33]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[34]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[35]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[36]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[37]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[38]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[39]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[40]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[41]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[42]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[43]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[44]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[45]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[46]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[47]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[48]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[49]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[50]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[51]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[52]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[53]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[54]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[55]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[56]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[57]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[58]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[59]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[60]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[61]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[62]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[63]} ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 64 [get_debug_ports u_ila_0/probe107]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe107]
|
||||
connect_debug_port u_ila_0/probe107 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[0]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[1]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[2]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[3]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[4]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[5]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[6]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[7]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[8]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[9]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[10]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[11]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[12]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[13]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[14]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[15]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[16]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[17]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[18]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[19]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[20]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[21]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[22]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[23]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[24]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[25]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[26]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[27]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[28]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[29]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[30]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[31]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[32]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[33]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[34]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[35]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[36]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[37]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[38]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[39]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[40]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[41]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[42]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[43]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[44]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[45]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[46]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[47]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[48]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[49]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[50]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[51]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[52]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[53]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[54]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[55]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[56]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[57]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[58]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[59]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[60]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[61]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[62]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[63]} ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe108]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe108]
|
||||
connect_debug_port u_ila_0/probe108 [get_nets [list wallypipelinedsoc/core/ieu/dp/RegWriteW]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe109]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe109]
|
||||
connect_debug_port u_ila_0/probe109 [get_nets [list {wallypipelinedsoc/core/priv.priv/CSRWriteM} ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 32 [get_debug_ports u_ila_0/probe110]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe110]
|
||||
connect_debug_port u_ila_0/probe110 [get_nets [list {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[0]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[1]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[2]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[3]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[4]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[5]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[6]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[7]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[8]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[9]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[10]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[11]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[12]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[13]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[14]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[15]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[16]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[17]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[18]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[19]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[20]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[21]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[22]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[23]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[24]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[25]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[26]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[27]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[28]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[29]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[30]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[31]} ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 64 [get_debug_ports u_ila_0/probe111]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe111]
|
||||
connect_debug_port u_ila_0/probe111 [get_nets [list {wallypipelinedsoc/core/ifu/PCNextF[0]} {wallypipelinedsoc/core/ifu/PCNextF[1]} {wallypipelinedsoc/core/ifu/PCNextF[2]} {wallypipelinedsoc/core/ifu/PCNextF[3]} {wallypipelinedsoc/core/ifu/PCNextF[4]} {wallypipelinedsoc/core/ifu/PCNextF[5]} {wallypipelinedsoc/core/ifu/PCNextF[6]} {wallypipelinedsoc/core/ifu/PCNextF[7]} {wallypipelinedsoc/core/ifu/PCNextF[8]} {wallypipelinedsoc/core/ifu/PCNextF[9]} {wallypipelinedsoc/core/ifu/PCNextF[10]} {wallypipelinedsoc/core/ifu/PCNextF[11]} {wallypipelinedsoc/core/ifu/PCNextF[12]} {wallypipelinedsoc/core/ifu/PCNextF[13]} {wallypipelinedsoc/core/ifu/PCNextF[14]} {wallypipelinedsoc/core/ifu/PCNextF[15]} {wallypipelinedsoc/core/ifu/PCNextF[16]} {wallypipelinedsoc/core/ifu/PCNextF[17]} {wallypipelinedsoc/core/ifu/PCNextF[18]} {wallypipelinedsoc/core/ifu/PCNextF[19]} {wallypipelinedsoc/core/ifu/PCNextF[20]} {wallypipelinedsoc/core/ifu/PCNextF[21]} {wallypipelinedsoc/core/ifu/PCNextF[22]} {wallypipelinedsoc/core/ifu/PCNextF[23]} {wallypipelinedsoc/core/ifu/PCNextF[24]} {wallypipelinedsoc/core/ifu/PCNextF[25]} {wallypipelinedsoc/core/ifu/PCNextF[26]} {wallypipelinedsoc/core/ifu/PCNextF[27]} {wallypipelinedsoc/core/ifu/PCNextF[28]} {wallypipelinedsoc/core/ifu/PCNextF[29]} {wallypipelinedsoc/core/ifu/PCNextF[30]} {wallypipelinedsoc/core/ifu/PCNextF[31]} {wallypipelinedsoc/core/ifu/PCNextF[32]} {wallypipelinedsoc/core/ifu/PCNextF[33]} {wallypipelinedsoc/core/ifu/PCNextF[34]} {wallypipelinedsoc/core/ifu/PCNextF[35]} {wallypipelinedsoc/core/ifu/PCNextF[36]} {wallypipelinedsoc/core/ifu/PCNextF[37]} {wallypipelinedsoc/core/ifu/PCNextF[38]} {wallypipelinedsoc/core/ifu/PCNextF[39]} {wallypipelinedsoc/core/ifu/PCNextF[40]} {wallypipelinedsoc/core/ifu/PCNextF[41]} {wallypipelinedsoc/core/ifu/PCNextF[42]} {wallypipelinedsoc/core/ifu/PCNextF[43]} {wallypipelinedsoc/core/ifu/PCNextF[44]} {wallypipelinedsoc/core/ifu/PCNextF[45]} {wallypipelinedsoc/core/ifu/PCNextF[46]} {wallypipelinedsoc/core/ifu/PCNextF[47]} {wallypipelinedsoc/core/ifu/PCNextF[48]} {wallypipelinedsoc/core/ifu/PCNextF[49]} {wallypipelinedsoc/core/ifu/PCNextF[50]} {wallypipelinedsoc/core/ifu/PCNextF[51]} {wallypipelinedsoc/core/ifu/PCNextF[52]} {wallypipelinedsoc/core/ifu/PCNextF[53]} {wallypipelinedsoc/core/ifu/PCNextF[54]} {wallypipelinedsoc/core/ifu/PCNextF[55]} {wallypipelinedsoc/core/ifu/PCNextF[56]} {wallypipelinedsoc/core/ifu/PCNextF[57]} {wallypipelinedsoc/core/ifu/PCNextF[58]} {wallypipelinedsoc/core/ifu/PCNextF[59]} {wallypipelinedsoc/core/ifu/PCNextF[60]} {wallypipelinedsoc/core/ifu/PCNextF[61]} {wallypipelinedsoc/core/ifu/PCNextF[62]} {wallypipelinedsoc/core/ifu/PCNextF[63]}]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 8 [get_debug_ports u_ila_0/probe112]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe112]
|
||||
connect_debug_port u_ila_0/probe112 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[7]} ]]
|
||||
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 8 [get_debug_ports u_ila_0/probe113]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe113]
|
||||
connect_debug_port u_ila_0/probe113 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[7]} ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 8 [get_debug_ports u_ila_0/probe114]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe114]
|
||||
connect_debug_port u_ila_0/probe114 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[7]} ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 8 [get_debug_ports u_ila_0/probe115]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe115]
|
||||
connect_debug_port u_ila_0/probe115 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[7]} ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 2 [get_debug_ports u_ila_0/probe116]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe116]
|
||||
connect_debug_port u_ila_0/probe116 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/txstate[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txstate[1]} ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe117]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe117]
|
||||
connect_debug_port u_ila_0/probe117 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csri/MExtInt}]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe118]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe118]
|
||||
connect_debug_port u_ila_0/probe118 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csri/SExtInt} ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe119]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe119]
|
||||
connect_debug_port u_ila_0/probe119 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csri/MTimerInt} ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe120]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe120]
|
||||
connect_debug_port u_ila_0/probe120 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csri/MSwInt} ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 11 [get_debug_ports u_ila_0/probe121]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe121]
|
||||
connect_debug_port u_ila_0/probe121 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[7]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[8]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[9]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[10]} ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe122]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe122]
|
||||
connect_debug_port u_ila_0/probe122 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxparityerr} ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 2 [get_debug_ports u_ila_0/probe123]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe123]
|
||||
connect_debug_port u_ila_0/probe123 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxstate[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxstate[1]} ]]
|
||||
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 12 [get_debug_ports u_ila_0/probe124]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe124]
|
||||
connect_debug_port u_ila_0/probe124 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[11]} ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 12 [get_debug_ports u_ila_0/probe125]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe125]
|
||||
connect_debug_port u_ila_0/probe125 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[11]} ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 64 [get_debug_ports u_ila_0/probe126]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe126]
|
||||
connect_debug_port u_ila_0/probe126 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[63]} ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 64 [get_debug_ports u_ila_0/probe127]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe127]
|
||||
connect_debug_port u_ila_0/probe127 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[63]} ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 64 [get_debug_ports u_ila_0/probe128]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe128]
|
||||
connect_debug_port u_ila_0/probe128 [get_nets [list {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[0]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[1]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[2]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[3]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[4]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[5]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[6]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[7]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[8]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[9]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[10]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[11]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[12]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[13]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[14]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[15]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[16]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[17]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[18]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[19]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[20]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[21]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[22]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[23]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[24]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[25]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[26]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[27]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[28]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[29]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[30]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[31]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[32]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[33]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[34]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[35]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[36]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[37]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[38]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[39]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[40]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[41]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[42]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[43]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[44]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[45]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[46]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[47]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[48]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[49]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[50]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[51]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[52]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[53]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[54]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[55]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[56]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[57]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[58]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[59]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[60]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[61]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[62]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[63]} ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 64 [get_debug_ports u_ila_0/probe129]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe129]
|
||||
connect_debug_port u_ila_0/probe129 [get_nets [list {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[0]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[1]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[2]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[3]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[4]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[5]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[6]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[7]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[8]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[9]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[10]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[11]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[12]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[13]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[14]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[15]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[16]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[17]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[18]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[19]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[20]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[21]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[22]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[23]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[24]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[25]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[26]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[27]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[28]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[29]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[30]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[31]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[32]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[33]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[34]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[35]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[36]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[37]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[38]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[39]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[40]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[41]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[42]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[43]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[44]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[45]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[46]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[47]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[48]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[49]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[50]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[51]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[52]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[53]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[54]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[55]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[56]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[57]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[58]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[59]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[60]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[61]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[62]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[63]} ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 64 [get_debug_ports u_ila_0/probe130]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe130]
|
||||
connect_debug_port u_ila_0/probe130 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[63]} ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 8 [get_debug_ports u_ila_0/probe131]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe131]
|
||||
connect_debug_port u_ila_0/probe131 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[7]} ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 3 [get_debug_ports u_ila_0/probe132]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe132]
|
||||
connect_debug_port u_ila_0/probe132 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/intrID[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/intrID[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/intrID[2]} ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe133]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe133]
|
||||
connect_debug_port u_ila_0/probe133 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxdataavailintr} ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe134]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe134]
|
||||
connect_debug_port u_ila_0/probe134 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/fifoenabled} ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe135]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe135]
|
||||
connect_debug_port u_ila_0/probe135 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifotriggered} ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 4 [get_debug_ports u_ila_0/probe136]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe136]
|
||||
connect_debug_port u_ila_0/probe136 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifoentries[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifoentries[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifoentries[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifoentries[3]} ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe137]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe137]
|
||||
connect_debug_port u_ila_0/probe137 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxdataready} ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 64 [get_debug_ports u_ila_0/probe138]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe138]
|
||||
connect_debug_port u_ila_0/probe138 [get_nets [list {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[0]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[1]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[2]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[3]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[4]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[5]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[6]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[7]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[8]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[9]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[10]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[11]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[12]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[13]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[14]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[15]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[16]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[17]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[18]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[19]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[20]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[21]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[22]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[23]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[24]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[25]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[26]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[27]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[28]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[29]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[30]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[31]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[32]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[33]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[34]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[35]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[36]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[37]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[38]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[39]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[40]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[41]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[42]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[43]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[44]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[45]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[46]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[47]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[48]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[49]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[50]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[51]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[52]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[53]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[54]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[55]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[56]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[57]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[58]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[59]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[60]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[61]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[62]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[63]} ]]
|
||||
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 4 [get_debug_ports u_ila_0/probe139]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe139]
|
||||
connect_debug_port u_ila_0/probe139 [get_nets [list {m_axi_awid[0]} {m_axi_awid[1]} {m_axi_awid[2]} {m_axi_awid[3]} ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 8 [get_debug_ports u_ila_0/probe140]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe140]
|
||||
connect_debug_port u_ila_0/probe140 [get_nets [list {m_axi_awlen[0]} {m_axi_awlen[1]} {m_axi_awlen[2]} {m_axi_awlen[3]} {m_axi_awlen[4]} {m_axi_awlen[5]} {m_axi_awlen[6]} {m_axi_awlen[7]} ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 3 [get_debug_ports u_ila_0/probe141]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe141]
|
||||
connect_debug_port u_ila_0/probe141 [get_nets [list {m_axi_awsize[0]} {m_axi_awsize[1]} {m_axi_awsize[2]} ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 2 [get_debug_ports u_ila_0/probe142]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe142]
|
||||
connect_debug_port u_ila_0/probe142 [get_nets [list {m_axi_awburst[0]} {m_axi_awburst[1]} ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 4 [get_debug_ports u_ila_0/probe143]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe143]
|
||||
connect_debug_port u_ila_0/probe143 [get_nets [list {m_axi_awcache[0]} {m_axi_awcache[1]} {m_axi_awcache[2]} {m_axi_awcache[3]} ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 31 [get_debug_ports u_ila_0/probe144]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe144]
|
||||
connect_debug_port u_ila_0/probe144 [get_nets [list {m_axi_awaddr[0]} {m_axi_awaddr[1]} {m_axi_awaddr[2]} {m_axi_awaddr[3]} {m_axi_awaddr[4]} {m_axi_awaddr[5]} {m_axi_awaddr[6]} {m_axi_awaddr[7]} {m_axi_awaddr[8]} {m_axi_awaddr[9]} {m_axi_awaddr[10]} {m_axi_awaddr[11]} {m_axi_awaddr[12]} {m_axi_awaddr[13]} {m_axi_awaddr[14]} {m_axi_awaddr[15]} {m_axi_awaddr[16]} {m_axi_awaddr[17]} {m_axi_awaddr[18]} {m_axi_awaddr[19]} {m_axi_awaddr[20]} {m_axi_awaddr[21]} {m_axi_awaddr[22]} {m_axi_awaddr[23]} {m_axi_awaddr[24]} {m_axi_awaddr[25]} {m_axi_awaddr[26]} {m_axi_awaddr[27]} {m_axi_awaddr[28]} {m_axi_awaddr[29]} {m_axi_awaddr[30]} ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 3 [get_debug_ports u_ila_0/probe145]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe145]
|
||||
connect_debug_port u_ila_0/probe145 [get_nets [list {m_axi_awprot[0]} {m_axi_awprot[1]} {m_axi_awprot[2]} ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe146]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe146]
|
||||
connect_debug_port u_ila_0/probe146 [get_nets [list {m_axi_awvalid}]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe147]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe147]
|
||||
connect_debug_port u_ila_0/probe147 [get_nets [list {m_axi_awready}]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe148]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe148]
|
||||
connect_debug_port u_ila_0/probe148 [get_nets [list {m_axi_awlock}]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 64 [get_debug_ports u_ila_0/probe149]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe149]
|
||||
connect_debug_port u_ila_0/probe149 [get_nets [list {m_axi_wdata[0]} {m_axi_wdata[1]} {m_axi_wdata[2]} {m_axi_wdata[3]} {m_axi_wdata[4]} {m_axi_wdata[5]} {m_axi_wdata[6]} {m_axi_wdata[7]} {m_axi_wdata[8]} {m_axi_wdata[9]} {m_axi_wdata[10]} {m_axi_wdata[11]} {m_axi_wdata[12]} {m_axi_wdata[13]} {m_axi_wdata[14]} {m_axi_wdata[15]} {m_axi_wdata[16]} {m_axi_wdata[17]} {m_axi_wdata[18]} {m_axi_wdata[19]} {m_axi_wdata[20]} {m_axi_wdata[21]} {m_axi_wdata[22]} {m_axi_wdata[23]} {m_axi_wdata[24]} {m_axi_wdata[25]} {m_axi_wdata[26]} {m_axi_wdata[27]} {m_axi_wdata[28]} {m_axi_wdata[29]} {m_axi_wdata[30]} {m_axi_wdata[31]} {m_axi_wdata[32]} {m_axi_wdata[33]} {m_axi_wdata[34]} {m_axi_wdata[35]} {m_axi_wdata[36]} {m_axi_wdata[37]} {m_axi_wdata[38]} {m_axi_wdata[39]} {m_axi_wdata[40]} {m_axi_wdata[41]} {m_axi_wdata[42]} {m_axi_wdata[43]} {m_axi_wdata[44]} {m_axi_wdata[45]} {m_axi_wdata[46]} {m_axi_wdata[47]} {m_axi_wdata[48]} {m_axi_wdata[49]} {m_axi_wdata[50]} {m_axi_wdata[51]} {m_axi_wdata[52]} {m_axi_wdata[53]} {m_axi_wdata[54]} {m_axi_wdata[55]} {m_axi_wdata[56]} {m_axi_wdata[57]} {m_axi_wdata[58]} {m_axi_wdata[59]} {m_axi_wdata[60]} {m_axi_wdata[61]} {m_axi_wdata[62]} {m_axi_wdata[63]} ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 8 [get_debug_ports u_ila_0/probe150]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe150]
|
||||
connect_debug_port u_ila_0/probe150 [get_nets [list {m_axi_wstrb[0]} {m_axi_wstrb[1]} {m_axi_wstrb[2]} {m_axi_wstrb[3]} {m_axi_wstrb[4]} {m_axi_wstrb[5]} {m_axi_wstrb[6]} {m_axi_wstrb[7]} ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe151]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe151]
|
||||
connect_debug_port u_ila_0/probe151 [get_nets [list {m_axi_wlast}]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe152]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe152]
|
||||
connect_debug_port u_ila_0/probe152 [get_nets [list {m_axi_wvalid}]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe153]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe153]
|
||||
connect_debug_port u_ila_0/probe153 [get_nets [list {m_axi_wready}]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 4 [get_debug_ports u_ila_0/probe154]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe154]
|
||||
connect_debug_port u_ila_0/probe154 [get_nets [list {m_axi_bid[0]} {m_axi_bid[1]} {m_axi_bid[2]} {m_axi_bid[3]} ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 2 [get_debug_ports u_ila_0/probe155]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe155]
|
||||
connect_debug_port u_ila_0/probe155 [get_nets [list {m_axi_bresp[0]} {m_axi_bresp[1]} ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe156]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe156]
|
||||
connect_debug_port u_ila_0/probe156 [get_nets [list {m_axi_bvalid}]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe157]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe157]
|
||||
connect_debug_port u_ila_0/probe157 [get_nets [list {m_axi_bready}]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 4 [get_debug_ports u_ila_0/probe158]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe158]
|
||||
connect_debug_port u_ila_0/probe158 [get_nets [list {m_axi_arid[0]} {m_axi_arid[1]} {m_axi_arid[2]} {m_axi_arid[3]} ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 8 [get_debug_ports u_ila_0/probe159]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe159]
|
||||
connect_debug_port u_ila_0/probe159 [get_nets [list {m_axi_arlen[0]} {m_axi_arlen[1]} {m_axi_arlen[2]} {m_axi_arlen[3]} {m_axi_arlen[4]} {m_axi_arlen[5]} {m_axi_arlen[6]} {m_axi_arlen[7]} ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 3 [get_debug_ports u_ila_0/probe160]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe160]
|
||||
connect_debug_port u_ila_0/probe160 [get_nets [list {m_axi_arsize[0]} {m_axi_arsize[1]} {m_axi_arsize[2]} ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 2 [get_debug_ports u_ila_0/probe161]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe161]
|
||||
connect_debug_port u_ila_0/probe161 [get_nets [list {m_axi_arburst[0]} {m_axi_arburst[1]} ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 3 [get_debug_ports u_ila_0/probe162]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe162]
|
||||
connect_debug_port u_ila_0/probe162 [get_nets [list {m_axi_arprot[0]} {m_axi_arprot[1]} {m_axi_arprot[2]} ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 4 [get_debug_ports u_ila_0/probe163]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe163]
|
||||
connect_debug_port u_ila_0/probe163 [get_nets [list {m_axi_arcache[0]} {m_axi_arcache[1]} {m_axi_arcache[2]} {m_axi_arcache[3]} ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe164]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe164]
|
||||
connect_debug_port u_ila_0/probe164 [get_nets [list {m_axi_arvalid}]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 31 [get_debug_ports u_ila_0/probe165]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe165]
|
||||
connect_debug_port u_ila_0/probe165 [get_nets [list {m_axi_araddr[0]} {m_axi_araddr[1]} {m_axi_araddr[2]} {m_axi_araddr[3]} {m_axi_araddr[4]} {m_axi_araddr[5]} {m_axi_araddr[6]} {m_axi_araddr[7]} {m_axi_araddr[8]} {m_axi_araddr[9]} {m_axi_araddr[10]} {m_axi_araddr[11]} {m_axi_araddr[12]} {m_axi_araddr[13]} {m_axi_araddr[14]} {m_axi_araddr[15]} {m_axi_araddr[16]} {m_axi_araddr[17]} {m_axi_araddr[18]} {m_axi_araddr[19]} {m_axi_araddr[20]} {m_axi_araddr[21]} {m_axi_araddr[22]} {m_axi_araddr[23]} {m_axi_araddr[24]} {m_axi_araddr[25]} {m_axi_araddr[26]} {m_axi_araddr[27]} {m_axi_araddr[28]} {m_axi_araddr[29]} {m_axi_araddr[30]} ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe166]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe166]
|
||||
connect_debug_port u_ila_0/probe166 [get_nets [list {m_axi_arlock}]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe167]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe167]
|
||||
connect_debug_port u_ila_0/probe167 [get_nets [list {m_axi_arready}]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 4 [get_debug_ports u_ila_0/probe168]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe168]
|
||||
connect_debug_port u_ila_0/probe168 [get_nets [list {m_axi_rid[0]} {m_axi_rid[1]} {m_axi_rid[2]} {m_axi_rid[3]} ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 64 [get_debug_ports u_ila_0/probe169]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe169]
|
||||
connect_debug_port u_ila_0/probe169 [get_nets [list {m_axi_rdata[0]} {m_axi_rdata[1]} {m_axi_rdata[2]} {m_axi_rdata[3]} {m_axi_rdata[4]} {m_axi_rdata[5]} {m_axi_rdata[6]} {m_axi_rdata[7]} {m_axi_rdata[8]} {m_axi_rdata[9]} {m_axi_rdata[10]} {m_axi_rdata[11]} {m_axi_rdata[12]} {m_axi_rdata[13]} {m_axi_rdata[14]} {m_axi_rdata[15]} {m_axi_rdata[16]} {m_axi_rdata[17]} {m_axi_rdata[18]} {m_axi_rdata[19]} {m_axi_rdata[20]} {m_axi_rdata[21]} {m_axi_rdata[22]} {m_axi_rdata[23]} {m_axi_rdata[24]} {m_axi_rdata[25]} {m_axi_rdata[26]} {m_axi_rdata[27]} {m_axi_rdata[28]} {m_axi_rdata[29]} {m_axi_rdata[30]} {m_axi_rdata[31]} {m_axi_rdata[32]} {m_axi_rdata[33]} {m_axi_rdata[34]} {m_axi_rdata[35]} {m_axi_rdata[36]} {m_axi_rdata[37]} {m_axi_rdata[38]} {m_axi_rdata[39]} {m_axi_rdata[40]} {m_axi_rdata[41]} {m_axi_rdata[42]} {m_axi_rdata[43]} {m_axi_rdata[44]} {m_axi_rdata[45]} {m_axi_rdata[46]} {m_axi_rdata[47]} {m_axi_rdata[48]} {m_axi_rdata[49]} {m_axi_rdata[50]} {m_axi_rdata[51]} {m_axi_rdata[52]} {m_axi_rdata[53]} {m_axi_rdata[54]} {m_axi_rdata[55]} {m_axi_rdata[56]} {m_axi_rdata[57]} {m_axi_rdata[58]} {m_axi_rdata[59]} {m_axi_rdata[60]} {m_axi_rdata[61]} {m_axi_rdata[62]} {m_axi_rdata[63]} ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 2 [get_debug_ports u_ila_0/probe170]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe170]
|
||||
connect_debug_port u_ila_0/probe170 [get_nets [list {m_axi_rresp[0]} {m_axi_rresp[1]} ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe171]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe171]
|
||||
connect_debug_port u_ila_0/probe171 [get_nets [list {m_axi_rvalid}]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe172]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe172]
|
||||
connect_debug_port u_ila_0/probe172 [get_nets [list {m_axi_rlast}]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe173]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe173]
|
||||
connect_debug_port u_ila_0/probe173 [get_nets [list {m_axi_rready}]]
|
||||
@ -1,130 +0,0 @@
|
||||
lsu/lsu.sv: logic IEUAdrM
|
||||
lsu/lsu.sv: logic WriteDataM
|
||||
lsu/lsu.sv: logic LSUHADDR
|
||||
lsu/lsu.sv: logic HRDATA
|
||||
lsu/lsu.sv: logic LSUHWDATA
|
||||
lsu/lsu.sv: logic LSUHREADY
|
||||
lsu/lsu.sv: logic LSUHWRITE
|
||||
lsu/lsu.sv: logic LSUHSIZE
|
||||
lsu/lsu.sv: logic LSUHBURST
|
||||
lsu/lsu.sv: logic LSUHTRANS
|
||||
lsu/lsu.sv: logic LSUHWSTRB
|
||||
lsu/lsu.sv: logic IHAdrM
|
||||
ieu/regfile.sv: logic rf
|
||||
ieu/datapath.sv: logic RegWriteW
|
||||
hazard/hazard.sv: logic BPPredWrongE
|
||||
hazard/hazard.sv: logic LoadStallD
|
||||
hazard/hazard.sv: logic LSUStallM
|
||||
hazard/hazard.sv: logic FCvtIntStallD
|
||||
hazard/hazard.sv: logic DivBusyE
|
||||
hazard/hazard.sv: logic EcallFaultM
|
||||
hazard/hazard.sv: logic WFIStallM
|
||||
hazard/hazard.sv: logic StallF
|
||||
hazard/hazard.sv: logic FlushD
|
||||
cache/cachefsm.sv: statetype CurrState
|
||||
wally/wallypipelinedcore.sv: logic TrapM
|
||||
wally/wallypipelinedcore.sv: logic SrcAM
|
||||
wally/wallypipelinedcore.sv: logic InstrM
|
||||
wally/wallypipelinedcore.sv: logic PCM
|
||||
wally/wallypipelinedcore.sv: logic MemRWM
|
||||
wally/wallypipelinedcore.sv: logic InstrValidM
|
||||
wally/wallypipelinedcore.sv: logic WriteDataM
|
||||
wally/wallypipelinedcore.sv: logic IEUAdrM
|
||||
ifu/spill.sv: statetype CurrState
|
||||
ifu/ifu.sv: logic IFUStallF
|
||||
ifu/ifu.sv: logic IFUHADDR
|
||||
ifu/ifu.sv: logic HRDATA
|
||||
ifu/ifu.sv: logic IFUHREADY
|
||||
ifu/ifu.sv: logic IFUHWRITE
|
||||
ifu/ifu.sv: logic IFUHSIZE
|
||||
ifu/ifu.sv: logic IFUHBURST
|
||||
ifu/ifu.sv: logic IFUHTRANS
|
||||
ifu/ifu.sv: logic PCF
|
||||
ifu/ifu.sv: logic PCNextF
|
||||
ifu/ifu.sv: logic PCPF
|
||||
ifu/ifu.sv: logic PostSpillInstrRawF
|
||||
mmu/hptw.sv: logic ITLBWriteF
|
||||
mmu/hptw.sv: statetype WalkerState
|
||||
privileged/csrs.sv: logic CSRSReadValM
|
||||
privileged/csrs.sv: logic SEPC_REGW
|
||||
privileged/csrs.sv: logic MIP_REGW
|
||||
privileged/csrs.sv: logic SSCRATCH_REGW
|
||||
privileged/csrs.sv: logic SCAUSE_REGW
|
||||
privileged/csr.sv: logic CSRReadValM
|
||||
privileged/csr.sv: logic CSRSrcM
|
||||
privileged/csr.sv: logic CSRWriteValM
|
||||
privileged/csr.sv: logic MSTATUS_REGW
|
||||
privileged/trap.sv: logic InstrMisalignedFaultM
|
||||
privileged/trap.sv: logic BreakpointFaultM
|
||||
privileged/trap.sv: logic LoadAccessFaultM
|
||||
privileged/trap.sv: logic LoadPageFaultM
|
||||
privileged/trap.sv: logic mretM
|
||||
privileged/trap.sv: logic MIP_REGW
|
||||
privileged/trap.sv: logic PendingIntsM
|
||||
privileged/privileged.sv: logic CSRReadM
|
||||
privileged/privileged.sv: logic InterruptM
|
||||
privileged/csrc.sv: logic HPMCOUNTER_REGW
|
||||
privileged/csri.sv: logic MExtInt
|
||||
privileged/csri.sv: logic MIP_REGW_writeabl
|
||||
privileged/csrm.sv: logic MIP_REGW
|
||||
privileged/csrm.sv: logic MEPC_REGW
|
||||
privileged/csrm.sv: logic MEDELEG_REGW
|
||||
privileged/csrm.sv: logic MIDELEG_REGW
|
||||
privileged/csrm.sv: logic MSCRATCH_REGW
|
||||
privileged/csrm.sv: logic MCAUSE_REGW
|
||||
uncore/uart_apb.sv: logic SIN
|
||||
uncore/uart_apb.sv: logic SOUT
|
||||
uncore/uart_apb.sv: logic OUT1b
|
||||
uncore/uartPC16550D.sv: logic RBR
|
||||
uncore/uartPC16550D.sv: logic FCR
|
||||
uncore/uartPC16550D.sv: logic IER
|
||||
uncore/uartPC16550D.sv: logic MCR
|
||||
uncore/uartPC16550D.sv: logic baudpulse
|
||||
uncore/uartPC16550D.sv: statetype rxstate
|
||||
uncore/uartPC16550D.sv: logic rxfifo
|
||||
uncore/uartPC16550D.sv: logic txfifo
|
||||
uncore/uartPC16550D.sv: logic rxfifohead
|
||||
uncore/uartPC16550D.sv: logic rxfifoentries
|
||||
uncore/uartPC16550D.sv: logic RXBR
|
||||
uncore/uartPC16550D.sv: logic rxtimeoutcnt
|
||||
uncore/uartPC16550D.sv: logic rxparityerr
|
||||
uncore/uartPC16550D.sv: logic rxdataready
|
||||
uncore/uartPC16550D.sv: logic rxfifoempty
|
||||
uncore/uartPC16550D.sv: logic rxdata
|
||||
uncore/uartPC16550D.sv: logic RXerrbit
|
||||
uncore/uartPC16550D.sv: logic rxfullbitunwrapped
|
||||
uncore/uartPC16550D.sv: logic txdata
|
||||
uncore/uartPC16550D.sv: logic txnextbit
|
||||
uncore/uartPC16550D.sv: logic txfifoempty
|
||||
uncore/uartPC16550D.sv: logic fifoenabled
|
||||
uncore/uartPC16550D.sv: logic RXerr
|
||||
uncore/uartPC16550D.sv: logic THRE
|
||||
uncore/uartPC16550D.sv: logic rxdataavailintr
|
||||
uncore/uartPC16550D.sv: logic intrID
|
||||
uncore/plic_apb.sv: logic MExtInt
|
||||
uncore/plic_apb.sv: logic Din
|
||||
uncore/plic_apb.sv: logic requests
|
||||
uncore/plic_apb.sv: logic intPriority
|
||||
uncore/plic_apb.sv: logic intInProgress
|
||||
uncore/plic_apb.sv: logic intThreshold
|
||||
uncore/plic_apb.sv: logic intEn
|
||||
uncore/plic_apb.sv: logic intClaim
|
||||
uncore/plic_apb.sv: logic irqMatrix
|
||||
uncore/plic_apb.sv: logic priorities_with_irqs
|
||||
uncore/plic_apb.sv: logic max_priority_with_irqs
|
||||
uncore/plic_apb.sv: logic irqs_at_max_priority
|
||||
uncore/plic_apb.sv: logic threshMask
|
||||
uncore/clint_apb.sv: logic MTIME
|
||||
uncore/clint_apb.sv: logic MTIMECMP
|
||||
ebu/ebu.sv: logic HCLK
|
||||
ebu/ebu.sv: logic HREADY
|
||||
ebu/ebu.sv: logic HRESP
|
||||
ebu/ebu.sv: logic HADDR
|
||||
ebu/ebu.sv: logic HWRITE
|
||||
ebu/ebu.sv: logic HSIZE
|
||||
ebu/ebu.sv: logic HBURST
|
||||
ebu/ebu.sv: logic HPROT
|
||||
ebu/ebu.sv: logic HTRANS
|
||||
ebu/ebu.sv: logic HMASTLOC
|
||||
ebu/buscachefsm.sv: busstatetype CurrState
|
||||
ebu/busfsm.sv: busstatetype CurrState
|
||||
@ -1,138 +0,0 @@
|
||||
create_debug_core u_ila_0 ila
|
||||
|
||||
|
||||
|
||||
|
||||
set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_0]
|
||||
set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
|
||||
set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
|
||||
set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
|
||||
set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
|
||||
set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
|
||||
set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
|
||||
set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
|
||||
startgroup
|
||||
set_property C_EN_STRG_QUAL true [get_debug_cores u_ila_0 ]
|
||||
set_property C_ADV_TRIGGER true [get_debug_cores u_ila_0 ]
|
||||
set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0 ]
|
||||
set_property ALL_PROBE_SAME_MU_CNT 4 [get_debug_cores u_ila_0 ]
|
||||
endgroup
|
||||
connect_debug_port u_ila_0/clk [get_nets CPUCLK]
|
||||
|
||||
set_property port_width 64 [get_debug_ports u_ila_0/probe0]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
|
||||
connect_debug_port u_ila_0/probe0 [get_nets [list {wallypipelinedsoc/core/PCM[0]} {wallypipelinedsoc/core/PCM[1]} {wallypipelinedsoc/core/PCM[2]} {wallypipelinedsoc/core/PCM[3]} {wallypipelinedsoc/core/PCM[4]} {wallypipelinedsoc/core/PCM[5]} {wallypipelinedsoc/core/PCM[6]} {wallypipelinedsoc/core/PCM[7]} {wallypipelinedsoc/core/PCM[8]} {wallypipelinedsoc/core/PCM[9]} {wallypipelinedsoc/core/PCM[10]} {wallypipelinedsoc/core/PCM[11]} {wallypipelinedsoc/core/PCM[12]} {wallypipelinedsoc/core/PCM[13]} {wallypipelinedsoc/core/PCM[14]} {wallypipelinedsoc/core/PCM[15]} {wallypipelinedsoc/core/PCM[16]} {wallypipelinedsoc/core/PCM[17]} {wallypipelinedsoc/core/PCM[18]} {wallypipelinedsoc/core/PCM[19]} {wallypipelinedsoc/core/PCM[20]} {wallypipelinedsoc/core/PCM[21]} {wallypipelinedsoc/core/PCM[22]} {wallypipelinedsoc/core/PCM[23]} {wallypipelinedsoc/core/PCM[24]} {wallypipelinedsoc/core/PCM[25]} {wallypipelinedsoc/core/PCM[26]} {wallypipelinedsoc/core/PCM[27]} {wallypipelinedsoc/core/PCM[28]} {wallypipelinedsoc/core/PCM[29]} {wallypipelinedsoc/core/PCM[30]} {wallypipelinedsoc/core/PCM[31]} {wallypipelinedsoc/core/PCM[32]} {wallypipelinedsoc/core/PCM[33]} {wallypipelinedsoc/core/PCM[34]} {wallypipelinedsoc/core/PCM[35]} {wallypipelinedsoc/core/PCM[36]} {wallypipelinedsoc/core/PCM[37]} {wallypipelinedsoc/core/PCM[38]} {wallypipelinedsoc/core/PCM[39]} {wallypipelinedsoc/core/PCM[40]} {wallypipelinedsoc/core/PCM[41]} {wallypipelinedsoc/core/PCM[42]} {wallypipelinedsoc/core/PCM[43]} {wallypipelinedsoc/core/PCM[44]} {wallypipelinedsoc/core/PCM[45]} {wallypipelinedsoc/core/PCM[46]} {wallypipelinedsoc/core/PCM[47]} {wallypipelinedsoc/core/PCM[48]} {wallypipelinedsoc/core/PCM[49]} {wallypipelinedsoc/core/PCM[50]} {wallypipelinedsoc/core/PCM[51]} {wallypipelinedsoc/core/PCM[52]} {wallypipelinedsoc/core/PCM[53]} {wallypipelinedsoc/core/PCM[54]} {wallypipelinedsoc/core/PCM[55]} {wallypipelinedsoc/core/PCM[56]} {wallypipelinedsoc/core/PCM[57]} {wallypipelinedsoc/core/PCM[58]} {wallypipelinedsoc/core/PCM[59]} {wallypipelinedsoc/core/PCM[60]} {wallypipelinedsoc/core/PCM[61]} {wallypipelinedsoc/core/PCM[62]} {wallypipelinedsoc/core/PCM[63]} ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe1]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
|
||||
connect_debug_port u_ila_0/probe1 [get_nets [list wallypipelinedsoc/core/TrapM ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe2]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
|
||||
connect_debug_port u_ila_0/probe2 [get_nets [list wallypipelinedsoc/core/InstrValidM ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 32 [get_debug_ports u_ila_0/probe3]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
|
||||
connect_debug_port u_ila_0/probe3 [get_nets [list {wallypipelinedsoc/core/InstrM[0]} {wallypipelinedsoc/core/InstrM[1]} {wallypipelinedsoc/core/InstrM[2]} {wallypipelinedsoc/core/InstrM[3]} {wallypipelinedsoc/core/InstrM[4]} {wallypipelinedsoc/core/InstrM[5]} {wallypipelinedsoc/core/InstrM[6]} {wallypipelinedsoc/core/InstrM[7]} {wallypipelinedsoc/core/InstrM[8]} {wallypipelinedsoc/core/InstrM[9]} {wallypipelinedsoc/core/InstrM[10]} {wallypipelinedsoc/core/InstrM[11]} {wallypipelinedsoc/core/InstrM[12]} {wallypipelinedsoc/core/InstrM[13]} {wallypipelinedsoc/core/InstrM[14]} {wallypipelinedsoc/core/InstrM[15]} {wallypipelinedsoc/core/InstrM[16]} {wallypipelinedsoc/core/InstrM[17]} {wallypipelinedsoc/core/InstrM[18]} {wallypipelinedsoc/core/InstrM[19]} {wallypipelinedsoc/core/InstrM[20]} {wallypipelinedsoc/core/InstrM[21]} {wallypipelinedsoc/core/InstrM[22]} {wallypipelinedsoc/core/InstrM[23]} {wallypipelinedsoc/core/InstrM[24]} {wallypipelinedsoc/core/InstrM[25]} {wallypipelinedsoc/core/InstrM[26]} {wallypipelinedsoc/core/InstrM[27]} {wallypipelinedsoc/core/InstrM[28]} {wallypipelinedsoc/core/InstrM[29]} {wallypipelinedsoc/core/InstrM[30]} {wallypipelinedsoc/core/InstrM[31]} ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 32 [get_debug_ports u_ila_0/probe4]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
|
||||
connect_debug_port u_ila_0/probe4 [get_nets [list {wallypipelinedsoc/core/lsu/LSUHADDR[0]} {wallypipelinedsoc/core/lsu/LSUHADDR[1]} {wallypipelinedsoc/core/lsu/LSUHADDR[2]} {wallypipelinedsoc/core/lsu/LSUHADDR[3]} {wallypipelinedsoc/core/lsu/LSUHADDR[4]} {wallypipelinedsoc/core/lsu/LSUHADDR[5]} {wallypipelinedsoc/core/lsu/LSUHADDR[6]} {wallypipelinedsoc/core/lsu/LSUHADDR[7]} {wallypipelinedsoc/core/lsu/LSUHADDR[8]} {wallypipelinedsoc/core/lsu/LSUHADDR[9]} {wallypipelinedsoc/core/lsu/LSUHADDR[10]} {wallypipelinedsoc/core/lsu/LSUHADDR[11]} {wallypipelinedsoc/core/lsu/LSUHADDR[12]} {wallypipelinedsoc/core/lsu/LSUHADDR[13]} {wallypipelinedsoc/core/lsu/LSUHADDR[14]} {wallypipelinedsoc/core/lsu/LSUHADDR[15]} {wallypipelinedsoc/core/lsu/LSUHADDR[16]} {wallypipelinedsoc/core/lsu/LSUHADDR[17]} {wallypipelinedsoc/core/lsu/LSUHADDR[18]} {wallypipelinedsoc/core/lsu/LSUHADDR[19]} {wallypipelinedsoc/core/lsu/LSUHADDR[20]} {wallypipelinedsoc/core/lsu/LSUHADDR[21]} {wallypipelinedsoc/core/lsu/LSUHADDR[22]} {wallypipelinedsoc/core/lsu/LSUHADDR[23]} {wallypipelinedsoc/core/lsu/LSUHADDR[24]} {wallypipelinedsoc/core/lsu/LSUHADDR[25]} {wallypipelinedsoc/core/lsu/LSUHADDR[26]} {wallypipelinedsoc/core/lsu/LSUHADDR[27]} {wallypipelinedsoc/core/lsu/LSUHADDR[28]} {wallypipelinedsoc/core/lsu/LSUHADDR[29]} {wallypipelinedsoc/core/lsu/LSUHADDR[30]} {wallypipelinedsoc/core/lsu/LSUHADDR[31]} ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe5]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
|
||||
connect_debug_port u_ila_0/probe5 [get_nets [list wallypipelinedsoc/core/lsu/LSUHREADY ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 28 [get_debug_ports u_ila_0/probe6]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
|
||||
connect_debug_port u_ila_0/probe6 [get_nets [list {m_axi_araddr[0]} {m_axi_araddr[1]} {m_axi_araddr[2]} {m_axi_araddr[3]} {m_axi_araddr[4]} {m_axi_araddr[5]} {m_axi_araddr[6]} {m_axi_araddr[7]} {m_axi_araddr[8]} {m_axi_araddr[9]} {m_axi_araddr[10]} {m_axi_araddr[11]} {m_axi_araddr[12]} {m_axi_araddr[13]} {m_axi_araddr[14]} {m_axi_araddr[15]} {m_axi_araddr[16]} {m_axi_araddr[17]} {m_axi_araddr[18]} {m_axi_araddr[19]} {m_axi_araddr[20]} {m_axi_araddr[21]} {m_axi_araddr[22]} {m_axi_araddr[23]} {m_axi_araddr[24]} {m_axi_araddr[25]} {m_axi_araddr[26]} {m_axi_araddr[27]} ]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe7]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7]
|
||||
connect_debug_port u_ila_0/probe7 [get_nets [list {m_axi_arready}]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe8]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8]
|
||||
connect_debug_port u_ila_0/probe8 [get_nets [list {m_axi_arvalid}]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe9]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9]
|
||||
connect_debug_port u_ila_0/probe9 [get_nets [list {c0_init_calib_complete}]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe10]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10]
|
||||
connect_debug_port u_ila_0/probe10 [get_nets [list {ui_clk_sync_rst}]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe11]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11]
|
||||
connect_debug_port u_ila_0/probe11 [get_nets [list {mmcm_locked}]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe12]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12]
|
||||
connect_debug_port u_ila_0/probe12 [get_nets [list {m_axi_awvalid}]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe13]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13]
|
||||
connect_debug_port u_ila_0/probe13 [get_nets [list {m_axi_awready}]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe14]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe14]
|
||||
connect_debug_port u_ila_0/probe14 [get_nets [list {BUS_axi_arvalid}]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe15]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe15]
|
||||
connect_debug_port u_ila_0/probe15 [get_nets [list {BUS_axi_awready}]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe16]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe16]
|
||||
connect_debug_port u_ila_0/probe16 [get_nets [list {BUS_axi_arvalid}]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe17]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe17]
|
||||
connect_debug_port u_ila_0/probe17 [get_nets [list {BUS_axi_arready}]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe18]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe18]
|
||||
connect_debug_port u_ila_0/probe18 [get_nets [list {BUS_axi_rvalid}]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe19]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe19]
|
||||
connect_debug_port u_ila_0/probe19 [get_nets [list {BUS_axi_rready}]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe20]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe20]
|
||||
connect_debug_port u_ila_0/probe20 [get_nets [list {BUS_axi_wready}]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe21]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe21]
|
||||
connect_debug_port u_ila_0/probe21 [get_nets [list {BUS_axi_wvalid}]]
|
||||
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 64 [get_debug_ports u_ila_0/probe22]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe22]
|
||||
connect_debug_port u_ila_0/probe22 [get_nets [list {wallypipelinedsoc/core/lsu/LSUHWDATA[0]} {wallypipelinedsoc/core/lsu/LSUHWDATA[1]} {wallypipelinedsoc/core/lsu/LSUHWDATA[2]} {wallypipelinedsoc/core/lsu/LSUHWDATA[3]} {wallypipelinedsoc/core/lsu/LSUHWDATA[4]} {wallypipelinedsoc/core/lsu/LSUHWDATA[5]} {wallypipelinedsoc/core/lsu/LSUHWDATA[6]} {wallypipelinedsoc/core/lsu/LSUHWDATA[7]} {wallypipelinedsoc/core/lsu/LSUHWDATA[8]} {wallypipelinedsoc/core/lsu/LSUHWDATA[9]} {wallypipelinedsoc/core/lsu/LSUHWDATA[10]} {wallypipelinedsoc/core/lsu/LSUHWDATA[11]} {wallypipelinedsoc/core/lsu/LSUHWDATA[12]} {wallypipelinedsoc/core/lsu/LSUHWDATA[13]} {wallypipelinedsoc/core/lsu/LSUHWDATA[14]} {wallypipelinedsoc/core/lsu/LSUHWDATA[15]} {wallypipelinedsoc/core/lsu/LSUHWDATA[16]} {wallypipelinedsoc/core/lsu/LSUHWDATA[17]} {wallypipelinedsoc/core/lsu/LSUHWDATA[18]} {wallypipelinedsoc/core/lsu/LSUHWDATA[19]} {wallypipelinedsoc/core/lsu/LSUHWDATA[20]} {wallypipelinedsoc/core/lsu/LSUHWDATA[21]} {wallypipelinedsoc/core/lsu/LSUHWDATA[22]} {wallypipelinedsoc/core/lsu/LSUHWDATA[23]} {wallypipelinedsoc/core/lsu/LSUHWDATA[24]} {wallypipelinedsoc/core/lsu/LSUHWDATA[25]} {wallypipelinedsoc/core/lsu/LSUHWDATA[26]} {wallypipelinedsoc/core/lsu/LSUHWDATA[27]} {wallypipelinedsoc/core/lsu/LSUHWDATA[28]} {wallypipelinedsoc/core/lsu/LSUHWDATA[29]} {wallypipelinedsoc/core/lsu/LSUHWDATA[30]} {wallypipelinedsoc/core/lsu/LSUHWDATA[31]} {wallypipelinedsoc/core/lsu/LSUHWDATA[32]} {wallypipelinedsoc/core/lsu/LSUHWDATA[33]} {wallypipelinedsoc/core/lsu/LSUHWDATA[34]} {wallypipelinedsoc/core/lsu/LSUHWDATA[35]} {wallypipelinedsoc/core/lsu/LSUHWDATA[36]} {wallypipelinedsoc/core/lsu/LSUHWDATA[37]} {wallypipelinedsoc/core/lsu/LSUHWDATA[38]} {wallypipelinedsoc/core/lsu/LSUHWDATA[39]} {wallypipelinedsoc/core/lsu/LSUHWDATA[40]} {wallypipelinedsoc/core/lsu/LSUHWDATA[41]} {wallypipelinedsoc/core/lsu/LSUHWDATA[42]} {wallypipelinedsoc/core/lsu/LSUHWDATA[43]} {wallypipelinedsoc/core/lsu/LSUHWDATA[44]} {wallypipelinedsoc/core/lsu/LSUHWDATA[45]} {wallypipelinedsoc/core/lsu/LSUHWDATA[46]} {wallypipelinedsoc/core/lsu/LSUHWDATA[47]} {wallypipelinedsoc/core/lsu/LSUHWDATA[48]} {wallypipelinedsoc/core/lsu/LSUHWDATA[49]} {wallypipelinedsoc/core/lsu/LSUHWDATA[50]} {wallypipelinedsoc/core/lsu/LSUHWDATA[51]} {wallypipelinedsoc/core/lsu/LSUHWDATA[52]} {wallypipelinedsoc/core/lsu/LSUHWDATA[53]} {wallypipelinedsoc/core/lsu/LSUHWDATA[54]} {wallypipelinedsoc/core/lsu/LSUHWDATA[55]} {wallypipelinedsoc/core/lsu/LSUHWDATA[56]} {wallypipelinedsoc/core/lsu/LSUHWDATA[57]} {wallypipelinedsoc/core/lsu/LSUHWDATA[58]} {wallypipelinedsoc/core/lsu/LSUHWDATA[59]} {wallypipelinedsoc/core/lsu/LSUHWDATA[60]} {wallypipelinedsoc/core/lsu/LSUHWDATA[61]} {wallypipelinedsoc/core/lsu/LSUHWDATA[62]} {wallypipelinedsoc/core/lsu/LSUHWDATA[63]} ]]
|
||||
|
||||
# the debug hub has issues with the clocks from the mmcm so lets give up an connect to the 100Mhz input clock.
|
||||
#connect_debug_port dbg_hub/clk [get_nets default_100mhz_clk]
|
||||
connect_debug_port dbg_hub/clk [get_nets CPUCLK]
|
||||
@ -1 +0,0 @@
|
||||
test to make sure i can still merge my code into the new open hardware group.
|
||||
@ -1,53 +1,14 @@
|
||||
dst := IP
|
||||
sdc_src := ~/repos/sdc.tar.gz
|
||||
|
||||
# Select the desired board and the all build rules
|
||||
# vcu118
|
||||
export XILINX_PART := xcvu9p-flga2104-2L-e
|
||||
export XILINX_BOARD := xilinx.com:vcu118:part0:2.4
|
||||
export board := vcu118
|
||||
all: FPGA
|
||||
|
||||
# vcu108
|
||||
#export XILINX_PART := xcvu095-ffva2104-2-e
|
||||
#export XILINX_BOARD := xilinx.com:vcu108:part0:1.2
|
||||
#export board := vcu108
|
||||
FPGA: IP
|
||||
vivado -mode batch -source wally.tcl 2>&1 | tee wally.log
|
||||
|
||||
# Arty A7
|
||||
#export XILINX_PART := xc7a100tcsg324-1
|
||||
#export XILINX_BOARD := digilentinc.com:arty-a7-100:part0:1.1
|
||||
#export board := ArtyA7
|
||||
|
||||
# for Arty A7 and S7 boards
|
||||
#all: FPGA_Arty
|
||||
|
||||
# VCU 108 and VCU 118 boards
|
||||
all: FPGA_VCU
|
||||
|
||||
FPGA_Arty: PreProcessFiles IP_Arty SDC
|
||||
vivado -mode tcl -source wally.tcl 2>&1 | tee wally.log
|
||||
|
||||
FPGA_VCU: PreProcessFiles IP_VCU SDC
|
||||
vivado -mode tcl -source wally.tcl 2>&1 | tee wally.log
|
||||
|
||||
IP_VCU: $(dst)/xlnx_proc_sys_reset.log \
|
||||
$(dst)/xlnx_ddr4-$(board).log \
|
||||
IP: $(dst)/xlnx_proc_sys_reset.log \
|
||||
$(dst)/xlnx_ddr4.log \
|
||||
$(dst)/xlnx_axi_clock_converter.log \
|
||||
$(dst)/xlnx_ahblite_axi_bridge.log
|
||||
|
||||
IP_Arty: $(dst)/xlnx_proc_sys_reset.log \
|
||||
$(dst)/xlnx_ddr3-$(board).log \
|
||||
$(dst)/xlnx_mmcm.log \
|
||||
$(dst)/xlnx_axi_clock_converter.log \
|
||||
$(dst)/xlnx_ahblite_axi_bridge.log
|
||||
|
||||
SDC:
|
||||
cp $(sdc_src) ../src/
|
||||
tar xzf ../src/sdc.tar.gz -C ../src
|
||||
|
||||
PreProcessFiles:
|
||||
rm -rf ../src/CopiedFiles_do_not_add_to_repo/
|
||||
cp -r ../../src/ ../src/CopiedFiles_do_not_add_to_repo/
|
||||
./insert_debug_comment.sh
|
||||
$(dst)/xlnx_ahblite_axi_bridge.log
|
||||
|
||||
$(dst)/%.log: %.tcl
|
||||
mkdir -p IP
|
||||
|
||||
@ -1,37 +0,0 @@
|
||||
##################################################
|
||||
#
|
||||
# For info on creating trigger state machines:
|
||||
# 1) In the main Vivado menu bar, select
|
||||
# Window > Language Templates
|
||||
# 2) In the Templates window, select
|
||||
# Debug > Trigger State Machine
|
||||
# 3) Refer to the entry 'Info' for an overview
|
||||
# of the trigger state machine language.
|
||||
#
|
||||
# More information can be found in this document:
|
||||
#
|
||||
# Vivado Design Suite User Guide: Programming
|
||||
# and Debugging (UG908)
|
||||
#
|
||||
##################################################
|
||||
state state_reset:
|
||||
if(wallypipelinedsoc/core/lsu/bus.dcache.dcache/cachefsm/CurrState == 4'h1) then
|
||||
reset_counter $counter0;
|
||||
goto state_begin_count;
|
||||
#goto state_trigger;
|
||||
else
|
||||
goto state_reset;
|
||||
endif
|
||||
|
||||
state state_begin_count:
|
||||
if($counter0 == 16'h0164) then
|
||||
goto state_trigger;
|
||||
elseif(wallypipelinedsoc/core/lsu/bus.dcache.dcache/cachefsm/CurrState == 4'h1) then
|
||||
increment_counter $counter0;
|
||||
goto state_begin_count;
|
||||
else
|
||||
goto state_reset;
|
||||
endif
|
||||
|
||||
state state_trigger:
|
||||
trigger;
|
||||
@ -1,49 +0,0 @@
|
||||
##################################################
|
||||
#
|
||||
# For info on creating trigger state machines:
|
||||
# 1) In the main Vivado menu bar, select
|
||||
# Window > Language Templates
|
||||
# 2) In the Templates window, select
|
||||
# Debug > Trigger State Machine
|
||||
# 3) Refer to the entry 'Info' for an overview
|
||||
# of the trigger state machine language.
|
||||
#
|
||||
# More information can be found in this document:
|
||||
#
|
||||
# Vivado Design Suite User Guide: Programming
|
||||
# and Debugging (UG908)
|
||||
#
|
||||
##################################################
|
||||
state state_reset:
|
||||
if(wallypipelinedsoc/uncore.uncore/uart.uart/INTR == 1'b1) then
|
||||
reset_counter $counter0;
|
||||
reset_counter $counter1;
|
||||
goto state_begin_count;
|
||||
else
|
||||
goto state_reset;
|
||||
endif
|
||||
|
||||
state state_begin_count:
|
||||
if(wallypipelinedsoc/uncore.uncore/uart.uart/INTR == 1'b0) then
|
||||
reset_counter $counter0;
|
||||
reset_counter $counter1;
|
||||
goto state_reset;
|
||||
elseif($counter0 == 16'hFFFF && wallypipelinedsoc/uncore.uncore/uart.uart/INTR == 1'b1) then
|
||||
goto state_count1;
|
||||
else
|
||||
increment_counter $counter0;
|
||||
goto state_begin_count;
|
||||
#endif
|
||||
endif
|
||||
|
||||
state state_count1:
|
||||
if($counter1 == 16'h000F && wallypipelinedsoc/uncore.uncore/uart.uart/INTR == 1'b1) then
|
||||
goto state_trigger;
|
||||
else
|
||||
increment_counter $counter1;
|
||||
reset_counter $counter0;
|
||||
goto state_begin_count;
|
||||
endif
|
||||
|
||||
state state_trigger:
|
||||
trigger;
|
||||
@ -1,38 +0,0 @@
|
||||
#!/bin/bash
|
||||
###########################################
|
||||
## insert_debug_comment.sh
|
||||
##
|
||||
## Written: Ross Thompson ross1728@gmail.com
|
||||
## Created: 20 January 2023
|
||||
## Modified: 20 January 2023
|
||||
##
|
||||
## A component of the CORE-V-WALLY configurable RISC-V project.
|
||||
##
|
||||
## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
|
||||
##
|
||||
## SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
##
|
||||
## Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||
## except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||
## may obtain a copy of the License at
|
||||
##
|
||||
## https:##solderpad.org#licenses#SHL-2.1#
|
||||
##
|
||||
## Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||
## License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||
## either express or implied. See the License for the specific language governing permissions
|
||||
## and limitations under the License.
|
||||
################################################################################################
|
||||
|
||||
# This script copies wally's pipelined#src to fpga#src#CopiedFiles_do_not_add_to_repo
|
||||
# Then it processes them to add mark_debug on signals needed by the FPGA's ILA.
|
||||
copiedDir="../src/CopiedFiles_do_not_add_to_repo"
|
||||
while read line; do
|
||||
readarray -d ":" -t StrArray <<< "$line"
|
||||
file="${copiedDir}/${StrArray[0]}"
|
||||
signal=`echo "${StrArray[1]}" | awk '{$1=$1};1'`
|
||||
readarray -d " " -t SigArray <<< $signal
|
||||
sigType=`echo "${SigArray[0]}" | awk '{$1=$1};1'`
|
||||
sigName=`echo "${SigArray[1]}" | awk '{$1=$1};1'`
|
||||
find $copiedDir -wholename $file | xargs sed -i "s/\(.*${sigType}.*${sigName}\)/(\* mark_debug = \"true\" \*)\1/g"
|
||||
done < ../constraints/marked_debug.txt
|
||||
@ -1,97 +0,0 @@
|
||||
#!/usr/bin/python3
|
||||
###########################################
|
||||
## fpgaTop.sv
|
||||
##
|
||||
## Written: jacob.pease@okstate.edu 06 April 2023
|
||||
## Modified:
|
||||
##
|
||||
## Purpose: Generates 1 entry in a ILA debugger
|
||||
##
|
||||
## A component of the Wally configurable RISC-V project.
|
||||
##
|
||||
## Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
||||
##
|
||||
## Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
|
||||
## files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
|
||||
## modify, merge, publish, distribute, sublicense, and#or sell copies of the Software, and to permit persons to whom the Software
|
||||
## is furnished to do so, subject to the following conditions:
|
||||
##
|
||||
## The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
|
||||
##
|
||||
## THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
## OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
|
||||
## BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
|
||||
## OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
###########################################
|
||||
|
||||
import sys
|
||||
|
||||
def usage():
|
||||
print("Usage: ./probes name width probenum")
|
||||
|
||||
def header():
|
||||
return """create_debug_core u_ila_0 ila
|
||||
|
||||
set_property C_DATA_DEPTH 16384 [get_debug_cores u_ila_0]
|
||||
set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
|
||||
set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
|
||||
set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
|
||||
set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
|
||||
set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
|
||||
set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
|
||||
set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
|
||||
startgroup
|
||||
set_property C_EN_STRG_QUAL true [get_debug_cores u_ila_0 ]
|
||||
set_property C_ADV_TRIGGER true [get_debug_cores u_ila_0 ]
|
||||
set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0 ]
|
||||
set_property ALL_PROBE_SAME_MU_CNT 4 [get_debug_cores u_ila_0 ]
|
||||
endgroup
|
||||
connect_debug_port u_ila_0/clk [get_nets [list xlnx_ddr4_c0/inst/u_ddr4_infrastructure/addn_ui_clkout1 ]]"""
|
||||
|
||||
def convertLine(x):
|
||||
temp = x.split()
|
||||
temp[1] = int(temp[1])
|
||||
return tuple(temp)
|
||||
|
||||
def probeBits( probe ):
|
||||
str = ''
|
||||
|
||||
if (probe[1] > 1):
|
||||
for i in range(probe[1]):
|
||||
if i != (probe[1]-1):
|
||||
str = str + f"{{{probe[0]}[{i}]}} "
|
||||
else:
|
||||
str = str + f"{{{probe[0]}[{i}]}} "
|
||||
|
||||
else:
|
||||
str = f'{{{probe[0]}}}'
|
||||
|
||||
return str
|
||||
|
||||
def printProbe( probe, i ):
|
||||
bits = probeBits(probe)
|
||||
|
||||
return (
|
||||
f'create_debug_port u_ila_0 probe\n'
|
||||
f'set_property port_width {probe[1]} [get_debug_ports u_ila_0/probe{i}]\n'
|
||||
f'set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe{i}]\n'
|
||||
f'connect_debug_port u_ila_0/probe{i} [get_nets [list {bits}]]\n\n'
|
||||
)
|
||||
|
||||
def main(args):
|
||||
if (len(args) != 3):
|
||||
usage()
|
||||
|
||||
name = args[0]
|
||||
width = int(args[1])
|
||||
probeNum = int(args[2])
|
||||
|
||||
|
||||
probe = (name, width)
|
||||
|
||||
print(printProbe(probe, probeNum))
|
||||
|
||||
if __name__ == '__main__':
|
||||
main(sys.argv[1:])
|
||||
|
||||
|
||||
@ -1,53 +1,33 @@
|
||||
# start by reading in all the IP blocks generated by vivado
|
||||
|
||||
set partNumber $::env(XILINX_PART)
|
||||
set boardName $::env(XILINX_BOARD)
|
||||
set boardSubName [lindex [split ${boardName} :] 1]
|
||||
set board $::env(board)
|
||||
set partNumber xcvu9p-flga2104-2L-e
|
||||
set boardName xilinx.com:vcu118:part0:2.4
|
||||
|
||||
set ipName WallyFPGA
|
||||
|
||||
create_project $ipName . -force -part $partNumber
|
||||
if {$boardName!="ArtyA7"} {
|
||||
set_property board_part $boardName [current_project]
|
||||
}
|
||||
set_property board_part $boardName [current_project]
|
||||
|
||||
read_ip IP/xlnx_proc_sys_reset.srcs/sources_1/ip/xlnx_proc_sys_reset/xlnx_proc_sys_reset.xci
|
||||
read_ip IP/xlnx_ahblite_axi_bridge.srcs/sources_1/ip/xlnx_ahblite_axi_bridge/xlnx_ahblite_axi_bridge.xci
|
||||
read_ip IP/xlnx_axi_clock_converter.srcs/sources_1/ip/xlnx_axi_clock_converter/xlnx_axi_clock_converter.xci
|
||||
|
||||
if {$board=="ArtyA7"} {
|
||||
read_ip IP/xlnx_ddr3.srcs/sources_1/ip/xlnx_ddr3/xlnx_ddr3.xci
|
||||
read_ip IP/xlnx_mmcm.srcs/sources_1/ip/xlnx_mmcm/xlnx_mmcm.xci
|
||||
} else {
|
||||
read_ip IP/xlnx_ddr4.srcs/sources_1/ip/xlnx_ddr4/xlnx_ddr4.xci
|
||||
}
|
||||
|
||||
read_verilog -sv [glob -type f ../src/CopiedFiles_do_not_add_to_repo/*/*.sv ../src/CopiedFiles_do_not_add_to_repo/*/*/*.sv]
|
||||
if {$board=="ArtyA7"} {
|
||||
read_verilog {../src/fpgaTopArtyA7.v}
|
||||
} else {
|
||||
read_verilog {../src/fpgaTop.v}
|
||||
}
|
||||
read_verilog -sv [glob -type f ../src/sdc/*.sv]
|
||||
|
||||
set_property include_dirs {../../config/fpga ../../config/shared} [current_fileset]
|
||||
read_ip IP/xlnx_ddr4.srcs/sources_1/ip/xlnx_ddr4/xlnx_ddr4.xci
|
||||
|
||||
|
||||
if {$board=="ArtyA7"} {
|
||||
add_files -fileset constrs_1 -norecurse ../constraints/constraints-$board.xdc
|
||||
set_property PROCESSING_ORDER NORMAL [get_files ../constraints/constraints-$board.xdc]
|
||||
} else {
|
||||
add_files -fileset constrs_1 -norecurse ../constraints/constraints-$boardSubName.xdc
|
||||
set_property PROCESSING_ORDER NORMAL [get_files ../constraints/constraints-$boardSubName.xdc]
|
||||
}
|
||||
read_verilog -sv [glob -type f ../../pipelined/src/*/*.sv ../../pipelined/src/*/*/*.sv]
|
||||
read_verilog {../src/fpgaTop.v}
|
||||
|
||||
set_property include_dirs {../../pipelined/config/fpga ../../pipelined/config/shared} [current_fileset]
|
||||
|
||||
add_files -fileset constrs_1 -norecurse ../constraints/constraints.xdc
|
||||
set_property PROCESSING_ORDER NORMAL [get_files ../constraints/constraints.xdc]
|
||||
|
||||
# define top level
|
||||
set_property top fpgaTop [current_fileset]
|
||||
|
||||
|
||||
update_compile_order -fileset sources_1
|
||||
# This is important as the ddr3/4 IP contains the generate clock constraint which the user constraints depend on.
|
||||
# This is important as the ddr4 IP contains the generate clock constraint which the user constraints depend on.
|
||||
exec mkdir -p reports/
|
||||
exec rm -rf reports/*
|
||||
|
||||
@ -58,12 +38,13 @@ synth_design -rtl -name rtl_1
|
||||
|
||||
report_clocks -file reports/clocks.rpt
|
||||
|
||||
# this does synthesis.
|
||||
# this does synthesis? wtf?
|
||||
launch_runs synth_1 -jobs 4
|
||||
|
||||
wait_on_run synth_1
|
||||
open_run synth_1
|
||||
|
||||
|
||||
check_timing -verbose -file reports/check_timing.rpt
|
||||
report_timing -max_paths 10 -nworst 10 -delay_type max -sort_by slack -file reports/timing_WORST_10.rpt
|
||||
report_timing -nworst 1 -delay_type max -sort_by group -file reports/timing.rpt
|
||||
@ -73,12 +54,8 @@ report_clock_interaction -file re
|
||||
|
||||
write_verilog -force -mode funcsim sim/syn-funcsim.v
|
||||
|
||||
if {$board=="ArtyA7"} {
|
||||
source ../constraints/small-debug.xdc
|
||||
|
||||
} else {
|
||||
source ../constraints/debug4.xdc
|
||||
}
|
||||
source ../constraints/debug2.xdc
|
||||
|
||||
|
||||
# set for RuntimeOptimized implementation
|
||||
|
||||
@ -9,15 +9,15 @@
|
||||
</db_ref>
|
||||
</db_ref_list>
|
||||
<zoom_setting>
|
||||
<ZoomStartTime time="14962fs"></ZoomStartTime>
|
||||
<ZoomEndTime time="14974fs"></ZoomEndTime>
|
||||
<Cursor1Time time="14967fs"></Cursor1Time>
|
||||
<ZoomStartTime time="8081fs"></ZoomStartTime>
|
||||
<ZoomEndTime time="8103fs"></ZoomEndTime>
|
||||
<Cursor1Time time="8083fs"></Cursor1Time>
|
||||
</zoom_setting>
|
||||
<column_width_setting>
|
||||
<NameColumnWidth column_width="400"></NameColumnWidth>
|
||||
<ValueColumnWidth column_width="177"></ValueColumnWidth>
|
||||
<NameColumnWidth column_width="355"></NameColumnWidth>
|
||||
<ValueColumnWidth column_width="170"></ValueColumnWidth>
|
||||
</column_width_setting>
|
||||
<WVObjectSize size="32" />
|
||||
<WVObjectSize size="15" />
|
||||
<wave_markers>
|
||||
</wave_markers>
|
||||
<wvobject type="array" fp_name="wallypipelinedsoc/core/PCM">
|
||||
@ -36,31 +36,6 @@
|
||||
<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="vbus" fp_name="vbus2259">
|
||||
<obj_property name="label">rd</obj_property>
|
||||
<obj_property name="DisplayName">label</obj_property>
|
||||
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
|
||||
<wvobject type="logic" fp_name="wallypipelinedsoc/core/InstrM[11]">
|
||||
<obj_property name="ElementShortName">[11]</obj_property>
|
||||
<obj_property name="ObjectShortName">[11]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="wallypipelinedsoc/core/InstrM[10]">
|
||||
<obj_property name="ElementShortName">[10]</obj_property>
|
||||
<obj_property name="ObjectShortName">[10]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="wallypipelinedsoc/core/InstrM[9]">
|
||||
<obj_property name="ElementShortName">[9]</obj_property>
|
||||
<obj_property name="ObjectShortName">[9]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="wallypipelinedsoc/core/InstrM[8]">
|
||||
<obj_property name="ElementShortName">[8]</obj_property>
|
||||
<obj_property name="ObjectShortName">[8]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="wallypipelinedsoc/core/InstrM[7]">
|
||||
<obj_property name="ElementShortName">[7]</obj_property>
|
||||
<obj_property name="ObjectShortName">[7]</obj_property>
|
||||
</wvobject>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="wallypipelinedsoc/core/InstrValidM">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">wallypipelinedsoc/core/InstrValidM</obj_property>
|
||||
@ -78,6 +53,7 @@
|
||||
<wvobject type="group" fp_name="group468">
|
||||
<obj_property name="label">CPU to LSU</obj_property>
|
||||
<obj_property name="DisplayName">label</obj_property>
|
||||
<obj_property name="isExpanded"></obj_property>
|
||||
<wvobject type="array" fp_name="wallypipelinedsoc/core/IEUAdrM">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">wallypipelinedsoc/core/IEUAdrM[63:0]</obj_property>
|
||||
@ -94,14 +70,6 @@
|
||||
<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="wallypipelinedsoc/core/lsu/ReadDataM">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">wallypipelinedsoc/core/lsu/ReadDataM[63:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">ReadDataM[63:0]</obj_property>
|
||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||
<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="wallypipelinedsoc/core/lsu/WriteDataM">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">wallypipelinedsoc/core/lsu/WriteDataM[63:0]</obj_property>
|
||||
@ -111,34 +79,22 @@
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="wallypipelinedsoc/core/IEUAdrM">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">wallypipelinedsoc/core/IEUAdrM[63:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">IEUAdrM[63:0]</obj_property>
|
||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||
<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
<wvobject type="group" fp_name="group469">
|
||||
<obj_property name="label">xIP</obj_property>
|
||||
<obj_property name="DisplayName">label</obj_property>
|
||||
<wvobject type="array" fp_name="wallypipelinedsoc/core/priv.priv/csr/csrm/MIP_REGW_5">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/csr/csrm/MIP_REGW_5[9:9]</obj_property>
|
||||
<obj_property name="ObjectShortName">MIP_REGW_5[9:9]</obj_property>
|
||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||
<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="wallypipelinedsoc/core/MemRWM">
|
||||
<wvobject type="array" fp_name="wallypipelinedsoc/core/priv.priv/csr/csrm/MIP_REGW_5">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">wallypipelinedsoc/core/MemRWM[1:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">MemRWM[1:0]</obj_property>
|
||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||
<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="wallypipelinedsoc/core/lsu/ReadDataM">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">wallypipelinedsoc/core/lsu/ReadDataM[63:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">ReadDataM[63:0]</obj_property>
|
||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||
<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="wallypipelinedsoc/core/lsu/WriteDataM">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">wallypipelinedsoc/core/lsu/WriteDataM[63:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">WriteDataM[63:0]</obj_property>
|
||||
<obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/csr/csrm/MIP_REGW_5[9:9]</obj_property>
|
||||
<obj_property name="ObjectShortName">MIP_REGW_5[9:9]</obj_property>
|
||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||
<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
@ -174,91 +130,103 @@
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[63:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">MEDELEG_REGW[63:0]</obj_property>
|
||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||
<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[11:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">MIDELEG_REGW[11:0]</obj_property>
|
||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||
<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="wallypipelinedsoc/core/priv.priv/InterruptM">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/InterruptM</obj_property>
|
||||
<obj_property name="ObjectShortName">InterruptM</obj_property>
|
||||
<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="group" fp_name="group463">
|
||||
<obj_property name="label">LSU to Bus</obj_property>
|
||||
<obj_property name="DisplayName">label</obj_property>
|
||||
<obj_property name="isExpanded"></obj_property>
|
||||
<wvobject type="array" fp_name="wallypipelinedsoc/core/lsu/LSUHADDR">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">wallypipelinedsoc/core/lsu/LSUHADDR[31:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">LSUHADDR[31:0]</obj_property>
|
||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||
<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="wallypipelinedsoc/core/lsu/LSUHBURST">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">wallypipelinedsoc/core/lsu/LSUHBURST[2:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">LSUHBURST[2:0]</obj_property>
|
||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||
<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="wallypipelinedsoc/core/lsu/LSUHREADY">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">wallypipelinedsoc/core/lsu/LSUHREADY</obj_property>
|
||||
<obj_property name="ObjectShortName">LSUHREADY</obj_property>
|
||||
<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="wallypipelinedsoc/core/lsu/LSUHSIZE">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">wallypipelinedsoc/core/lsu/LSUHSIZE[1:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">LSUHSIZE[1:0]</obj_property>
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@ -266,7 +234,6 @@
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|
||||
<obj_property name="ElementShortName">wallypipelinedsoc/core/hzu/LSUStallM</obj_property>
|
||||
<obj_property name="ObjectShortName">LSUStallM</obj_property>
|
||||
<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="wallypipelinedsoc/core/hzu/MDUStallD">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">wallypipelinedsoc/core/hzu/MDUStallD</obj_property>
|
||||
<obj_property name="ObjectShortName">MDUStallD</obj_property>
|
||||
<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="wallypipelinedsoc/core/hzu/StoreStallD">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">wallypipelinedsoc/core/hzu/StoreStallD</obj_property>
|
||||
<obj_property name="ObjectShortName">StoreStallD</obj_property>
|
||||
<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
|
||||
</wvobject>
|
||||
<wvobject type="group" fp_name="group1722">
|
||||
<obj_property name="label">flush/stall</obj_property>
|
||||
<obj_property name="DisplayName">label</obj_property>
|
||||
<obj_property name="isExpanded"></obj_property>
|
||||
<wvobject type="logic" fp_name="wallypipelinedsoc/core/hzu/FlushD">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">wallypipelinedsoc/core/hzu/FlushD</obj_property>
|
||||
<obj_property name="ObjectShortName">FlushD</obj_property>
|
||||
<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="wallypipelinedsoc/core/hzu/FlushE">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">wallypipelinedsoc/core/hzu/FlushE</obj_property>
|
||||
<obj_property name="ObjectShortName">FlushE</obj_property>
|
||||
<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="wallypipelinedsoc/core/hzu/FlushM">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">wallypipelinedsoc/core/hzu/FlushM</obj_property>
|
||||
<obj_property name="ObjectShortName">FlushM</obj_property>
|
||||
<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="wallypipelinedsoc/core/hzu/FlushW">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">wallypipelinedsoc/core/hzu/FlushW</obj_property>
|
||||
<obj_property name="ObjectShortName">FlushW</obj_property>
|
||||
<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="wallypipelinedsoc/core/hzu/StallD">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">wallypipelinedsoc/core/hzu/StallD</obj_property>
|
||||
<obj_property name="ObjectShortName">StallD</obj_property>
|
||||
<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="wallypipelinedsoc/core/hzu/StallE">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">wallypipelinedsoc/core/hzu/StallE</obj_property>
|
||||
<obj_property name="ObjectShortName">StallE</obj_property>
|
||||
<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="wallypipelinedsoc/core/hzu/StallF">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">wallypipelinedsoc/core/hzu/StallF</obj_property>
|
||||
<obj_property name="ObjectShortName">StallF</obj_property>
|
||||
<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="wallypipelinedsoc/core/hzu/StallM">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">wallypipelinedsoc/core/hzu/StallM</obj_property>
|
||||
<obj_property name="ObjectShortName">StallM</obj_property>
|
||||
<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[63:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">csrs.SCAUSE_REGW[63:0]</obj_property>
|
||||
<wvobject type="array" fp_name="wallypipelinedsoc/core/HRDATA">
|
||||
<obj_property name="ElementShortName">wallypipelinedsoc/core/HRDATA[63:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">HRDATA[63:0]</obj_property>
|
||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||
<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[63:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">MCAUSE_REGW[63:0]</obj_property>
|
||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||
<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="group" fp_name="group3442">
|
||||
<obj_property name="label">IFU</obj_property>
|
||||
<obj_property name="DisplayName">label</obj_property>
|
||||
<obj_property name="isExpanded"></obj_property>
|
||||
<wvobject type="array" fp_name="wallypipelinedsoc/core/ifu/bus.icache.icache/cachefsm/CurrState">
|
||||
<obj_property name="DisplayName">label</obj_property>
|
||||
<obj_property name="ElementShortName">wallypipelinedsoc/core/ifu/bus.icache.icache/cachefsm/CurrState[3:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">CurrState[3:0]</obj_property>
|
||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||
<obj_property name="label">icache fsm</obj_property>
|
||||
<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="wallypipelinedsoc/core/ifu/bus.icache.ahbcacheinterface/AHBBuscachefsm/CurrState">
|
||||
<obj_property name="DisplayName">label</obj_property>
|
||||
<obj_property name="ElementShortName">wallypipelinedsoc/core/ifu/bus.icache.ahbcacheinterface/AHBBuscachefsm/CurrState[2:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">CurrState[2:0]</obj_property>
|
||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||
<obj_property name="label">ifu bus fsm</obj_property>
|
||||
<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="wallypipelinedsoc/core/ifu/PCNextF">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">wallypipelinedsoc/core/ifu/PCNextF[63:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">PCNextF[63:0]</obj_property>
|
||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||
<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="wallypipelinedsoc/core/ifu/PCPF">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">wallypipelinedsoc/core/ifu/PCPF[55:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">PCPF[55:0]</obj_property>
|
||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||
<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
|
||||
</wvobject>
|
||||
<wvobject type="group" fp_name="group3443">
|
||||
<obj_property name="label">TLB</obj_property>
|
||||
<obj_property name="DisplayName">label</obj_property>
|
||||
<obj_property name="isExpanded"></obj_property>
|
||||
<wvobject type="logic" fp_name="wallypipelinedsoc/core/lsu/DTLBMissM">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">wallypipelinedsoc/core/lsu/DTLBMissM</obj_property>
|
||||
<obj_property name="ObjectShortName">DTLBMissM</obj_property>
|
||||
<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="wallypipelinedsoc/core/lsu/DTLBWriteM">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">wallypipelinedsoc/core/lsu/DTLBWriteM</obj_property>
|
||||
<obj_property name="ObjectShortName">DTLBWriteM</obj_property>
|
||||
<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="wallypipelinedsoc/core/lsu/ITLBMissF">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">wallypipelinedsoc/core/lsu/ITLBMissF</obj_property>
|
||||
<obj_property name="ObjectShortName">ITLBMissF</obj_property>
|
||||
<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="wallypipelinedsoc/core/lsu/ITLBWriteF">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">wallypipelinedsoc/core/lsu/ITLBWriteF</obj_property>
|
||||
<obj_property name="ObjectShortName">ITLBWriteF</obj_property>
|
||||
<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[63:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">MEPC_REGW[63:0]</obj_property>
|
||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||
<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[63:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">SEPC_REGW[63:0]</obj_property>
|
||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||
<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[63:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">rf[2]__0[63:0]</obj_property>
|
||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||
<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[63:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">rf[4]__0[63:0]</obj_property>
|
||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||
<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[63:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">rf[10]__0[63:0]</obj_property>
|
||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||
<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="wallypipelinedsoc/core/lsu/VIRTMEM_SUPPORTED.hptw/WalkerState">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">wallypipelinedsoc/core/lsu/VIRTMEM_SUPPORTED.hptw/WalkerState[3:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">WalkerState[3:0]</obj_property>
|
||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||
<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
|
||||
</wave_config>
|
||||
|
||||
@ -1,10 +1,10 @@
|
||||
|
||||
set partNumber $::env(XILINX_PART)
|
||||
set boardName $::env(XILINX_BOARD)
|
||||
#set partNumber $::env(XILINX_PART)
|
||||
#set boardNmae $::env(XILINX_BOARD)
|
||||
|
||||
# vcu118 board
|
||||
#set partNumber xcvu9p-flga2104-2L-e
|
||||
#set boardName xilinx.com:vcu118:part0:2.4
|
||||
set partNumber xcvu9p-flga2104-2L-e
|
||||
set boardName xilinx.com:vcu118:part0:2.4
|
||||
|
||||
# kcu105 board
|
||||
#set partNumber xcku040-ffva1156-2-e
|
||||
@ -13,9 +13,7 @@ set boardName $::env(XILINX_BOARD)
|
||||
set ipName xlnx_ahblite_axi_bridge
|
||||
|
||||
create_project $ipName . -force -part $partNumber
|
||||
if {$boardName!="ArtyA7"} {
|
||||
set_property board_part $boardName [current_project]
|
||||
}
|
||||
set_property board_part $boardName [current_project]
|
||||
|
||||
# really just these two lines which change
|
||||
create_ip -name ahblite_axi_bridge -vendor xilinx.com -library ip -module_name $ipName
|
||||
|
||||
@ -1,15 +1,13 @@
|
||||
|
||||
set partNumber $::env(XILINX_PART)
|
||||
set boardName $::env(XILINX_BOARD)
|
||||
#set partNumber xcvu9p-flga2104-2L-e
|
||||
#set boardName xilinx.com:vcu118:part0:2.4
|
||||
#set partNumber $::env(XILINX_PART)
|
||||
#set boardNmae $::env(XILINX_BOARD)
|
||||
set partNumber xcvu9p-flga2104-2L-e
|
||||
set boardName xilinx.com:vcu118:part0:2.4
|
||||
|
||||
set ipName xlnx_axi_clock_converter
|
||||
|
||||
create_project $ipName . -force -part $partNumber
|
||||
if {$boardName!="ArtyA7"} {
|
||||
set_property board_part $boardName [current_project]
|
||||
}
|
||||
set_property board_part $boardName [current_project]
|
||||
|
||||
create_ip -name axi_clock_converter -vendor xilinx.com -library ip -module_name $ipName
|
||||
|
||||
|
||||
@ -1,22 +0,0 @@
|
||||
|
||||
set partNumber $::env(XILINX_PART)
|
||||
set boardName $::env(XILINX_BOARD)
|
||||
|
||||
set ipName xlnx_ddr3
|
||||
|
||||
create_project $ipName . -force -part $partNumber
|
||||
set_property board_part $boardName [current_project]
|
||||
|
||||
# really just these two lines which change
|
||||
create_ip -name mig_7series -vendor xilinx.com -library ip -module_name $ipName
|
||||
|
||||
exec mkdir -p IP/$ipName.srcs/sources_1/ip/$ipName
|
||||
exec cp ../xlnx_ddr3-artya7-mig.prj $ipName.srcs/sources_1/ip/$ipName/xlnx_ddr3-artya7-mig.prj
|
||||
|
||||
set_property -dict [list CONFIG.XML_INPUT_FILE {xlnx_ddr3-artya7-mig.prj} CONFIG.RESET_BOARD_INTERFACE {Custom} CONFIG.MIG_DONT_TOUCH_PARAM {Custom} CONFIG.BOARD_MIG_PARAM {Custom}] [get_ips $ipName]
|
||||
|
||||
generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
|
||||
generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
|
||||
create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
|
||||
launch_run -jobs 8 ${ipName}_synth_1
|
||||
wait_on_run ${ipName}_synth_1
|
||||
@ -1,162 +0,0 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<Project NoOfControllers="1">
|
||||
|
||||
|
||||
|
||||
<!-- IMPORTANT: This is an internal file that has been generated by the MIG software. Any direct editing or changes made to this file may result in unpredictable behavior or data corruption. It is strongly advised that users do not edit the contents of this file. Re-run the MIG GUI with the required settings if any of the options provided below need to be altered. -->
|
||||
|
||||
<ModuleName>mig_7series_0</ModuleName>
|
||||
|
||||
<dci_inouts_inputs>1</dci_inouts_inputs>
|
||||
|
||||
<dci_inputs>1</dci_inputs>
|
||||
|
||||
<Debug_En>OFF</Debug_En>
|
||||
|
||||
<DataDepth_En>1024</DataDepth_En>
|
||||
|
||||
<LowPower_En>ON</LowPower_En>
|
||||
|
||||
<XADC_En>Enabled</XADC_En>
|
||||
|
||||
<TargetFPGA>xc7a100t-csg324/-1</TargetFPGA>
|
||||
|
||||
<Version>4.2</Version>
|
||||
|
||||
<SystemClock>Single-Ended</SystemClock>
|
||||
|
||||
<ReferenceClock>No Buffer</ReferenceClock>
|
||||
|
||||
<SysResetPolarity>ACTIVE LOW</SysResetPolarity>
|
||||
|
||||
<BankSelectionFlag>FALSE</BankSelectionFlag>
|
||||
|
||||
<InternalVref>1</InternalVref>
|
||||
|
||||
<dci_hr_inouts_inputs>50 Ohms</dci_hr_inouts_inputs>
|
||||
|
||||
<dci_cascade>0</dci_cascade>
|
||||
|
||||
<FPGADevice>
|
||||
<selected>7a/xc7a100ti-csg324</selected>
|
||||
</FPGADevice>
|
||||
|
||||
<Controller number="0">
|
||||
<MemoryDevice>DDR3_SDRAM/Components/MT41K128M16XX-15E</MemoryDevice>
|
||||
<TimePeriod>3000</TimePeriod>
|
||||
<VccAuxIO>1.8V</VccAuxIO>
|
||||
<PHYRatio>4:1</PHYRatio>
|
||||
<InputClkFreq>166.666</InputClkFreq>
|
||||
<UIExtraClocks>0</UIExtraClocks>
|
||||
<MMCM_VCO>666</MMCM_VCO>
|
||||
<MMCMClkOut0> 1.000</MMCMClkOut0>
|
||||
<MMCMClkOut1>1</MMCMClkOut1>
|
||||
<MMCMClkOut2>1</MMCMClkOut2>
|
||||
<MMCMClkOut3>1</MMCMClkOut3>
|
||||
<MMCMClkOut4>1</MMCMClkOut4>
|
||||
<DataWidth>16</DataWidth>
|
||||
<DeepMemory>1</DeepMemory>
|
||||
<DataMask>1</DataMask>
|
||||
<ECC>Disabled</ECC>
|
||||
<Ordering>Normal</Ordering>
|
||||
<BankMachineCnt>4</BankMachineCnt>
|
||||
<CustomPart>FALSE</CustomPart>
|
||||
<NewPartName/>
|
||||
<RowAddress>14</RowAddress>
|
||||
<ColAddress>10</ColAddress>
|
||||
<BankAddress>3</BankAddress>
|
||||
<MemoryVoltage>1.35V</MemoryVoltage>
|
||||
<UserMemoryAddressMap>BANK_ROW_COLUMN</UserMemoryAddressMap>
|
||||
<PinSelection>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="R2" SLEW="" VCCAUX_IO="" name="ddr3_addr[0]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="R6" SLEW="" VCCAUX_IO="" name="ddr3_addr[10]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="U6" SLEW="" VCCAUX_IO="" name="ddr3_addr[11]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="T6" SLEW="" VCCAUX_IO="" name="ddr3_addr[12]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="T8" SLEW="" VCCAUX_IO="" name="ddr3_addr[13]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="M6" SLEW="" VCCAUX_IO="" name="ddr3_addr[1]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="N4" SLEW="" VCCAUX_IO="" name="ddr3_addr[2]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="T1" SLEW="" VCCAUX_IO="" name="ddr3_addr[3]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="N6" SLEW="" VCCAUX_IO="" name="ddr3_addr[4]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="R7" SLEW="" VCCAUX_IO="" name="ddr3_addr[5]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="V6" SLEW="" VCCAUX_IO="" name="ddr3_addr[6]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="U7" SLEW="" VCCAUX_IO="" name="ddr3_addr[7]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="R8" SLEW="" VCCAUX_IO="" name="ddr3_addr[8]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="V7" SLEW="" VCCAUX_IO="" name="ddr3_addr[9]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="R1" SLEW="" VCCAUX_IO="" name="ddr3_ba[0]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="P4" SLEW="" VCCAUX_IO="" name="ddr3_ba[1]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="P2" SLEW="" VCCAUX_IO="" name="ddr3_ba[2]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="M4" SLEW="" VCCAUX_IO="" name="ddr3_cas_n"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="DIFF_SSTL135" PADName="V9" SLEW="" VCCAUX_IO="" name="ddr3_ck_n[0]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="DIFF_SSTL135" PADName="U9" SLEW="" VCCAUX_IO="" name="ddr3_ck_p[0]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="N5" SLEW="" VCCAUX_IO="" name="ddr3_cke[0]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="U8" SLEW="" VCCAUX_IO="" name="ddr3_cs_n[0]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="L1" SLEW="" VCCAUX_IO="" name="ddr3_dm[0]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="U1" SLEW="" VCCAUX_IO="" name="ddr3_dm[1]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="K5" SLEW="" VCCAUX_IO="" name="ddr3_dq[0]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="U4" SLEW="" VCCAUX_IO="" name="ddr3_dq[10]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="V5" SLEW="" VCCAUX_IO="" name="ddr3_dq[11]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="V1" SLEW="" VCCAUX_IO="" name="ddr3_dq[12]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="T3" SLEW="" VCCAUX_IO="" name="ddr3_dq[13]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="U3" SLEW="" VCCAUX_IO="" name="ddr3_dq[14]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="R3" SLEW="" VCCAUX_IO="" name="ddr3_dq[15]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="L3" SLEW="" VCCAUX_IO="" name="ddr3_dq[1]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="K3" SLEW="" VCCAUX_IO="" name="ddr3_dq[2]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="L6" SLEW="" VCCAUX_IO="" name="ddr3_dq[3]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="M3" SLEW="" VCCAUX_IO="" name="ddr3_dq[4]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="M1" SLEW="" VCCAUX_IO="" name="ddr3_dq[5]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="L4" SLEW="" VCCAUX_IO="" name="ddr3_dq[6]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="M2" SLEW="" VCCAUX_IO="" name="ddr3_dq[7]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="V4" SLEW="" VCCAUX_IO="" name="ddr3_dq[8]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="T5" SLEW="" VCCAUX_IO="" name="ddr3_dq[9]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="DIFF_SSTL135" PADName="N1" SLEW="" VCCAUX_IO="" name="ddr3_dqs_n[0]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="DIFF_SSTL135" PADName="V2" SLEW="" VCCAUX_IO="" name="ddr3_dqs_n[1]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="DIFF_SSTL135" PADName="N2" SLEW="" VCCAUX_IO="" name="ddr3_dqs_p[0]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="DIFF_SSTL135" PADName="U2" SLEW="" VCCAUX_IO="" name="ddr3_dqs_p[1]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="R5" SLEW="" VCCAUX_IO="" name="ddr3_odt[0]"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="P3" SLEW="" VCCAUX_IO="" name="ddr3_ras_n"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="K6" SLEW="" VCCAUX_IO="" name="ddr3_reset_n"/>
|
||||
<Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="P5" SLEW="" VCCAUX_IO="" name="ddr3_we_n"/>
|
||||
</PinSelection>
|
||||
<System_Clock>
|
||||
<Pin Bank="Select Bank" PADName="No connect" name="sys_clk_i"/>
|
||||
</System_Clock>
|
||||
<System_Control>
|
||||
<Pin Bank="Select Bank" PADName="No connect" name="sys_rst"/>
|
||||
<Pin Bank="Select Bank" PADName="No connect" name="init_calib_complete"/>
|
||||
<Pin Bank="Select Bank" PADName="No connect" name="tg_compare_error"/>
|
||||
</System_Control>
|
||||
<TimingParameters>
|
||||
<Parameters tcke="5.625" tfaw="45" tras="36" trcd="13.5" trefi="7.8" trfc="160" trp="13.5" trrd="7.5" trtp="7.5" twtr="7.5"/>
|
||||
</TimingParameters>
|
||||
<mrBurstLength name="Burst Length">8 - Fixed</mrBurstLength>
|
||||
<mrBurstType name="Read Burst Type and Length">Sequential</mrBurstType>
|
||||
<mrCasLatency name="CAS Latency">5</mrCasLatency>
|
||||
<mrMode name="Mode">Normal</mrMode>
|
||||
<mrDllReset name="DLL Reset">No</mrDllReset>
|
||||
<mrPdMode name="DLL control for precharge PD">Slow Exit</mrPdMode>
|
||||
<emrDllEnable name="DLL Enable">Enable</emrDllEnable>
|
||||
<emrOutputDriveStrength name="Output Driver Impedance Control">RZQ/6</emrOutputDriveStrength>
|
||||
<emrMirrorSelection name="Address Mirroring">Disable</emrMirrorSelection>
|
||||
<emrCSSelection name="Controller Chip Select Pin">Enable</emrCSSelection>
|
||||
<emrRTT name="RTT (nominal) - On Die Termination (ODT)">RZQ/6</emrRTT>
|
||||
<emrPosted name="Additive Latency (AL)">0</emrPosted>
|
||||
<emrOCD name="Write Leveling Enable">Disabled</emrOCD>
|
||||
<emrDQS name="TDQS enable">Enabled</emrDQS>
|
||||
<emrRDQS name="Qoff">Output Buffer Enabled</emrRDQS>
|
||||
<mr2PartialArraySelfRefresh name="Partial-Array Self Refresh">Full Array</mr2PartialArraySelfRefresh>
|
||||
<mr2CasWriteLatency name="CAS write latency">5</mr2CasWriteLatency>
|
||||
<mr2AutoSelfRefresh name="Auto Self Refresh">Enabled</mr2AutoSelfRefresh>
|
||||
<mr2SelfRefreshTempRange name="High Temparature Self Refresh Rate">Normal</mr2SelfRefreshTempRange>
|
||||
<mr2RTTWR name="RTT_WR - Dynamic On Die Termination (ODT)">Dynamic ODT off</mr2RTTWR>
|
||||
<PortInterface>AXI</PortInterface>
|
||||
<AXIParameters>
|
||||
<C0_C_RD_WR_ARB_ALGORITHM>ROUND_ROBIN</C0_C_RD_WR_ARB_ALGORITHM>
|
||||
<C0_S_AXI_ADDR_WIDTH>28</C0_S_AXI_ADDR_WIDTH>
|
||||
<C0_S_AXI_DATA_WIDTH>64</C0_S_AXI_DATA_WIDTH>
|
||||
<C0_S_AXI_ID_WIDTH>4</C0_S_AXI_ID_WIDTH>
|
||||
<C0_S_AXI_SUPPORTS_NARROW_BURST>0</C0_S_AXI_SUPPORTS_NARROW_BURST>
|
||||
</AXIParameters>
|
||||
</Controller>
|
||||
|
||||
|
||||
</Project>
|
||||
@ -1,164 +0,0 @@
|
||||
|
||||
set partNumber $::env(XILINX_PART)
|
||||
set boardName $::env(XILINX_BOARD)
|
||||
#set partNumber xcvu9p-flga2104-2L-e
|
||||
#set boardName xilinx.com:vcu118:part0:2.4
|
||||
|
||||
set ipName xlnx_ddr4
|
||||
|
||||
create_project $ipName . -force -part $partNumber
|
||||
set_property board_part $boardName [current_project]
|
||||
|
||||
# really just these two lines which change
|
||||
create_ip -name ddr4 -vendor xilinx.com -library ip -module_name $ipName
|
||||
set_property -dict [list CONFIG.C0.ControllerType {DDR4_SDRAM} \
|
||||
CONFIG.No_Controller {1} \
|
||||
CONFIG.Phy_Only {Complete_Memory_Controller} \
|
||||
CONFIG.C0.DDR4_PhyClockRatio {4:1} \
|
||||
CONFIG.C0.DDR4_TimePeriod {1200} \
|
||||
CONFIG.C0.DDR4_MemoryPart {MT40A256M16GE-083E} \
|
||||
CONFIG.C0.DDR4_BurstLength {8} \
|
||||
CONFIG.C0.DDR4_BurstType {Sequential} \
|
||||
CONFIG.C0.DDR4_CasLatency {13} \
|
||||
CONFIG.C0.DDR4_CasWriteLatency {10} \
|
||||
CONFIG.C0.DDR4_Slot {Single} \
|
||||
CONFIG.C0.DDR4_MemoryVoltage {1.2V} \
|
||||
CONFIG.C0.DDR4_DataWidth {64} \
|
||||
CONFIG.C0.DDR4_DataMask {DM_NO_DBI} \
|
||||
CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK} \
|
||||
CONFIG.C0.DDR4_Ordering {Normal} \
|
||||
CONFIG.C0.DDR4_Ecc {false} \
|
||||
CONFIG.C0.DDR4_AUTO_AP_COL_A3 {false} \
|
||||
CONFIG.C0.DDR4_AutoPrecharge {false} \
|
||||
CONFIG.C0.DDR4_UserRefresh_ZQCS {false} \
|
||||
CONFIG.C0.DDR4_AxiDataWidth {64} \
|
||||
CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} \
|
||||
CONFIG.C0.DDR4_AxiIDWidth {4} \
|
||||
CONFIG.C0.DDR4_AxiAddressWidth {31} \
|
||||
CONFIG.C0.DDR4_AxiNarrowBurst {false} \
|
||||
CONFIG.C0.DDR4_CLKFBOUT_MULT {5} \
|
||||
CONFIG.C0.DDR4_DIVCLK_DIVIDE {1} \
|
||||
CONFIG.C0.DDR4_CLKOUT0_DIVIDE {6} \
|
||||
CONFIG.Reference_Clock {Differential} \
|
||||
CONFIG.ADDN_UI_CLKOUT1.INSERT_VIP {0} \
|
||||
CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {22} \
|
||||
CONFIG.ADDN_UI_CLKOUT2.INSERT_VIP {0} \
|
||||
CONFIG.ADDN_UI_CLKOUT2_FREQ_HZ {208} \
|
||||
CONFIG.ADDN_UI_CLKOUT3.INSERT_VIP {0} \
|
||||
CONFIG.ADDN_UI_CLKOUT3_FREQ_HZ {None} \
|
||||
CONFIG.ADDN_UI_CLKOUT4.INSERT_VIP {0} \
|
||||
CONFIG.ADDN_UI_CLKOUT4_FREQ_HZ {None} \
|
||||
CONFIG.Debug_Signal {Disable} \
|
||||
CONFIG.MCS_DBG_EN {false} \
|
||||
CONFIG.C0.DDR4_MCS_ECC {false} \
|
||||
CONFIG.Simulation_Mode {BFM} \
|
||||
CONFIG.Example_TG {SIMPLE_TG} \
|
||||
CONFIG.C0.DDR4_SELF_REFRESH {false} \
|
||||
CONFIG.RECONFIG_XSDB_SAVE_RESTORE {false} \
|
||||
CONFIG.C0.DDR4_SAVE_RESTORE {false} \
|
||||
CONFIG.C0.DDR4_RESTORE_CRC {false} \
|
||||
CONFIG.C0.MIGRATION {false} \
|
||||
CONFIG.AL_SEL {0} \
|
||||
CONFIG.C0.ADDR_WIDTH {17} \
|
||||
CONFIG.C0.BANK_GROUP_WIDTH {1} \
|
||||
CONFIG.C0.CKE_WIDTH {1} \
|
||||
CONFIG.C0.CK_WIDTH {1} \
|
||||
CONFIG.C0.CS_WIDTH {1} \
|
||||
CONFIG.C0.DDR4_ACT_SKEW {0} \
|
||||
CONFIG.C0.DDR4_ADDR_SKEW_0 {0} \
|
||||
CONFIG.C0.DDR4_ADDR_SKEW_1 {0} \
|
||||
CONFIG.C0.DDR4_ADDR_SKEW_2 {0} \
|
||||
CONFIG.C0.DDR4_ADDR_SKEW_3 {0} \
|
||||
CONFIG.C0.DDR4_ADDR_SKEW_4 {0} \
|
||||
CONFIG.C0.DDR4_ADDR_SKEW_5 {0} \
|
||||
CONFIG.C0.DDR4_ADDR_SKEW_6 {0} \
|
||||
CONFIG.C0.DDR4_ADDR_SKEW_7 {0} \
|
||||
CONFIG.C0.DDR4_ADDR_SKEW_8 {0} \
|
||||
CONFIG.C0.DDR4_ADDR_SKEW_9 {0} \
|
||||
CONFIG.C0.DDR4_ADDR_SKEW_10 {0} \
|
||||
CONFIG.C0.DDR4_ADDR_SKEW_11 {0} \
|
||||
CONFIG.C0.DDR4_ADDR_SKEW_12 {0} \
|
||||
CONFIG.C0.DDR4_ADDR_SKEW_13 {0} \
|
||||
CONFIG.C0.DDR4_ADDR_SKEW_14 {0} \
|
||||
CONFIG.C0.DDR4_ADDR_SKEW_15 {0} \
|
||||
CONFIG.C0.DDR4_ADDR_SKEW_16 {0} \
|
||||
CONFIG.C0.DDR4_ADDR_SKEW_17 {0} \
|
||||
CONFIG.C0.DDR4_AxiSelection {true} \
|
||||
CONFIG.C0.DDR4_BA_SKEW_0 {0} \
|
||||
CONFIG.C0.DDR4_BA_SKEW_1 {0} \
|
||||
CONFIG.C0.DDR4_BG_SKEW_0 {0} \
|
||||
CONFIG.C0.DDR4_BG_SKEW_1 {0} \
|
||||
CONFIG.C0.DDR4_CKE_SKEW_0 {0} \
|
||||
CONFIG.C0.DDR4_CKE_SKEW_1 {0} \
|
||||
CONFIG.C0.DDR4_CKE_SKEW_2 {0} \
|
||||
CONFIG.C0.DDR4_CKE_SKEW_3 {0} \
|
||||
CONFIG.C0.DDR4_CK_SKEW_0 {0} \
|
||||
CONFIG.C0.DDR4_CK_SKEW_1 {0} \
|
||||
CONFIG.C0.DDR4_CK_SKEW_2 {0} \
|
||||
CONFIG.C0.DDR4_CK_SKEW_3 {0} \
|
||||
CONFIG.C0.DDR4_CS_SKEW_0 {0} \
|
||||
CONFIG.C0.DDR4_CS_SKEW_1 {0} \
|
||||
CONFIG.C0.DDR4_CS_SKEW_2 {0} \
|
||||
CONFIG.C0.DDR4_CS_SKEW_3 {0} \
|
||||
CONFIG.C0.DDR4_Capacity {512} \
|
||||
CONFIG.C0.DDR4_ChipSelect {true} \
|
||||
CONFIG.C0.DDR4_Clamshell {false} \
|
||||
CONFIG.C0.DDR4_CustomParts {no_file_loaded} \
|
||||
CONFIG.C0.DDR4_EN_PARITY {false} \
|
||||
CONFIG.C0.DDR4_Enable_LVAUX {false} \
|
||||
CONFIG.C0.DDR4_InputClockPeriod {3359} \
|
||||
CONFIG.C0.DDR4_LR_SKEW_0 {0} \
|
||||
CONFIG.C0.DDR4_LR_SKEW_1 {0} \
|
||||
CONFIG.C0.DDR4_MemoryName {MainMemory} \
|
||||
CONFIG.C0.DDR4_ODT_SKEW_0 {0} \
|
||||
CONFIG.C0.DDR4_ODT_SKEW_1 {0} \
|
||||
CONFIG.C0.DDR4_ODT_SKEW_2 {0} \
|
||||
CONFIG.C0.DDR4_ODT_SKEW_3 {0} \
|
||||
CONFIG.C0.DDR4_OnDieTermination {RZQ/6} \
|
||||
CONFIG.C0.DDR4_PAR_SKEW {0} \
|
||||
CONFIG.C0.DDR4_Specify_MandD {false} \
|
||||
CONFIG.C0.DDR4_TREFI {0} \
|
||||
CONFIG.C0.DDR4_TRFC {0} \
|
||||
CONFIG.C0.DDR4_TRFC_DLR {0} \
|
||||
CONFIG.C0.DDR4_TXPR {0} \
|
||||
CONFIG.C0.DDR4_isCKEShared {false} \
|
||||
CONFIG.C0.DDR4_isCustom {false} \
|
||||
CONFIG.C0.DDR4_nCK_TREFI {0} \
|
||||
CONFIG.C0.DDR4_nCK_TRFC {0} \
|
||||
CONFIG.C0.DDR4_nCK_TRFC_DLR {0} \
|
||||
CONFIG.C0.DDR4_nCK_TXPR {5} \
|
||||
CONFIG.C0.LR_WIDTH {1} \
|
||||
CONFIG.C0.ODT_WIDTH {1} \
|
||||
CONFIG.C0.StackHeight {1} \
|
||||
CONFIG.C0_CLOCK_BOARD_INTERFACE {default_sysclk1_300} \
|
||||
CONFIG.C0_DDR4_ARESETN.INSERT_VIP {0} \
|
||||
CONFIG.C0_DDR4_BOARD_INTERFACE {Custom} \
|
||||
CONFIG.C0_DDR4_CLOCK.INSERT_VIP {0} \
|
||||
CONFIG.C0_DDR4_RESET.INSERT_VIP {0} \
|
||||
CONFIG.C0_DDR4_S_AXI.INSERT_VIP {0} \
|
||||
CONFIG.C0_SYS_CLK_I.INSERT_VIP {0} \
|
||||
CONFIG.CLKOUT6 {0} \
|
||||
CONFIG.DCI_Cascade {false} \
|
||||
CONFIG.DIFF_TERM_SYSCLK {false} \
|
||||
CONFIG.Default_Bank_Selections {false} \
|
||||
CONFIG.EN_PP_4R_MIR {false} \
|
||||
CONFIG.Enable_SysPorts {true} \
|
||||
CONFIG.IOPowerReduction {OFF} \
|
||||
CONFIG.IO_Power_Reduction {false} \
|
||||
CONFIG.IS_FROM_PHY {1} \
|
||||
CONFIG.PARTIAL_RECONFIG_FLOW_MIG {false} \
|
||||
CONFIG.PING_PONG_PHY {1} \
|
||||
CONFIG.RESET_BOARD_INTERFACE {reset} \
|
||||
CONFIG.SET_DW_TO_40 {false} \
|
||||
CONFIG.SYSTEM_RESET.INSERT_VIP {0} \
|
||||
CONFIG.System_Clock {Differential} \
|
||||
CONFIG.TIMING_3DS {false} \
|
||||
CONFIG.TIMING_OP1 {false} \
|
||||
CONFIG.TIMING_OP2 {false} \
|
||||
] [get_ips $ipName]
|
||||
|
||||
generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
|
||||
generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
|
||||
create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
|
||||
launch_run -jobs 8 ${ipName}_synth_1
|
||||
wait_on_run ${ipName}_synth_1
|
||||
@ -1,162 +0,0 @@
|
||||
|
||||
set partNumber $::env(XILINX_PART)
|
||||
set boardName $::env(XILINX_BOARD)
|
||||
#set partNumber xcvu9p-flga2104-2L-e
|
||||
#set boardName xilinx.com:vcu118:part0:2.4
|
||||
|
||||
set ipName xlnx_ddr4
|
||||
|
||||
create_project $ipName . -force -part $partNumber
|
||||
set_property board_part $boardName [current_project]
|
||||
|
||||
# really just these two lines which change
|
||||
create_ip -name ddr4 -vendor xilinx.com -library ip -module_name $ipName
|
||||
set_property -dict [list CONFIG.C0.ControllerType {DDR4_SDRAM} \
|
||||
CONFIG.No_Controller {1} \
|
||||
CONFIG.Phy_Only {Complete_Memory_Controller} \
|
||||
CONFIG.C0.DDR4_PhyClockRatio {4:1} \
|
||||
CONFIG.C0.DDR4_TimePeriod {833} \
|
||||
CONFIG.C0.DDR4_MemoryPart {MT40A256M16GE-083E} \
|
||||
CONFIG.C0.DDR4_BurstLength {8} \
|
||||
CONFIG.C0.DDR4_BurstType {Sequential} \
|
||||
CONFIG.C0.DDR4_CasLatency {16} \
|
||||
CONFIG.C0.DDR4_CasWriteLatency {12} \
|
||||
CONFIG.C0.DDR4_Slot {Single} \
|
||||
CONFIG.C0.DDR4_MemoryVoltage {1.2V} \
|
||||
CONFIG.C0.DDR4_DataWidth {64} \
|
||||
CONFIG.C0.DDR4_DataMask {DM_NO_DBI} \
|
||||
CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK} \
|
||||
CONFIG.C0.DDR4_Ordering {Normal} \
|
||||
CONFIG.C0.DDR4_Ecc {false} \
|
||||
CONFIG.C0.DDR4_AUTO_AP_COL_A3 {false} \
|
||||
CONFIG.C0.DDR4_AutoPrecharge {false} \
|
||||
CONFIG.C0.DDR4_UserRefresh_ZQCS {false} \
|
||||
CONFIG.C0.DDR4_AxiDataWidth {64} \
|
||||
CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} \
|
||||
CONFIG.C0.DDR4_AxiIDWidth {4} \
|
||||
CONFIG.C0.DDR4_AxiAddressWidth {31} \
|
||||
CONFIG.C0.DDR4_AxiNarrowBurst {false} \
|
||||
CONFIG.Reference_Clock {Differential} \
|
||||
CONFIG.ADDN_UI_CLKOUT1.INSERT_VIP {0} \
|
||||
CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {38} \
|
||||
CONFIG.ADDN_UI_CLKOUT2.INSERT_VIP {0} \
|
||||
CONFIG.ADDN_UI_CLKOUT2_FREQ_HZ {300} \
|
||||
CONFIG.ADDN_UI_CLKOUT3.INSERT_VIP {0} \
|
||||
CONFIG.ADDN_UI_CLKOUT3_FREQ_HZ {None} \
|
||||
CONFIG.ADDN_UI_CLKOUT4.INSERT_VIP {0} \
|
||||
CONFIG.ADDN_UI_CLKOUT4_FREQ_HZ {None} \
|
||||
CONFIG.Debug_Signal {Disable} \
|
||||
CONFIG.MCS_DBG_EN {false} \
|
||||
CONFIG.C0.DDR4_MCS_ECC {false} \
|
||||
CONFIG.Simulation_Mode {BFM} \
|
||||
CONFIG.Example_TG {SIMPLE_TG} \
|
||||
CONFIG.C0.DDR4_SELF_REFRESH {false} \
|
||||
CONFIG.RECONFIG_XSDB_SAVE_RESTORE {false} \
|
||||
CONFIG.C0.DDR4_SAVE_RESTORE {false} \
|
||||
CONFIG.C0.DDR4_RESTORE_CRC {false} \
|
||||
CONFIG.C0.MIGRATION {false} \
|
||||
CONFIG.AL_SEL {0} \
|
||||
CONFIG.C0.ADDR_WIDTH {17} \
|
||||
CONFIG.C0.BANK_GROUP_WIDTH {1} \
|
||||
CONFIG.C0.CKE_WIDTH {1} \
|
||||
CONFIG.C0.CK_WIDTH {1} \
|
||||
CONFIG.C0.CS_WIDTH {1} \
|
||||
CONFIG.C0.DDR4_ACT_SKEW {0} \
|
||||
CONFIG.C0.DDR4_ADDR_SKEW_0 {0} \
|
||||
CONFIG.C0.DDR4_ADDR_SKEW_1 {0} \
|
||||
CONFIG.C0.DDR4_ADDR_SKEW_2 {0} \
|
||||
CONFIG.C0.DDR4_ADDR_SKEW_3 {0} \
|
||||
CONFIG.C0.DDR4_ADDR_SKEW_4 {0} \
|
||||
CONFIG.C0.DDR4_ADDR_SKEW_5 {0} \
|
||||
CONFIG.C0.DDR4_ADDR_SKEW_6 {0} \
|
||||
CONFIG.C0.DDR4_ADDR_SKEW_7 {0} \
|
||||
CONFIG.C0.DDR4_ADDR_SKEW_8 {0} \
|
||||
CONFIG.C0.DDR4_ADDR_SKEW_9 {0} \
|
||||
CONFIG.C0.DDR4_ADDR_SKEW_10 {0} \
|
||||
CONFIG.C0.DDR4_ADDR_SKEW_11 {0} \
|
||||
CONFIG.C0.DDR4_ADDR_SKEW_12 {0} \
|
||||
CONFIG.C0.DDR4_ADDR_SKEW_13 {0} \
|
||||
CONFIG.C0.DDR4_ADDR_SKEW_14 {0} \
|
||||
CONFIG.C0.DDR4_ADDR_SKEW_15 {0} \
|
||||
CONFIG.C0.DDR4_ADDR_SKEW_16 {0} \
|
||||
CONFIG.C0.DDR4_ADDR_SKEW_17 {0} \
|
||||
CONFIG.C0.DDR4_AxiSelection {true} \
|
||||
CONFIG.C0.DDR4_BA_SKEW_0 {0} \
|
||||
CONFIG.C0.DDR4_BA_SKEW_1 {0} \
|
||||
CONFIG.C0.DDR4_BG_SKEW_0 {0} \
|
||||
CONFIG.C0.DDR4_BG_SKEW_1 {0} \
|
||||
CONFIG.C0.DDR4_CKE_SKEW_0 {0} \
|
||||
CONFIG.C0.DDR4_CKE_SKEW_1 {0} \
|
||||
CONFIG.C0.DDR4_CKE_SKEW_2 {0} \
|
||||
CONFIG.C0.DDR4_CKE_SKEW_3 {0} \
|
||||
CONFIG.C0.DDR4_CK_SKEW_0 {0} \
|
||||
CONFIG.C0.DDR4_CK_SKEW_1 {0} \
|
||||
CONFIG.C0.DDR4_CK_SKEW_2 {0} \
|
||||
CONFIG.C0.DDR4_CK_SKEW_3 {0} \
|
||||
CONFIG.C0.DDR4_CS_SKEW_0 {0} \
|
||||
CONFIG.C0.DDR4_CS_SKEW_1 {0} \
|
||||
CONFIG.C0.DDR4_CS_SKEW_2 {0} \
|
||||
CONFIG.C0.DDR4_CS_SKEW_3 {0} \
|
||||
CONFIG.C0.DDR4_Capacity {512} \
|
||||
CONFIG.C0.DDR4_ChipSelect {true} \
|
||||
CONFIG.C0.DDR4_Clamshell {false} \
|
||||
CONFIG.C0.DDR4_CustomParts {no_file_loaded} \
|
||||
CONFIG.C0.DDR4_EN_PARITY {false} \
|
||||
CONFIG.C0.DDR4_Enable_LVAUX {false} \
|
||||
CONFIG.C0.DDR4_InputClockPeriod {4000} \
|
||||
CONFIG.C0.DDR4_LR_SKEW_0 {0} \
|
||||
CONFIG.C0.DDR4_LR_SKEW_1 {0} \
|
||||
CONFIG.C0.DDR4_MemoryName {MainMemory} \
|
||||
CONFIG.C0.DDR4_ODT_SKEW_0 {0} \
|
||||
CONFIG.C0.DDR4_ODT_SKEW_1 {0} \
|
||||
CONFIG.C0.DDR4_ODT_SKEW_2 {0} \
|
||||
CONFIG.C0.DDR4_ODT_SKEW_3 {0} \
|
||||
CONFIG.C0.DDR4_OnDieTermination {RZQ/6} \
|
||||
CONFIG.C0.DDR4_OutputDriverImpedenceControl {RZQ/7} \
|
||||
CONFIG.C0.DDR4_PAR_SKEW {0} \
|
||||
CONFIG.C0.DDR4_Specify_MandD {false} \
|
||||
CONFIG.C0.DDR4_TREFI {0} \
|
||||
CONFIG.C0.DDR4_TRFC {0} \
|
||||
CONFIG.C0.DDR4_TRFC_DLR {0} \
|
||||
CONFIG.C0.DDR4_TXPR {0} \
|
||||
CONFIG.C0.DDR4_isCKEShared {false} \
|
||||
CONFIG.C0.DDR4_isCustom {false} \
|
||||
CONFIG.C0.DDR4_nCK_TREFI {0} \
|
||||
CONFIG.C0.DDR4_nCK_TRFC {0} \
|
||||
CONFIG.C0.DDR4_nCK_TRFC_DLR {0} \
|
||||
CONFIG.C0.DDR4_nCK_TXPR {5} \
|
||||
CONFIG.C0.LR_WIDTH {1} \
|
||||
CONFIG.C0.ODT_WIDTH {1} \
|
||||
CONFIG.C0.StackHeight {1} \
|
||||
CONFIG.C0_CLOCK_BOARD_INTERFACE {default_250mhz_clk1} \
|
||||
CONFIG.C0_DDR4_ARESETN.INSERT_VIP {0} \
|
||||
CONFIG.C0_DDR4_BOARD_INTERFACE {Custom} \
|
||||
CONFIG.C0_DDR4_CLOCK.INSERT_VIP {0} \
|
||||
CONFIG.C0_DDR4_RESET.INSERT_VIP {0} \
|
||||
CONFIG.C0_DDR4_S_AXI.INSERT_VIP {0} \
|
||||
CONFIG.C0_SYS_CLK_I.INSERT_VIP {0} \
|
||||
CONFIG.CLKOUT6 {0} \
|
||||
CONFIG.DCI_Cascade {false} \
|
||||
CONFIG.DIFF_TERM_SYSCLK {false} \
|
||||
CONFIG.Default_Bank_Selections {false} \
|
||||
CONFIG.EN_PP_4R_MIR {false} \
|
||||
CONFIG.Enable_SysPorts {true} \
|
||||
CONFIG.IOPowerReduction {OFF} \
|
||||
CONFIG.IO_Power_Reduction {false} \
|
||||
CONFIG.IS_FROM_PHY {1} \
|
||||
CONFIG.PARTIAL_RECONFIG_FLOW_MIG {false} \
|
||||
CONFIG.PING_PONG_PHY {1} \
|
||||
CONFIG.RESET_BOARD_INTERFACE {reset} \
|
||||
CONFIG.SET_DW_TO_40 {false} \
|
||||
CONFIG.SYSTEM_RESET.INSERT_VIP {0} \
|
||||
CONFIG.System_Clock {Differential} \
|
||||
CONFIG.TIMING_3DS {false} \
|
||||
CONFIG.TIMING_OP1 {false} \
|
||||
CONFIG.TIMING_OP2 {false} \
|
||||
] [get_ips $ipName]
|
||||
|
||||
generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
|
||||
generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
|
||||
create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
|
||||
launch_run -jobs 8 ${ipName}_synth_1
|
||||
wait_on_run ${ipName}_synth_1
|
||||
@ -1,9 +1,8 @@
|
||||
|
||||
#set partNumber $::env(XILINX_PART)
|
||||
#set boardNmae $::env(XILINX_BOARD)
|
||||
set partNumber xcvu095-ffva2104-2-e
|
||||
set boardName xilinx.com:vcu108:part0:1.2
|
||||
|
||||
set partNumber xcvu9p-flga2104-2L-e
|
||||
set boardName xilinx.com:vcu118:part0:2.4
|
||||
|
||||
set ipName xlnx_ddr4
|
||||
|
||||
@ -42,7 +41,7 @@ set_property -dict [list CONFIG.C0.ControllerType {DDR4_SDRAM} \
|
||||
CONFIG.C0.DDR4_CLKOUT0_DIVIDE {6} \
|
||||
CONFIG.Reference_Clock {Differential} \
|
||||
CONFIG.ADDN_UI_CLKOUT1.INSERT_VIP {0} \
|
||||
CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {22} \
|
||||
CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {30} \
|
||||
CONFIG.ADDN_UI_CLKOUT2.INSERT_VIP {0} \
|
||||
CONFIG.ADDN_UI_CLKOUT2_FREQ_HZ {208} \
|
||||
CONFIG.ADDN_UI_CLKOUT3.INSERT_VIP {0} \
|
||||
@ -107,7 +106,7 @@ set_property -dict [list CONFIG.C0.ControllerType {DDR4_SDRAM} \
|
||||
CONFIG.C0.DDR4_CustomParts {no_file_loaded} \
|
||||
CONFIG.C0.DDR4_EN_PARITY {false} \
|
||||
CONFIG.C0.DDR4_Enable_LVAUX {false} \
|
||||
CONFIG.C0.DDR4_InputClockPeriod {3359} \
|
||||
CONFIG.C0.DDR4_InputClockPeriod {4000} \
|
||||
CONFIG.C0.DDR4_LR_SKEW_0 {0} \
|
||||
CONFIG.C0.DDR4_LR_SKEW_1 {0} \
|
||||
CONFIG.C0.DDR4_MemoryName {MainMemory} \
|
||||
@ -116,6 +115,7 @@ set_property -dict [list CONFIG.C0.ControllerType {DDR4_SDRAM} \
|
||||
CONFIG.C0.DDR4_ODT_SKEW_2 {0} \
|
||||
CONFIG.C0.DDR4_ODT_SKEW_3 {0} \
|
||||
CONFIG.C0.DDR4_OnDieTermination {RZQ/6} \
|
||||
CONFIG.C0.DDR4_OutputDriverImpedenceControl {RZQ/7} \
|
||||
CONFIG.C0.DDR4_PAR_SKEW {0} \
|
||||
CONFIG.C0.DDR4_Specify_MandD {false} \
|
||||
CONFIG.C0.DDR4_TREFI {0} \
|
||||
@ -131,7 +131,7 @@ set_property -dict [list CONFIG.C0.ControllerType {DDR4_SDRAM} \
|
||||
CONFIG.C0.LR_WIDTH {1} \
|
||||
CONFIG.C0.ODT_WIDTH {1} \
|
||||
CONFIG.C0.StackHeight {1} \
|
||||
CONFIG.C0_CLOCK_BOARD_INTERFACE {default_sysclk1_300} \
|
||||
CONFIG.C0_CLOCK_BOARD_INTERFACE {default_250mhz_clk1} \
|
||||
CONFIG.C0_DDR4_ARESETN.INSERT_VIP {0} \
|
||||
CONFIG.C0_DDR4_BOARD_INTERFACE {Custom} \
|
||||
CONFIG.C0_DDR4_CLOCK.INSERT_VIP {0} \
|
||||
|
||||
@ -1,26 +0,0 @@
|
||||
set partNumber $::env(XILINX_PART)
|
||||
set boardName $::env(XILINX_BOARD)
|
||||
|
||||
set ipName xlnx_mmcm
|
||||
|
||||
create_project $ipName . -force -part $partNumber
|
||||
set_property board_part $boardName [current_project]
|
||||
|
||||
create_ip -name clk_wiz -vendor xilinx.com -library ip -module_name $ipName
|
||||
|
||||
set_property -dict [list CONFIG.PRIM_IN_FREQ {100.000} \
|
||||
CONFIG.NUM_OUT_CLKS {3} \
|
||||
CONFIG.CLKOUT2_USED {true} \
|
||||
CONFIG.CLKOUT3_USED {true} \
|
||||
CONFIG.CLKOUT4_USED {false} \
|
||||
CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {166.66667} \
|
||||
CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {200} \
|
||||
CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {15} \
|
||||
CONFIG.CLKIN1_JITTER_PS {10.0} \
|
||||
] [get_ips $ipName]
|
||||
|
||||
generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
|
||||
generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
|
||||
create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
|
||||
launch_run -jobs 8 ${ipName}_synth_1
|
||||
wait_on_run ${ipName}_synth_1
|
||||
@ -1,15 +1,13 @@
|
||||
|
||||
set partNumber $::env(XILINX_PART)
|
||||
set boardName $::env(XILINX_BOARD)
|
||||
#set partNumber xcvu9p-flga2104-2L-e
|
||||
#set boardName xilinx.com:vcu118:part0:2.4
|
||||
#set partNumber $::env(XILINX_PART)
|
||||
#set boardNmae $::env(XILINX_BOARD)
|
||||
set partNumber xcvu9p-flga2104-2L-e
|
||||
set boardName xilinx.com:vcu118:part0:2.4
|
||||
|
||||
set ipName xlnx_proc_sys_reset
|
||||
|
||||
create_project $ipName . -force -part $partNumber
|
||||
if {$boardName!="ArtyA7"} {
|
||||
set_property board_part $boardName [current_project]
|
||||
}
|
||||
set_property board_part $boardName [current_project]
|
||||
|
||||
# really just these two lines which change
|
||||
create_ip -name proc_sys_reset -vendor xilinx.com -library ip -module_name $ipName
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue
Block a user