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Initial commit with nonfunctional and unwritter SPI
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pipelined/src/uncore/spi_apb.sv
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84
pipelined/src/uncore/spi_apb.sv
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///////////////////////////////////////////
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// gpio_apb.sv
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//
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// Written: Nicholas Lucio 18. Sep. 2022
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// Modified:
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//
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// Purpose: Serial Peripheral Interface peripheral
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// See FE310-G002-Manual-v19p05 for specifications
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// MIT LICENSE
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this
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// software and associated documentation files (the "Software"), to deal in the Software
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// without restriction, including without limitation the rights to use, copy, modify, merge,
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// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
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// to whom the Software is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or
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// substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
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// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
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// OR OTHER DEALINGS IN THE SOFTWARE.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module spi_apb (
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input logic PCLK, PRESETn,
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input logic PSEL,
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input logic [7:0] PADDR,
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input logic [`XLEN-1:0] PWDATA,
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input logic [`XLEN/8-1:0] PSTRB,
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input logic PWRITE,
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input logic PENABLE,
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output logic [`XLEN-1:0] PRDATA,
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output logic PREADY,
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input logic [31:0] iof0, iof1,
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input logic [31:0] GPIOPinsIn,
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output logic [31:0] GPIOPinsOut, GPIOPinsEn,
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output logic GPIOIntr);
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logic [11:0] sckdiv;
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logic [1:0] sckmode;
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logic [31:0] csid, csdef, csmode;
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logic [23:0] delay0, delay1;
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logic [19:0] fmt;
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logic [31:0] txdata, rxdata;
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logic [2:0] txmark, rxmark;
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logic [1:0] ie, ip;
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logic fctrl;
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logic [31:0] ffmt;
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logic [7:0] entry;
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logic [31:0] Din, Dout;
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logic memwrite;
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// APB I/O
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assign entry = {PADDR[7:2],2'b00}; // 32-bit word-aligned accesses
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assign memwrite = PWRITE & PENABLE & PSEL; // only write in access phase
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assign PREADY = 1'b1; // GPIO never takes >1 cycle to respond
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// account for subword read/write circuitry
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// -- Note SPI registers are 32 bits no matter what; access them with LW SW.
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// (At least that's what I think when FE310 spec says "only naturally aligned 32-bit accesses are supported")
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if (`XLEN == 64) begin
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assign Din = entry[2] ? PWDATA[63:32] : PWDATA[31:0];
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assign PRDATA = entry[2] ? {Dout,32'b0} : {32'b0,Dout};
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end else begin // 32-bit
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assign Din = PWDATA[31:0];
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assign PRDATA = Dout;
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end
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endmodule
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