Ross Thompson
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9d5a7281b8
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Modified ram_ahb to work with different latencies.
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2022-09-04 14:46:15 -05:00 |
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Ross Thompson
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fcd1465de1
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Renamed AHBCachebusdp to abhcacheinterface.
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2022-08-31 14:12:19 -05:00 |
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Ross Thompson
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5b8f888e21
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Maybe fixed it?
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2022-08-30 18:08:34 -05:00 |
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Ross Thompson
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ccb3e9e24e
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Updates to wave file.
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2022-08-30 17:34:36 -05:00 |
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Ross Thompson
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96793d15c0
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more progress.
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2022-08-30 17:32:32 -05:00 |
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Ross Thompson
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2d6a6c6e44
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Temporary commit.
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2022-08-30 15:40:42 -05:00 |
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Ross Thompson
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63a824cca1
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More progress.
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2022-08-30 15:27:19 -05:00 |
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Ross Thompson
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a532eb61ba
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Progress.
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2022-08-30 14:17:00 -05:00 |
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Ross Thompson
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5cc4f1f1cd
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Added generate around uncore.
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2022-08-25 10:35:24 -05:00 |
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Ross Thompson
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1e1646da90
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Added generate around ebu.
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2022-08-25 09:24:13 -05:00 |
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Ross Thompson
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5301444a61
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Changed signal names.
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2022-08-17 16:12:04 -05:00 |
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Ross Thompson
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334008630f
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Overlapped read fetch line end with eviction write line start. I'm a bit concerned this is not well tested.
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2022-07-24 01:20:29 -05:00 |
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Ross Thompson
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e12e6c3acd
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Added more i-cache signals to wave file.
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2022-07-24 00:24:13 -05:00 |
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Ross Thompson
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0f586c9ed3
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Possible improvement to cache which removes the cpu_busy states.
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2022-07-22 23:20:37 -05:00 |
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Ross Thompson
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6c8ac7851e
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Reverted to fetched the demand cache line first then doing the eviction. This is important because of an optimization in the replacement policy. The replacement policy updates the LRU 1 cycle late and reads the LRU 1 cycle late for critical path timing. This means doing the eviction first requires an initial 1 cycle delay but this delay has to be applied to all misses because we don't know if an eviction is required. Since reading the demand line first is logically ok so long as it is not written to the sram until after the eviction.
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2022-07-19 22:42:25 -05:00 |
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Ross Thompson
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ffda64587c
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Merged together the cache speed updates with the cache sram changes. The fstore2 changes still need to be added.
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2022-07-18 23:37:18 -05:00 |
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slmnemo
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ec7cdee0f3
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Merge branch 'main' into cacheburstmode
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2022-06-09 17:51:03 -07:00 |
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David Harris
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dd4fa7c682
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qslc_r4a2 generator
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2022-06-09 17:26:47 +00:00 |
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slmnemo
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e17ee3073e
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Fixed ifu displaying LSU bus state in wave.do
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2022-06-08 15:30:32 -07:00 |
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DTowersM
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0de54a01bf
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removed delapidated signals SIE_REGW SIP_REGW TimerIntM SwIntM
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2022-05-31 20:10:56 +00:00 |
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bbracker
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9d26bfe71d
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expand WALLY-PERIPH test to use SEIP on PLIC context 1
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2022-03-31 18:02:06 -07:00 |
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bbracker
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e9e827c83e
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add CSRs to waveview
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2022-03-02 18:31:10 +00:00 |
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bbracker
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202bd2f8f8
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change UART PLIC IRQ mapping from 4 to 10 to match virt model; move WALLY-PERIPH tests to wally arch tests
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2022-02-22 03:46:08 +00:00 |
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Ross Thompson
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4cfb601dc8
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Fixed a bunch of the virtual memory changes. Now supports atomic update of PTE in memory concurrent with TLB.
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2022-02-17 10:04:18 -06:00 |
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Ross Thompson
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565ca4e4a3
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Broken state. address translation not working after changes to hptw to support atomic updates to PT.
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2022-02-16 23:37:36 -06:00 |
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Ross Thompson
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1d7949513d
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More cache cleanup.
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2022-02-13 15:47:27 -06:00 |
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Ross Thompson
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7ffbc6b2ab
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Changed names of signals in cache.
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2022-02-13 15:06:18 -06:00 |
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Ross Thompson
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9fb612d4ff
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Updated wave files to reflect recent changes.
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2022-02-10 17:52:19 -06:00 |
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David Harris
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a6708ed887
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cache cleanup
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2022-02-03 15:36:11 +00:00 |
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Ross Thompson
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2d827bf8c0
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Added helpful signals to wavefile.
Makefile for tests now creates the function address to name mapping files.
The function name and test name are included in the wave file.
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2022-02-02 10:15:54 -06:00 |
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Ross Thompson
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f055441ecf
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Improved function_radix to not printout warnings when no valid function is found.
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2022-02-01 18:03:09 -06:00 |
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Ross Thompson
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5407b72af9
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Setup the main regression test to be able to handle coremark.
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2022-02-01 17:00:11 -06:00 |
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Ross Thompson
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4422e2f91c
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Repaired wavefile and fixed modelsim warning.
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2022-01-31 12:34:17 -06:00 |
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Ross Thompson
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2e00186eea
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Updated wave.do to match the ifu/lsu changes.
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2022-01-28 14:37:15 -06:00 |
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Ross Thompson
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862bf2faae
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Moved all instr/load/storeamo faults to mmu with the exception of instr misaligned fault.
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2022-01-27 17:11:27 -06:00 |
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David Harris
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07425369fc
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Renamed wallypipelinedhart to wallypipelinedcore
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2022-01-20 16:02:08 +00:00 |
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David Harris
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6febce0001
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Moved Dcache into bus block
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2022-01-15 00:39:07 +00:00 |
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David Harris
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fd13272d4c
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Renamed LSUStall to LSUStallM
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2022-01-15 00:24:16 +00:00 |
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Ross Thompson
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85b5dc08a8
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Fixed support to allow spills and no icache.
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2022-01-12 17:25:16 -06:00 |
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Ross Thompson
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786a772444
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Improve wavefile by adding performance counters.
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2022-01-12 10:53:29 -06:00 |
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Ross Thompson
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73c488914f
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Added icache access and icache miss to performance counters.
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2022-01-09 22:56:56 -06:00 |
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Ross Thompson
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04ea93aa27
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Added performance counters to wavefile.
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2022-01-09 22:42:14 -06:00 |
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Ross Thompson
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ae927e2bc6
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Fixed wavefile.
Converted coremark to use elf2hex.
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2022-01-09 22:03:10 -06:00 |
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Ross Thompson
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75788dd9c2
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Changes to wave file.
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2022-01-05 14:16:59 -06:00 |
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Ross Thompson
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06168e67e4
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Switched block for line in caches.
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2022-01-04 22:08:18 -06:00 |
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David Harris
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b36ace221e
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Renamed wally-pipelined to pipelined
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2022-01-04 19:47:41 +00:00 |
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