6 Commits

Author	SHA1	Message	Date
Ross Thompson	f2628494e3	Missed constraints file for xilinx ILA.	2021-12-12 15:06:29 -06:00
Ross Thompson	c3c9c327b7	Fixed more constraint issues in fpga. ... Added back in the ILA. Design does not work yet. Stil having issues with order of automatic clock and I/O constraint ordering. Added back in the preload for the boottim.	2021-12-05 15:14:18 -06:00
Ross Thompson	5b4ff4526e	Fixed a bunch of fpga issues.	2021-12-03 17:47:54 -06:00
Ross Thompson	96fb3acefd	Constraints for fpga are still wrong.	2021-12-02 14:23:21 -06:00
Ross Thompson	0d47749cb5	Separated timing constraints from ILA.	2021-12-01 18:15:04 -06:00
Ross Thompson	e94fb2aaec	Got fpga synthesis running from scripts.	2021-12-01 16:59:04 -06:00