11 Commits

Author	SHA1	Message	Date
David Harris	865d5ce0b1	Renamed dtim->ram and boottim ->bootrom	2021-12-14 13:43:06 -08:00
Kevin	98420cb988	dot stars conversions on the rest of the testbenches	2021-12-12 17:53:26 -08:00
Ross Thompson	74fba4bb06	Moved the test bench modules to a common directory.	2021-07-30 14:16:14 -05:00
David Harris	1ec90a5e1f	Reversed [0:...] with [...:0] in bus widths across the project	2021-06-21 01:17:08 -04:00
David Harris	35c74348a4	allow all size memory access in CLINT; added underscore to peripheral address symbols	2021-06-18 08:05:50 -04:00
Thomas Fleming	3c49fd08f6	Remove imem from testbenches	2021-04-14 20:20:34 -04:00
Domenico Ottolia	6619a5f44f	Add mcause tests to testbench	2021-03-30 17:17:59 -04:00
ushakya22	6b9ae41302	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-03-30 15:25:07 -04:00
Domenico Ottolia	f134b09a97	Fix bugs with privileged tests	2021-03-25 14:06:05 -04:00
Domenico Ottolia	d67e28bf50	re-organize privileged tests to be in rv64p to rv32p folders	2021-03-24 13:51:25 -04:00
Domenico Ottolia	d354cbd37d	Add privileged testbench	2021-03-16 20:28:38 -04:00