17 Commits

Author	SHA1	Message	Date
cturek	06c58f310d	Added mux for integer special case, renamed signals to match pipelined stage	2022-12-16 18:43:49 +00:00
David Harris	7989f449ad	Disabled starting FPU divider when IDIV_ON_FPU = 0	2022-12-16 06:35:29 -08:00
David Harris	4365c99b52	Refactored stalls and flushes, including FDIV flush with FlushE	2022-12-15 10:56:18 -08:00
David Harris	9395414df3	Renamed FPUStallD to FCvtIntStallD	2022-12-02 11:55:23 -08:00
David Harris	d64cd715f9	Renamed DivStartE to IFDivStartE	2022-12-02 11:30:49 -08:00
David Harris	9c1b7e53e4	FPU divider working with execute stage stall	2022-12-02 11:11:53 -08:00
David Harris	bc3b783543	comment cleanup	2022-11-16 10:23:20 -08:00
David Harris	ddba68605e	Renamed DivBusy to FDivBusyE in FPU	2022-11-16 10:13:27 -08:00
David Harris	e008d663f4	Moved DivStartE to fdivsqrtfsm	2022-11-16 10:00:07 -08:00
David Harris	0ce3cc393a	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-11-13 04:23:26 -08:00
David Harris	0502b8ea4d	Comments about division hazards	2022-11-13 04:17:37 -08:00
cturek	ff410cd849	Added integer step counter to fsm	2022-11-11 00:23:25 +00:00
David Harris	fc4146f409	Adding start signals for integer divider to fdivsqrt	2022-09-29 16:30:25 -07:00
David Harris	f87e15388a	commented SpecialCase	2022-09-21 05:02:08 -07:00
David Harris	b21e36a788	Added SpecialCaseReg to hold SpecialCase for fdivsqrtpostproc	2022-09-21 04:55:43 -07:00
David Harris	437fd52bf6	Gated sticky bit in fdiv with SpecialCase	2022-09-20 20:05:00 -07:00
David Harris	8d1408a9d6	Moved fpu modules into subdirectories	2022-09-20 04:12:05 -07:00