forked from Github_Repos/cvw
122 lines
4.2 KiB
Systemverilog
122 lines
4.2 KiB
Systemverilog
///////////////////////////////////////////
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// fdivsqrtfsm.sv
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//
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// Written: David_Harris@hmc.edu, me@KatherineParry.com, cturek@hmc.edu
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// Modified:13 January 2022
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//
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// Purpose: Combined Divide and Square Root Floating Point and Integer Unit
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// MIT LICENSE
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this
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// software and associated documentation files (the "Software"), to deal in the Software
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// without restriction, including without limitation the rights to use, copy, modify, merge,
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// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
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// to whom the Software is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or
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// substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
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// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
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// OR OTHER DEALINGS IN THE SOFTWARE.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module fdivsqrtfsm(
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input logic clk,
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input logic reset,
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input logic [`FMTBITS-1:0] FmtE,
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input logic XInfE, YInfE,
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input logic XZeroE, YZeroE,
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input logic XNaNE, YNaNE,
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input logic DivStart,
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input logic XsE,
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input logic SqrtE,
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input logic StallE,
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input logic StallM,
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input logic WZero,
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output logic DivDone,
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output logic DivBusy
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);
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typedef enum logic [1:0] {IDLE, BUSY, DONE} statetype;
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statetype state;
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logic [`DURLEN-1:0] step;
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logic SpecialCase;
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logic [`DURLEN-1:0] cycles;
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// terminate immediately on special cases
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assign SpecialCase = XZeroE | (YZeroE&~SqrtE) | XInfE | YInfE | XNaNE | YNaNE | (XsE&SqrtE);
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// DIVN = `NF+3
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// NS = NF + 1
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// N = NS or NS+2 for div/sqrt.
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/* verilator lint_off WIDTH */
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logic [`DURLEN+1:0] Nf, fbits; // number of fractional bits
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if (`FPSIZES == 1)
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assign Nf = `NF;
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else if (`FPSIZES == 2)
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always_comb
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case (FmtE)
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1'b0: Nf = `NF1;
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1'b1: Nf = `NF;
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endcase
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else if (`FPSIZES == 3)
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always_comb
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case (FmtE)
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`FMT: Nf = `NF;
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`FMT1: Nf = `NF1;
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`FMT2: Nf = `NF2;
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endcase
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else if (`FPSIZES == 4)
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always_comb
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case(FmtE)
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`S_FMT: Nf = `S_NF;
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`D_FMT: Nf = `D_NF;
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`H_FMT: Nf = `H_NF;
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`Q_FMT: Nf = `Q_NF;
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endcase
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always_comb begin
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if (SqrtE) fbits = Nf + 2 + 2; // Nf + two fractional bits for round/guard + 2 for right shift by up to 2
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else fbits = Nf + 2 + `LOGR; // Nf + two fractional bits for round/guard + integer bits - try this when placing results in msbs
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cycles = (fbits + (`LOGR*`DIVCOPIES)-1)/(`LOGR*`DIVCOPIES);
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end
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/* verilator lint_on WIDTH */
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always_ff @(posedge clk) begin
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if (reset) begin
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state <= #1 IDLE;
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end else if (DivStart&~StallE) begin
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step <= cycles; // *** this should be adjusted to depend on the precision; sqrt should use one fewer step becasue firststep=1
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// $display("Setting Nf = %d fbits %d cycles = %d FmtE %d FPSIZES = %d Q_NF = %d num = %d denom = %d\n", Nf, fbits, cycles, FmtE, `FPSIZES, `Q_NF,
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// (fbits +(`LOGR*`DIVCOPIES)-1), (`LOGR*`DIVCOPIES));
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if (SpecialCase) state <= #1 DONE;
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else state <= #1 BUSY;
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end else if (DivDone) begin
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if (StallM) state <= #1 DONE;
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else state <= #1 IDLE;
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end else if (state == BUSY) begin
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if (step == 1) begin
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state <= #1 DONE;
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end
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step <= step - 1;
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end
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end
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assign DivDone = (state == DONE) | (WZero & (state == BUSY));
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assign DivBusy = (state == BUSY & ~DivDone);
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endmodule |