Kip Macsai-Goren
|
7d1504be89
|
added backup output files for when execution tests are possible
|
2021-07-16 17:25:40 -04:00 |
|
Kip Macsai-Goren
|
d945ba8975
|
removed execution tests until fences are implemented
|
2021-07-16 17:24:59 -04:00 |
|
Ross Thompson
|
c850ae0d99
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2021-07-16 15:59:13 -05:00 |
|
Kip Macsai-Goren
|
4a2da2035e
|
More fixes to bring physical address into dtim range
|
2021-07-16 16:58:28 -04:00 |
|
Ross Thompson
|
0b3dc288ec
|
Made furture progress in the mmu tests.
|
2021-07-16 15:56:06 -05:00 |
|
Kip Macsai-Goren
|
dec15e7b90
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2021-07-16 16:05:50 -04:00 |
|
Ross Thompson
|
698afb0e79
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2021-07-16 15:04:38 -05:00 |
|
Ross Thompson
|
5e18a15a4c
|
Added guide for Ben to do linux conversion.
|
2021-07-16 15:04:30 -05:00 |
|
Kip Macsai-Goren
|
70fa6bca8e
|
removed exectution tests that intentionally fail as well until fences are implemented.
|
2021-07-16 15:47:08 -04:00 |
|
Kip Macsai-Goren
|
6c21c7903a
|
removed execution tests that are supposed to pass until fences are implemented.
|
2021-07-16 15:32:13 -04:00 |
|
Ross Thompson
|
6521d2b468
|
Also changed the shadow ram's dcache copy widths.
Merge branch 'dcache' into main
|
2021-07-16 14:21:09 -05:00 |
|
Ross Thompson
|
1aabee0478
|
Updated the config so the tim has a bigger range.
|
2021-07-16 12:35:00 -05:00 |
|
Ross Thompson
|
b3bf04d474
|
Updated wave file.
|
2021-07-16 12:34:37 -05:00 |
|
Ross Thompson
|
46bce70e42
|
Fixed walker fault interaction with dcache.
|
2021-07-16 12:22:13 -05:00 |
|
bbracker
|
b0fcfc2773
|
reduce number of UART ports to 1
|
2021-07-16 12:42:29 -04:00 |
|
bbracker
|
f9d9d348d6
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2021-07-16 12:27:25 -04:00 |
|
bbracker
|
01ca22af49
|
changed stop of linux boot from arch_cpu_idle to do_idle
|
2021-07-16 12:27:15 -04:00 |
|
Ross Thompson
|
e0f719d513
|
Updated the ptw, lsuarb and dcache to hopefully solve the interlock issues.
|
2021-07-16 11:12:57 -05:00 |
|
bbracker
|
ae7d48c326
|
incremental linux config de-bloating
|
2021-07-16 12:08:58 -04:00 |
|
bbracker
|
40352ab7e4
|
incremental linux config de-bloating
|
2021-07-16 11:33:11 -04:00 |
|
bbracker
|
b1fe4ff295
|
incremental linux config de-bloating
|
2021-07-16 11:15:25 -04:00 |
|
bbracker
|
f34e28d187
|
incremental linux config de-bloating
|
2021-07-16 01:58:21 -04:00 |
|
bbracker
|
3bcc5808d4
|
incremental linux config de-bloating
|
2021-07-16 01:54:36 -04:00 |
|
bbracker
|
ff90e6744c
|
incremental linux config de-bloating
|
2021-07-16 01:43:16 -04:00 |
|
bbracker
|
ca5a1755f3
|
incremental linux config de-bloating
|
2021-07-16 01:33:51 -04:00 |
|
bbracker
|
b003c651be
|
incremental linux config de-bloating
|
2021-07-16 01:25:41 -04:00 |
|
bbracker
|
ae886b015d
|
incremental linux config de-bloating
|
2021-07-16 01:00:12 -04:00 |
|
bbracker
|
7340e089f7
|
incremental linux config de-bloating
|
2021-07-16 00:46:22 -04:00 |
|
bbracker
|
c4716af4d6
|
incremental linux config de-bloating
|
2021-07-16 00:41:18 -04:00 |
|
bbracker
|
0238b869fb
|
incremental linux config de-bloating
|
2021-07-16 00:34:41 -04:00 |
|
bbracker
|
3273b030e1
|
incremental linux config de-bloating
|
2021-07-16 00:16:12 -04:00 |
|
bbracker
|
66bf2005fe
|
incremental linux config de-bloating
|
2021-07-16 00:10:31 -04:00 |
|
bbracker
|
4734f0eee5
|
incremental linux config de-bloating
|
2021-07-15 23:53:15 -04:00 |
|
bbracker
|
e565adfece
|
incremental linux config de-bloating
|
2021-07-15 23:30:24 -04:00 |
|
bbracker
|
3ff723493f
|
incremental linux config de-bloating
|
2021-07-15 23:12:21 -04:00 |
|
bbracker
|
8586462ee5
|
incremental linux config de-bloating
|
2021-07-15 23:00:20 -04:00 |
|
bbracker
|
03e0bdaa5a
|
incremental linux config de-bloating
|
2021-07-15 21:33:52 -04:00 |
|
bbracker
|
e922732fc5
|
incremental linux config de-bloating
|
2021-07-15 20:54:36 -04:00 |
|
Kip Macsai-Goren
|
ca63f6bc48
|
fixed output file to match sv48 test again
|
2021-07-15 18:55:00 -04:00 |
|
bbracker
|
c2535308fd
|
working linux config
|
2021-07-15 18:49:54 -04:00 |
|
Kip Macsai-Goren
|
473ed689a2
|
fixed another address to be in tim range
|
2021-07-15 18:31:53 -04:00 |
|
Kip Macsai-Goren
|
abd5b1c02d
|
Still broken, midway through fixing understanding of how ptw and datacache interact in time especially wrt adrE, adrM, faults, and tlb interaction.
|
2021-07-15 18:30:29 -04:00 |
|
bbracker
|
3b6291b734
|
stripped down busybox a bit
|
2021-07-15 16:07:56 -04:00 |
|
Kip Macsai-Goren
|
9aedfafb3c
|
modified sv48 test to only read or write from physical addresses located in the dtim range from 0x80000000 to 0x87FFFFFF
|
2021-07-15 14:01:29 -04:00 |
|
Ross Thompson
|
e5d624c1fa
|
Found bug in the PMA such that invalid addresses were sent to the tim. Once addressing this issue the sv48 test fails early with a pma access fault.
|
2021-07-15 11:56:35 -05:00 |
|
Ross Thompson
|
fa26aec588
|
Merge branch 'main' into dcache
|
2021-07-15 11:55:20 -05:00 |
|
Ross Thompson
|
fd1de6b047
|
Updated wave file.
|
2021-07-15 11:04:49 -05:00 |
|
Ross Thompson
|
b9902b0560
|
Fixed how the dcache and page table walker stall cpu so that once a tlb miss occurs the CPU is always stalled until the walk is complete, the tlb updated, and the dcache fetched and hits.
|
2021-07-15 11:00:42 -05:00 |
|
Ross Thompson
|
8610ef204c
|
Renamed DCacheStall to LSUStall in hart and hazard.
Added missing logic in lsu.
|
2021-07-15 10:16:16 -05:00 |
|
Kip Macsai-Goren
|
74e67df080
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2021-07-15 10:52:39 -04:00 |
|