Xavi/cvw
1
0
Fork 0
forked from Github_Repos/cvw
Code Issues Pull Requests Packages Projects Releases Wiki Activity
6,367 Commits 14 Branches 1 Tag 31 MiB
c431278fe6
Commit Graph

6367 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
David Harris
7963bfdbe5
Merge pull request #205 from kbox13/my-single-change 
Increase LSU Coverage
 2023-04-05 13:16:04 -07:00
Kevin Thomas
7345927cb1 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-04-05 15:04:12 -05:00
David Harris
af58afd054
Merge pull request #208 from ross144/main 
Fixes Issue 203
 2023-04-05 13:03:30 -07:00
Ross Thompson
90c2156164
Merge pull request #207 from AlecVercruysse/cachesim 
Cache Simulator
 2023-04-05 14:59:52 -05:00
Ross Thompson
d1ac175e27 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-04-05 14:55:12 -05:00
Limnanthes Serafini
5bae4801bb
*.out removal 2023-04-05 12:50:26 -07:00
Limnanthes Serafini
69eecac989
*.out removal 2023-04-05 12:50:10 -07:00
Limnanthes Serafini
6f53531e26
*.out removal 2023-04-05 12:49:57 -07:00
Alec Vercruysse
61e19c2ddf Make CacheWay flush and dirty logic dependent on !READ_ONLY_CACHE 
To increase coverage. Read-only caches do not have flushes since
they do not have dirty bits.
 2023-04-05 11:48:18 -07:00
Alec Vercruysse
d3a988c96c make Cache Flush Logic dependent on !READ_ONLY_CACHE 
read-only caches do not have flush logic since they do not have to
deal with dirty bits.
 2023-04-05 11:48:18 -07:00
Alec Vercruysse
247af17b6b remove ClearValid from cache 
The cachefsm hardwired ClearValid logic to zero.
This signal might've been added to potentially add extra functionality
later. Unless that functionality is added, however, it negatively
impacts coverage. If the goal is to maximize coverage, this signal
should be removed and only added when it becomes necessary.
 2023-04-05 11:48:18 -07:00
Alec Vercruysse
3867142f10 change i$ cachetagmem from ram1p1rwbe -> ram1p1rwe 
the byte write-enables were always tied high, so we can use
RAM without byte-enable to increase coverage.
 2023-04-05 11:48:18 -07:00
Alec Vercruysse
4993b1b426 turn off ce coverage for ram1p1rwe 
According to the textbook, the cache memory chip enable,
`CacheEn`, is only lowered by the cachefsm with it is in the ready
state and a pipeline stall is asserted.

For read only caches, cache writes only occur in the state_write_line
state. So there is no way that a write would happen while the chip
enable is low.

Removing the chip-enable check from this memory to increase coverage
would be a bad idea since if anyone else uses this ram, the behaviour
would be differently than expected. Instead, I opted to turn off
coverage for this statement. Since this ram, which does not have a
byte enable, is used exclusively by read-only caches right now, this
should not mistakenly exclude coverage for other cases, such as D$.
 2023-04-05 11:48:18 -07:00
Alec Vercruysse
277f507e9a add ram1p1rwe for read-only cache ways (remove byte-enable) 
- increases coverage
 2023-04-05 11:48:18 -07:00
Alec Vercruysse
c0206cfcb3 fix typo in cachway setValid input comment 2023-04-05 11:48:18 -07:00
Alec Vercruysse
270200bc1c put cacheLRU coverage explanation on another line 
the `: explanation` syntax was not working
 2023-04-05 11:48:18 -07:00
Alec Vercruysse
c41f4d2e7b Exclude CacheLRU log2 function from coverage 2023-04-05 11:48:18 -07:00
Ross Thompson
7c2512446c Progress on bug 203. 2023-04-05 13:20:04 -05:00
Kevin Box
c43ee180d3 Add sfence.vma 2023-04-05 10:34:30 -07:00
Kevin Box
490cebe36b Revert "Add sfence.vma and arch64d/f tests to increase coverage in the LSU" 
This reverts commit 90b5d279fd.
 2023-04-05 10:32:25 -07:00
Kevin Box
0517c6b2be remove testing changes 2023-04-05 10:27:34 -07:00
Kevin Box
2c1a0c19dc remove testing change 2023-04-05 10:27:11 -07:00
Kevin Box
90b5d279fd Add sfence.vma and arch64d/f tests to increase coverage in the LSU 2023-04-05 10:18:41 -07:00
Limnanthes Serafini
7de772dcfe Merge remote-tracking branch 'upstream/main' into cachesim 2023-04-05 09:53:05 -07:00
Kevin Thomas
5e5842893b Minor change with the IFU in the decompress module, in the compressed instruction truth table. 
The truth table is already fully covered, removed redundant last case checking
 2023-04-05 10:27:52 -05:00
David Harris
7373cbb3ff
Merge pull request #201 from ross144/main 
Improved d/i cache loggers
 2023-04-05 06:40:14 -07:00
Limnanthes Serafini
98a56dcd66 Further comments and attribution. 2023-04-05 02:46:31 -07:00
Limnanthes Serafini
c42d798ff4 Commenting, attribution for sim, minor log changes 2023-04-05 02:43:02 -07:00
Limnanthes Serafini
47a8cf3993 Outfiles for the failing tests. 2023-04-05 02:42:09 -07:00
Limnanthes Serafini
6abd4ee1b7 Changed logging enables, debug mode in sim. 2023-04-04 23:49:35 -07:00
Limnanthes Serafini
8f3413f0d5 CacheSim edits, tests. I/D$ logging, Lim's version 2023-04-04 21:12:35 -07:00
Noah Limpert
77bd9824c5 Merge branch 'main' of https://github.com/openhwgroup/cvw into main 2023-04-04 20:22:00 -07:00
Limnanthes Serafini
243246e49f
Merge branch 'openhwgroup:main' into cachesim 2023-04-04 13:15:56 -07:00
Ross Thompson
5b188f239b Fixed the d cache logger. 2023-04-04 14:19:19 -05:00
Ross Thompson
b1a805d1f6 Improved d/i cache logger. 2023-04-04 13:38:32 -05:00
Ross Thompson
23ad9f79f0
Merge pull request #199 from davidharrishmc/dev 
Fixed WFI to commit when an interrupt occurs
 2023-04-04 11:34:24 -05:00
David Harris
b7b1f2443f Fixed WFI to commit when an interrupt occurs 2023-04-04 09:32:26 -07:00
David Harris
11230f01ae
Merge pull request #198 from eroom1966/main 
add support for Sstc
 2023-04-04 09:23:38 -07:00
eroom1966
b9ef99530a add support for Sstc 2023-04-04 17:20:00 +01:00
Ross Thompson
c21a5aaaf7
Merge pull request #194 from davidharrishmc/dev 
Bit manipulation support in ImperasDV.  Test improvements.
 2023-04-04 09:13:27 -05:00
David Harris
2466594067
Merge pull request #196 from kipmacsaigoren/zbc_optimize 
bitmanip: simplify zbc input mux
 2023-04-04 06:27:47 -07:00
Kevin Kim
d7deed1690
Merge branch 'openhwgroup:main' into zbc_optimize 2023-04-03 23:45:49 -07:00
Kevin Kim
ce8a401a84 reduced mux3 to mux2 for input signal to clmul 2023-04-03 22:53:46 -07:00
Noah Limpert
f770243689 Test File for Pull Request, Attempt to fill all four ways 2023-04-03 21:54:27 -07:00
David Harris
57ee9f3a5a Merged priv.S edits 2023-04-03 18:07:14 -07:00
David Harris
77f071dc14 Updated imperas.ic to enable B extension 2023-04-03 17:55:30 -07:00
David Harris
23bf8e0375
Merge pull request #190 from SydRiley/main 
expanded ifu coverage including 4 added directed tests and 1 exclusion, expanded fpu coverage including 6 directed tests and 2 multiline exclusions
 2023-04-03 17:48:47 -07:00
David Harris
43a13ff102
Merge pull request #193 from ACWright256/main 
Hardware performance counterer registers test coverage
 2023-04-03 17:47:06 -07:00
Alexa Wright
803fee5903
Merge branch 'openhwgroup:main' into main 2023-04-03 14:30:54 -07:00
Limnanthes Serafini
37f4443012
Merge branch 'openhwgroup:main' into cachesim 2023-04-03 14:10:43 -07:00