Ross Thompson
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1cc258ade1
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Progress towards the test bench flush.
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2021-07-12 14:22:13 -05:00 |
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Ross Thompson
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d65c01bc29
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Write Hits and Write Misses without eviction are working correctly! The next
step is to add eviction of dirty lines.
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2021-07-10 10:56:25 -05:00 |
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Ross Thompson
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4c0cee1c19
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Design loads in modelsim, but trap is an X.
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2021-07-09 15:37:16 -05:00 |
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Ross Thompson
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ec80cc1820
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Lint passes, but I only hope to have loads working. Stores, lr/sc, atomic, are not fully implemented.
Also faults and the dcache ptw interlock are not implemented.
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2021-07-09 15:16:38 -05:00 |
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Ross Thompson
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1fe06bc670
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Partial implementation of the data cache. Missing the fsm.
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2021-07-07 17:52:16 -05:00 |
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