7 Commits

Author	SHA1	Message	Date
David Harris	a86a9f5c2a	simpleram simplification	2022-01-25 18:26:31 +00:00
David Harris	e3136c9a1e	simpleram address simplification	2022-01-25 18:17:33 +00:00
David Harris	7ad2eb009a	simpleram address simplification	2022-01-25 18:00:50 +00:00
David Harris	6a555032eb	simpleram clk and reset simplification	2022-01-25 17:34:15 +00:00
Ross Thompson	9982549057	Changed the IROM and DTIM memories to behave like edge-triggered srams.	2022-01-21 15:42:54 -06:00
David Harris	07425369fc	Renamed wallypipelinedhart to wallypipelinedcore	2022-01-20 16:02:08 +00:00
Ross Thompson	a973681a90	Added support for logic memory in the IFU and LSU. This disables the bus interface. Peripherals do not work. Also requires using testbench-harvard.sv. I hope to merge this testbench with the main testbench.sv soon.	2022-01-13 22:21:43 -06:00