Ross Thompson
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44196af61a
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Have program which checks for sdc init and issues read, but read done is
not correctly being read back by the software. The error is in how the
sdc indicates busy.
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2021-09-24 15:53:38 -05:00 |
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David Harris
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118cb7fb87
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Added testbench-arch for riscv-arch-test suite
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2021-09-08 15:59:40 -04:00 |
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Ross Thompson
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6e803b724e
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Merge branch 'tests' into icache-almost-working
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2021-04-25 21:25:36 -05:00 |
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Ross Thompson
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4322694f7a
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Switch to use RV64IC for the benchmarks.
Still not working correctly with the icache.
instr
addr correct got
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2021-04-07 19:12:43 -05:00 |
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Ross Thompson
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c91436d3b7
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Merge branch 'icache_bp_bug' into tests
Not sure this merge is right.
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2021-04-06 21:46:40 -05:00 |
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Ross Thompson
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bff2d61a1f
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Steps to getting branch predictor benchmarks running.
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2021-04-06 21:20:51 -05:00 |
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Ross Thompson
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a64a37d702
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Merge of main with the new icache and the branch predictor. I believe there is a bug in the icache with unaligned memory access. The second part of the access is incorrectly relying on the PCF being the address of the next two bytes of the instruction. However this is not always the case as the branch predictor can get the wrong target address. The icache needs to generate the +2 address internally.
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2021-03-30 23:18:20 -05:00 |
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Ross Thompson
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5edc90b1c2
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added a whole bunch of interseting test code for branches which does not work.
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2021-03-23 13:54:59 -05:00 |
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Ross Thompson
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2b0f7cdd42
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Temporary exe2memfile0.pl script to support starting addresses of 0.
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2021-03-23 13:54:59 -05:00 |
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