26 Commits

Author	SHA1	Message	Date
David Harris	739c2c8322	Changed MIT license to Solderpad License	2023-01-10 11:35:20 -08:00
Ross Thompson	01d4e942d0	Added more missing files.	2023-01-06 00:12:08 -06:00
Ross Thompson	872ff619e3	Fixed problems with changes to ram2p.	2022-12-29 17:13:48 -06:00
Ross Thompson	a129e27502	signal name changes in ram2p.	2022-12-27 15:07:01 -06:00
David Harris	f0ef5caf32	Memory cleanup	2022-12-20 11:22:26 -08:00
David Harris	e74d47bcb4	Renamed renamed sram to ram	2022-12-20 08:36:45 -08:00
David Harris	16f3c25cb7	sram1p1rw cleanup	2022-12-20 02:57:51 -08:00
David Harris	08234cb1c7	Remoed unused bram modules	2022-12-20 02:40:45 -08:00
David Harris	2c46f22be5	Renamed SRAM2P1R1W to lower case	2022-12-20 02:09:55 -08:00
David Harris	54e856c4f5	Renamed SRAM2P1R1W to lower case	2022-12-20 02:09:36 -08:00
Ross Thompson	8692ccbafb	Intermediate commit. Replaced flip flop dirty bit array with sram.	2022-11-30 00:08:31 -06:00
Ross Thompson	1a00e7bbee	Changed names of cache signals.	2022-11-13 21:36:12 -06:00
David Harris	b5d2bbe7ca	changed always_ff to always in sram1p1rw to fix testbench complaint	2022-09-25 19:56:40 -07:00
Ross Thompson	6a6686a34b	Removed the write first sram model.	2022-09-22 16:12:08 -05:00
Ross Thompson	29087812e1	Solved the sram write first / read first issue. Works correctly with read first now.	2022-09-22 14:16:26 -05:00
Ross Thompson	cdc80c1f28	Moved other SRAMs to generic/mem.	2022-09-21 12:36:03 -05:00
Ross Thompson	427db1f55f	Renamed brom1p1r to rom1p1r. ... removed used file bram2p1r1w.sv.	2022-09-21 12:31:20 -05:00
Ross Thompson	91fcca9d17	Merged together bram1p1rw with sram1p1rw as sram1p1rw. ... Fixed a major issue with the real SRAM implemenation.	2022-09-21 12:20:00 -05:00
Ross Thompson	b2f4d4aaa7	Added chip enables to sram.	2022-09-20 10:49:14 -05:00
Ross Thompson	2aa5886769	Fixed brom1p1r.sv to have fpga preload.	2022-09-02 15:49:50 -05:00
Ross Thompson	559e093ab5	Fixed up FPGA constraints. ... Added back in the fpga boot rom preload.	2022-09-02 13:54:35 -05:00
David Harris	24ce72f0a2	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-08-25 09:52:49 -07:00
Ross Thompson	72b886ec8f	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-08-25 09:03:34 -05:00
David Harris	b9dc8d9e33	Cleanup typos	2022-08-25 04:32:19 -07:00
David Harris	fe3147806d	removed simpleram and modified dtim to use bram1p1rw	2022-08-25 03:39:57 -07:00
David Harris	e6077f1f16	Added ROM module and moved memories into generic/mem	2022-08-24 17:03:22 -07:00