15 Commits

Author	SHA1	Message	Date
eroom1966	319a1b9161	fix break to simulation testbench	2023-04-06 14:45:41 +01:00
eroom1966	b9ef99530a	add support for Sstc	2023-04-04 17:20:00 +01:00
Ross Thompson	78ab9f59af	Updated GPIO signal names to reflect book.	2023-03-24 18:55:43 -05:00
eroom1966	0d260accb4	Fix MISA RO and UART addresses ... It appears on inspection that the MISA register is read only in Wally In which case this has now also been set in the ImperasDV representation Also the Addresss for the UART R/W privileges are corrected	2023-03-13 11:07:19 +00:00
eroom1966	8e657c335e	Enhancements to support the PMA ranges	2023-03-10 14:09:22 +00:00
eroom1966	68f3e31547	Add support for setting PMP registers ... Add support for async DV	2023-03-08 12:44:53 +00:00
eroom1966	1169567219	fix the memory map privileges in the REF model view	2023-03-02 15:25:27 +00:00
eroom1966	72b92e8c0d	update testbench for memory privileges ... also update configuration to define value of mimpid	2023-03-01 15:37:11 +00:00
eroom1966	baf93a1f0e	add support for idv package	2023-02-22 13:27:01 +00:00
David Harris	0da32a41f6	moved riscvassertons to its own file, added proper license headers to testbench support files	2023-02-16 19:40:27 -08:00
eroom1966	0ac99d2233	add files to support coverage	2023-02-15 11:13:50 +00:00
eroom1966	3910e90b54	remove dead code for ignoring fflags/fcsr	2023-02-06 15:53:29 +00:00
eroom1966	02b4f9c304	remerge changes	2023-02-06 13:43:12 +00:00
David Harris	8e9183962d	Fixed license on testbench files	2023-02-04 08:19:20 -08:00
David Harris	99d179dd3e	Removed pipelined level of hierarchy	2023-02-02 14:14:11 -08:00