64 Commits

Author	SHA1	Message	Date
David Harris	6febce0001	Moved Dcache into bus block	2022-01-15 00:39:07 +00:00
David Harris	fd13272d4c	Renamed LSUStall to LSUStallM	2022-01-15 00:24:16 +00:00
Ross Thompson	11f1613d59	Added additional fsm to ILA.	2022-01-12 14:17:16 -06:00
Ross Thompson	d8173745bb	Possible fix for the TrapM DTLBMiss suppression.	2022-01-12 14:17:16 -06:00
Ross Thompson	d14dffd010	Updated debug constraints again to match changes in verilog.	2022-01-08 13:28:51 -06:00
Ross Thompson	6bd447d570	Patched the ILA's debug2.xdc constraint file to work with the wally memory design.	2022-01-06 15:18:18 -06:00
Ross Thompson	42623141cd	Updated fpga ILA constraints to match the new changes to the rtl.	2022-01-06 11:56:09 -06:00
Ross Thompson	5a2ae561a7	Updates to support fpga.	2022-01-05 18:07:23 -06:00
Ross Thompson	beb1988539	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2021-12-20 10:03:19 -06:00
Ross Thompson	225cd5a114	Renamed MemAdrM to IEUAdrM. This will free the name MemAdrm for use in the DCache.	2021-12-19 14:00:30 -06:00
Ross Thompson	a11597b6bd	Added more debugging code for FPGA.	2021-12-17 14:40:25 -06:00
Ross Thompson	21b13fc237	Reverted 23Mhz to 10Mhz. The flash card can't work at that speed. ... added icache debugging signals.	2021-12-15 10:24:29 -06:00
Ross Thompson	68745d40f2	Modified FPGA to add additional signals to ILA. Created advanced trigger for ILA using vivado's tsm language.	2021-12-12 17:21:44 -06:00
Ross Thompson	f2628494e3	Missed constraints file for xilinx ILA.	2021-12-12 15:06:29 -06:00