Commit Graph

18 Commits

Author SHA1 Message Date
Ross Thompson
4dbd5d45ee Added information on how to copy the linux image to flash card. 2021-12-07 13:16:38 -06:00
Ross Thompson
22721dd923 Added generate around the dtim preload.
Added readme to explain FPGA.
2021-12-07 13:12:47 -06:00
Ross Thompson
29743c5e9e Fixed two issues.
First the xci files already include the xdc constraints for each IP block. There is no need to include the xdc files explicitly.
Second the bidir buffer for the sd card was connected backwards.
2021-12-07 12:15:50 -06:00
Ross Thompson
c3c9c327b7 Fixed more constraint issues in fpga.
Added back in the ILA.
Design does not work yet.  Stil having issues with order of automatic
clock and I/O constraint ordering.
Added back in the preload for the boottim.
2021-12-05 15:14:18 -06:00
Ross Thompson
955ddcfbe1 Fixed bug in the top level of fpga verilog. 2021-12-03 17:55:36 -06:00
Ross Thompson
5b4ff4526e Fixed a bunch of fpga issues. 2021-12-03 17:47:54 -06:00
Ross Thompson
cbb5e4440f Improved FPGA makefile and fixed timing constraints in clock converter. 2021-12-03 10:05:13 -06:00
Ross Thompson
96fb3acefd Constraints for fpga are still wrong. 2021-12-02 14:23:21 -06:00
Ross Thompson
303324d370 Added tcl commands to build the implementation. 2021-12-02 10:17:30 -06:00
Ross Thompson
0d47749cb5 Separated timing constraints from ILA. 2021-12-01 18:15:04 -06:00
Ross Thompson
e94fb2aaec Got fpga synthesis running from scripts. 2021-12-01 16:59:04 -06:00
Ross Thompson
5ea9ec0ae6 Created top level FPGA module which replicates the schematic of the initial fpga design. 2021-11-30 17:18:28 -06:00
Ross Thompson
d5f445e0fd Added make clean to fpga IP generator. 2021-11-29 18:42:28 -06:00
Ross Thompson
a528a86607 Created Makefile to manage IP generation. 2021-11-29 18:33:58 -06:00
Ross Thompson
51807379a8 Added final IP generator script (proc_sys_reset). 2021-11-29 17:43:47 -06:00
Ross Thompson
8aa87958a9 Added ddr4 generator script. 2021-11-29 15:56:57 -06:00
Ross Thompson
da4ed957aa Created tcl scripts to build 2 of the 4 xilinx IP. 2021-11-29 11:26:08 -06:00
Ross Thompson
9150133c7d Fpga simualtion files. 2021-10-11 10:24:40 -05:00