bbracker
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742e8d98cd
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fix up PLIC and UART checkpointing
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2022-03-07 23:48:47 -08:00 |
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bbracker
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bfaf496473
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change UART state saving to temporarily modify LCR so that DLAB=0 when reading addresses 0 and 1 so that we get RBR and IER instead of divisor latch registers
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2022-03-07 22:12:08 -08:00 |
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bbracker
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92e1583db5
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change testbench-linux.sv to use new shared location of disassembly files
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2022-03-07 20:04:08 -08:00 |
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bbracker
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097301635a
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change checkpoint generation to integrate GDB scripting more cleanly and save UART and PLIC state
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2022-03-07 17:59:49 -08:00 |
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bbracker
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409dd48706
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modify debug.sh to not rely on external GDB script
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2022-03-07 11:56:04 -08:00 |
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bbracker
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4bf95714eb
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add debug.sh
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2022-03-07 19:52:19 +00:00 |
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Shreya Sanghai
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c15517d334
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removed reminant changes
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2022-03-07 17:36:05 +00:00 |
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Shreya Sanghai
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a218a3d9fa
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undid changes to synth script
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2022-03-07 17:32:08 +00:00 |
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Shreya Sanghai
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94a57fb6eb
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modified synth script to take config from outputdir
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2022-03-07 17:12:43 +00:00 |
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Shreya Sanghai
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bc049e8042
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updated makefile to speed up synth
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2022-03-07 00:09:18 +00:00 |
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Shreya Sanghai
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a68c1c8cb1
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modified makefile
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2022-03-07 00:09:18 +00:00 |
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bbracker
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483aad2a05
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update checkpointSweep in accordance to having removed trace parsing feature
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2022-03-06 14:55:51 -08:00 |
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bbracker
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bea2faeda6
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remove vestigial silencePipe mechanism
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2022-03-06 14:54:35 -08:00 |
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bbracker
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11e9bbf3e4
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needed to initialize checkpoint directory
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2022-03-06 14:51:25 -08:00 |
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bbracker
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d007208aa9
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no longer use cythonization on python parser scripts because its a little complicated and has marginal benefit
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2022-03-06 14:40:26 -08:00 |
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bbracker
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f64b7776ed
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give genCheckpoint the same de-sudo'ing treatement
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2022-03-06 14:37:12 -08:00 |
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bbracker
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7182ec228f
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better to use $tvDir variable rather than abs path
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2022-03-06 14:33:53 -08:00 |
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bbracker
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8f2e67984f
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replace sudo's with suggestions in genRecording.sh
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2022-03-06 14:31:55 -08:00 |
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bbracker
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e57b5208dc
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replace sudo's in genTrace.sh with suggested commands
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2022-03-06 14:24:50 -08:00 |
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bbracker
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91f327e109
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small bugfix to suggested sudo commands for linux testvectors
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2022-03-06 14:16:23 -08:00 |
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bbracker
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742b9d884d
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remove checkpoint trace generation since that requires qemu hacking and because we are able to generate the whole trace on VLSI
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2022-03-06 14:04:30 -08:00 |
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bbracker
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bb90644fb2
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add path to Modelsim on vlsi
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2022-03-06 13:55:19 -08:00 |
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bbracker
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e3f735cc1a
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recommend sudo commands without automatically executing them in genInitMem.sh
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2022-03-06 13:30:19 -08:00 |
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bbracker
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efee8d3a22
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change from clang to gcc when compiling testvector-generation executables
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2022-03-06 13:18:53 -08:00 |
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bbracker
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b1120069a0
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generate $WALLY in a way that works for bash and zsh
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2022-03-06 13:12:20 -08:00 |
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bbracker
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70ddc98d19
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Revert "fix "dirname: missing operand" bug from setup.sh"
This reverts commit 60cbd1c9c1.
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2022-03-06 12:48:53 -08:00 |
|
David Harris
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db3b253ac1
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Fixed merge of fpcalc
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2022-03-06 13:32:13 +00:00 |
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David Harris
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7391c6d338
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Checked in fma16_template.v
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2022-03-06 13:29:35 +00:00 |
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bbracker
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1fc7856c36
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add extractFunctionRadix step to buildroot Makefile
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2022-03-05 19:02:07 -08:00 |
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bbracker
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4eb46785fc
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change genInitMem.sh to check for sufficient directory privileges rather than invoke sudo
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2022-03-05 18:04:00 -08:00 |
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bbracker
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891ec82d81
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remove linux-testgen dir because it is now completely obsolete
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2022-03-05 17:26:30 -08:00 |
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bbracker
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60cbd1c9c1
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fix "dirname: missing operand" bug from setup.sh
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2022-03-05 17:21:34 -08:00 |
|
David Harris
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e6133f3d83
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-03-04 07:21:22 -08:00 |
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David Harris
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bffd417567
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Cleaned up printing and warnings in fpcalc.c
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2022-03-04 07:21:18 -08:00 |
|
David Harris
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cba6f10c19
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Prettied up softfloat_demo
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2022-03-04 05:16:20 +00:00 |
|
David Harris
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99a0e2d73d
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Adjusted scripts to use
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2022-03-04 05:09:02 +00:00 |
|
David Harris
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c13517f0ce
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Defined WALLY in setup as pointer to repository
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2022-03-03 21:00:07 -08:00 |
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David Harris
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e4d18f1808
|
removed more old 64priv tests
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2022-03-04 03:57:19 +00:00 |
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bbracker
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41c75dc89d
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-03-04 00:12:00 +00:00 |
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bbracker
|
c3e59ae2df
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comment out nonfunctioning CSR-PERMISSIONS-M test
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2022-03-04 00:11:55 +00:00 |
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David Harris
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a50f1a4424
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2022-03-04 00:07:34 +00:00 |
|
David Harris
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2cea3349ad
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LSU/Cache code review notes
|
2022-03-04 00:07:31 +00:00 |
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bbracker
|
d645666fe7
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-03-04 00:06:27 +00:00 |
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bbracker
|
79ff8d3c80
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remove imperas32p tests
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2022-03-04 00:06:18 +00:00 |
|
David Harris
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db7d3cfc0e
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Updated Makefile to reflect new Linux and Imperas situation. Updated setup to include Synopsys license file.
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2022-03-03 11:28:22 -08:00 |
|
David Harris
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6431ad4a8b
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Fixed fma files to stop breaking synthesis. Changed Makefiles to skip Imperas
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2022-03-03 15:38:08 +00:00 |
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David Harris
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f76e396255
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erge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-03-02 23:47:16 +00:00 |
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David Harris
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8e83aaeced
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fma file fixes
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2022-03-02 23:47:01 +00:00 |
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bbracker
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87aad1d953
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fix peripheral test and add it to regression
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2022-03-02 23:44:39 +00:00 |
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bbracker
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11423d1d17
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but apparently QEMU doesn't show UXL in SSTATUS
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2022-03-02 22:44:19 +00:00 |
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