8 Commits

Author	SHA1	Message	Date
Ross Thompson	6f53f7943f	More spillsupport more structual.	2022-02-23 10:27:14 -06:00
Ross Thompson	19ec874641	Fixed bug with spill support and Instruction DA Page Faults.	2022-02-23 10:16:12 -06:00
Ross Thompson	febd019854	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-02-11 10:47:21 -06:00
Ross Thompson	6d12010d02	Fixed subtle and infrequenct bug. ... Loading buildroot at 483M instructions started with a spill + ITLBMiss. The spillsupport logic allowed transition to the second access only after the bus/cache completed the first operation. However the BusStall was suppressed if ITLBMissF occurs resulting in the spillfsm advancing to the second operation. Now the spill logic also takes in ITLBMissF and prevents the early transition to the second access.	2022-02-11 10:46:06 -06:00
David Harris	de5e80696d	Cleaned up synthesis warnings	2022-02-11 01:15:16 +00:00
Ross Thompson	689c32215f	Fixed bugs in ifu spills and missing reset on bus data register.	2022-02-10 18:11:57 -06:00
David Harris	da8819d64b	changed DMEM and IMEM configurations to support BUS/TIM/CACHE	2022-02-03 00:41:09 +00:00
Ross Thompson	a4f6653cd8	Encapsulated the bus data path into a separate module.	2022-01-31 10:15:48 -06:00