5 Commits

Author	SHA1	Message	Date
Ross Thompson	9dce2a0679	Towards allowing dtim + bus.	2022-03-11 14:58:21 -06:00
Ross Thompson	b7a680ec2a	Moved subcachelineread inside the cache. There is some ugliness to still resolve.	2022-03-11 12:44:04 -06:00
David Harris	2cea3349ad	LSU/Cache code review notes	2022-03-04 00:07:31 +00:00
Ross Thompson	d21be9d998	Added config to allow using the save/restore or replay implementation to handle sram clocked read delay.	2022-02-04 23:49:07 -06:00
Ross Thompson	725852362e	Got separate module for the sub cache line read.	2022-02-04 20:23:09 -06:00