Ross Thompson
6668956351
More cachefsm cleanup.
2022-02-07 11:12:28 -06:00
Ross Thompson
5536e3ca90
More cachefsm cleanup.
2022-02-07 10:54:22 -06:00
Ross Thompson
529d8b629a
Cache cleanup.
2022-02-07 10:43:58 -06:00
Ross Thompson
41a79556e0
More cachfsm cleanup.
2022-02-07 10:33:50 -06:00
Ross Thompson
0b66106925
More cachefsm cleanup.
2022-02-06 21:50:44 -06:00
Ross Thompson
dd6baa9ed4
started cachefsm cleanup.
2022-02-06 21:39:38 -06:00
Ross Thompson
d21be9d998
Added config to allow using the save/restore or replay implementation to handle sram clocked read delay.
2022-02-04 23:49:07 -06:00
Ross Thompson
725852362e
Got separate module for the sub cache line read.
2022-02-04 20:23:09 -06:00
Ross Thompson
7c1f7e335c
Working first cut of the cache changes moving the replay to a save/restore.
...
The current implementation is too expensive costing (tag+linelen)*numway flip flops and muxes.
2022-02-04 13:31:32 -06:00
David Harris
ee3300bcd2
sram1rw cleanup
2022-02-03 18:03:22 +00:00
Ross Thompson
42ef1e22e5
1. Modified the cache so it can handle the reset delay internally. This removes the mux from the IFU.
...
2. Removed the write address delay from simpleram.sv
3. Fixed rv32tim and rv32ic mode to handle missalignment correctly.
4. Added imperas32i and imperas32c to rv32tim mode.
2022-01-26 18:23:39 -06:00
David Harris
120fb7863f
Reformatted MIT license to 95 characters
2022-01-07 12:58:40 +00:00
Ross Thompson
e1db967417
Clean up of cachefsm.
2022-01-06 16:32:49 -06:00
Ross Thompson
365b2715ed
More name cleanup in cache.
2022-01-05 22:37:53 -06:00
Ross Thompson
8d33bf0b4a
Slower but correct implementation of flush.
2022-01-05 16:57:22 -06:00
Ross Thompson
49eea2add5
Fixed bug with flush dirty not cleared in the correct cache line.
2022-01-05 14:14:01 -06:00
Ross Thompson
f89c1d91dc
Renamed most signals inside cache.sv so they are agnostic to i or d.
2022-01-04 23:52:42 -06:00
