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Author SHA1 Message Date
Ross Thompson
67ff8f27f4 Can now support the following memory and bus configurations. 
1. dtim/irom only
2. bus only
3. dtim/irom + bus
4. caches + bus
 2022-03-11 15:18:56 -06:00
Ross Thompson
9dce2a0679 Towards allowing dtim + bus. 2022-03-11 14:58:21 -06:00
Kip Macsai-Goren
9d0a9f0747 added preliminary files for trap/priv tests. These DO NOT pass make yet because if interrrupt handling problems 2022-03-11 20:00:54 +00:00
Kip Macsai-Goren
026354f09f removed compressed instructions from gcc make for privilege tests 2022-03-11 19:09:40 +00:00
Kip Macsai-Goren
88897da30b Added interrupt support (not exiting correctly yet), macros for causing traps. 2022-03-11 19:09:16 +00:00
Ross Thompson
6e24a807f6 mild cleanup. 2022-03-11 13:05:47 -06:00
Ross Thompson
b7a680ec2a Moved subcachelineread inside the cache. There is some ugliness to still resolve. 2022-03-11 12:44:04 -06:00
Ross Thompson
a18f06c20b Moved subcacheline read inside the cache. 2022-03-11 11:03:36 -06:00
Ross Thompson
52cc852600 removed unused parameter. 2022-03-11 10:43:54 -06:00
Ross Thompson
7f0c5cc847 atomic cleanup. 2022-03-10 18:56:37 -06:00
Ross Thompson
257015a2df Name changes. 2022-03-10 18:50:03 -06:00
Ross Thompson
6d914def08 Name cleanup. 2022-03-10 18:44:50 -06:00
Ross Thompson
63b1ea88c9 Signal name cleanup. 2022-03-10 18:26:58 -06:00
Ross Thompson
654c4d1148 simplified uncore's name for HWDATA. 2022-03-10 18:17:44 -06:00
Ross Thompson
1aa87c9f3a Moved subwordwrite to lsu directory. 2022-03-10 18:15:25 -06:00
Ross Thompson
d0cf41dbe4 Simplified byte write enable logic. 2022-03-10 18:13:35 -06:00
Ross Thompson
396c97fc36 Byte write enables are passing all configs now. 2022-03-10 17:26:32 -06:00
Ross Thompson
d8e71e8e35 Progress on the path to getting all configs working with byte write enables. 2022-03-10 17:02:52 -06:00
Ross Thompson
67ef46ea92 Partially working byte write enables. Works for cache, but not dtim or bus only. 2022-03-10 16:11:39 -06:00
Ross Thompson
7a129c75cd Added byte write enables to cache SRAMs. 2022-03-10 15:48:31 -06:00
David Harris
bc2b757952 bit write update 2022-03-09 19:09:20 +00:00
David Harris
27f09ffb33 Refactored SRAM bit write enable 2022-03-09 17:49:28 +00:00
David Harris
89e0830883 Updated testbench to read expected flags 2022-03-09 13:58:17 +00:00
Ross Thompson
95bb4cc8a8 Minor cleanup to interlockfsm. 2022-03-08 23:38:58 -06:00
Ross Thompson
9b113149b6 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-03-08 18:05:35 -06:00
Ross Thompson
0310fe858f Comments. 2022-03-08 18:05:25 -06:00
Ross Thompson
75e93baaee Marked signals for name changes. 2022-03-08 17:41:02 -06:00
David Harris
00908132e6 Added more test cases and rounding modes to fma test generator 2022-03-08 23:29:29 +00:00
David Harris
8fa6a85af2 fixed setup.sh merge conflict 2022-03-08 23:21:06 +00:00
David Harris
c8f2dce026 fma16_testgen.c test cases 2022-03-08 23:18:18 +00:00
Ross Thompson
3ec32d7ce8 Removed unused signal. 2022-03-08 16:58:26 -06:00
Ross Thompson
d78ba777a4 Added parameter to spillsupport. 2022-03-08 16:38:48 -06:00
Ross Thompson
7b96b3f73c Moved cacheable signal into cache. 2022-03-08 16:34:02 -06:00
bbracker
099fc34c10 change genTrace to dump UART output to file so we can see how far parsing got 2022-03-08 09:52:17 -08:00
bbracker
742e8d98cd fix up PLIC and UART checkpointing 2022-03-07 23:48:47 -08:00
bbracker
bfaf496473 change UART state saving to temporarily modify LCR so that DLAB=0 when reading addresses 0 and 1 so that we get RBR and IER instead of divisor latch registers 2022-03-07 22:12:08 -08:00
bbracker
92e1583db5 change testbench-linux.sv to use new shared location of disassembly files 2022-03-07 20:04:08 -08:00
bbracker
097301635a change checkpoint generation to integrate GDB scripting more cleanly and save UART and PLIC state 2022-03-07 17:59:49 -08:00
bbracker
409dd48706 modify debug.sh to not rely on external GDB script 2022-03-07 11:56:04 -08:00
bbracker
4bf95714eb add debug.sh 2022-03-07 19:52:19 +00:00
Shreya Sanghai
c15517d334 removed reminant changes 2022-03-07 17:36:05 +00:00
Shreya Sanghai
a218a3d9fa undid changes to synth script 2022-03-07 17:32:08 +00:00
Shreya Sanghai
94a57fb6eb modified synth script to take config from outputdir 2022-03-07 17:12:43 +00:00
Shreya Sanghai
bc049e8042 updated makefile to speed up synth 2022-03-07 00:09:18 +00:00
Shreya Sanghai
a68c1c8cb1 modified makefile 2022-03-07 00:09:18 +00:00
bbracker
483aad2a05 update checkpointSweep in accordance to having removed trace parsing feature 2022-03-06 14:55:51 -08:00
bbracker
bea2faeda6 remove vestigial silencePipe mechanism 2022-03-06 14:54:35 -08:00
bbracker
11e9bbf3e4 needed to initialize checkpoint directory 2022-03-06 14:51:25 -08:00
bbracker
d007208aa9 no longer use cythonization on python parser scripts because its a little complicated and has marginal benefit 2022-03-06 14:40:26 -08:00
bbracker
f64b7776ed give genCheckpoint the same de-sudo'ing treatement 2022-03-06 14:37:12 -08:00