Domenico Ottolia
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5ab86a690b
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Fix bug that caused stvec to get the wrong value
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2021-05-03 17:54:57 -04:00 |
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Ross Thompson
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6e803b724e
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Merge branch 'tests' into icache-almost-working
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2021-04-25 21:25:36 -05:00 |
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Domenico Ottolia
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0c307d2db1
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Fix synthesis warnings for privileged unit (replace 'initial' settings)
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2021-04-20 17:57:56 -04:00 |
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Thomas Fleming
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fdb20ee1cf
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Implement sfence.vma and fix tlb writing
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2021-04-01 15:55:05 -04:00 |
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Ross Thompson
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a99c0502e5
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Fixed bugs with the csr interacting with StallW. StallW is required to pervent updating a csr. Now have a working branch predictor and performance counters to track the number of commited branches and mispredictions.
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2021-03-24 15:56:55 -05:00 |
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Noah Boorstin
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bc1a0c6ee7
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change ifndef to generate/if
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2021-03-18 12:50:19 -04:00 |
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Thomas Fleming
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be6ee84d87
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2021-03-05 15:46:51 -05:00 |
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Thomas Fleming
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7e11317a2d
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Export SATP_REGW from csrs to MMU modules
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2021-03-05 01:22:53 -05:00 |
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Noah Boorstin
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f48af209c4
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busybear: make CSRs only weird for us
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2021-03-05 00:46:32 +00:00 |
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David Harris
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015b632eb1
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Cleaned out unused signals
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2021-02-26 09:17:36 -05:00 |
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kaveh pezeshki
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c7863d58cd
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merged with main to integrate with AHB
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2021-02-26 05:37:10 -08:00 |
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Noah Boorstin
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5835641c6c
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busybear testbench: check (almost) all the CSRs
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2021-02-16 20:03:24 -05:00 |
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Noah Boorstin
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14cde0d59c
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Change CSR reset and available bits to conform to OVPsim
Now actually keeping perfectly in line with OVP for the first 100k instrs. Yay.
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2021-02-04 22:03:45 +00:00 |
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David Harris
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9d7e242596
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Moved fpu to temporary location to fix compile and cleaned up interface formatting
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2021-02-01 23:44:41 -05:00 |
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David Harris
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396cea1ea7
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Reorganized src hierarchically
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2021-01-30 11:50:37 -05:00 |
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