15 Commits

Author	SHA1	Message	Date
cturek	333da5c945	Added n, p, and m signals between fdivsqrt submodules. Added w64 and mdue to divsqrt testbench.	2022-11-06 22:08:18 +00:00
cturek	b893d9249d	Added new macros for int div preprocessing, added p, n, and rightshiftx logic	2022-11-06 21:53:48 +00:00
cturek	39bf6a456e	renamed remOp to RemOp	2022-11-03 22:37:25 +00:00
cturek	890b26466f	Added rem/div operation to postprocessor	2022-11-02 17:49:40 +00:00
cturek	51fc4de0e1	small signal cleanup	2022-10-26 18:42:49 +00:00
cturek	94daa961b3	Started Integer Preprocessing	2022-10-25 17:48:43 +00:00
amaiuolo	a0712d1456	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally	2022-10-13 22:36:57 +00:00
amaiuolo	000117fcd4	added amaiuolo@hmc.edu	2022-10-13 22:36:52 +00:00
David Harris	55e4911cf0	fdivsqrt code cleanup	2022-10-09 03:37:27 -07:00
David Harris	fc4146f409	Adding start signals for integer divider to fdivsqrt	2022-09-29 16:30:25 -07:00
cturek	c72e2e5d49	Added integer inputs and flags to divsqrt	2022-09-29 23:08:27 +00:00
David Harris	b21e36a788	Added SpecialCaseReg to hold SpecialCase for fdivsqrtpostproc	2022-09-21 04:55:43 -07:00
David Harris	437fd52bf6	Gated sticky bit in fdiv with SpecialCase	2022-09-20 20:05:00 -07:00
David Harris	811f498f63	renamed q to u for unified digit selection	2022-09-20 04:35:14 -07:00
David Harris	8d1408a9d6	Moved fpu modules into subdirectories	2022-09-20 04:12:05 -07:00