17 Commits

Author	SHA1	Message	Date
Ross Thompson	fe896bff8e	Found a way to remove a bus input into MMU. PAdr can be made into VAdr by selecting the faulting virtual address when writing the DTLB.	2022-03-24 23:47:28 -05:00
Ross Thompson	95bb4cc8a8	Minor cleanup to interlockfsm.	2022-03-08 23:38:58 -06:00
David Harris	2cea3349ad	LSU/Cache code review notes	2022-03-04 00:07:31 +00:00
Ross Thompson	971dd494f6	Clarified interlockfsm.	2022-02-22 11:31:28 -06:00
Ross Thompson	1ab2e7590b	Added some clearity to lsuvirtmem.sv.	2022-02-21 17:20:58 -06:00
Ross Thompson	ace743ae91	Changed HPTWRead/HPTWWrite to be HPTWRW to be similar to MemRW.	2022-02-21 16:54:38 -06:00
Ross Thompson	414e73edd9	Cleaned up names in lsuvirtmem.	2022-02-21 16:44:30 -06:00
Ross Thompson	456a54166a	Minor cleanup of lsu.	2022-02-21 12:46:06 -06:00
Ross Thompson	5d9ad011d2	Moved mux into lsuvirtmem.	2022-02-21 09:31:29 -06:00
Ross Thompson	a60332b455	Minor changes to LSU.	2022-02-19 14:38:17 -06:00
Ross Thompson	0bd533473c	New config option to enable hptw writes to PTE in memory to update Access and Dirty bits.	2022-02-17 17:19:41 -06:00
Ross Thompson	d152733a17	Rough implementation passing regression test with hptw atomic writes to memory.	2022-02-17 14:46:11 -06:00
Ross Thompson	4cfb601dc8	Fixed a bunch of the virtual memory changes. Now supports atomic update of PTE in memory concurrent with TLB.	2022-02-17 10:04:18 -06:00
Ross Thompson	565ca4e4a3	Broken state. address translation not working after changes to hptw to support atomic updates to PT.	2022-02-16 23:37:36 -06:00
Ross Thompson	36ab78ef3b	Removed all possilbe paths to PreSelAdr from TrapM.	2022-02-09 19:20:10 -06:00
David Harris	02071700d6	Removed Busybear dependencies	2022-02-02 20:28:21 +00:00
Ross Thompson	31da37dd0f	Moved lsu virtual memory logic into separate module.	2022-01-31 11:56:03 -06:00