2 Commits

Author	SHA1	Message	Date
bbracker	67eb1f5c6b	change sram1rw to have a small delay so that we don't have signals changing on clock edges	2021-07-19 11:30:07 -04:00
Ross Thompson	19a93345b5	Reduced icache to 1 port memory.	2021-05-03 14:47:49 -05:00