David Harris
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fb95767da0
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Fixed bug with CSRRS/CSRRC for MIP/SIP
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2022-04-03 20:18:25 +00:00 |
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Ross Thompson
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19a8df9739
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Added wave config
added new signals to ILA.
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2022-04-01 12:44:14 -05:00 |
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bbracker
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69a0f6e00b
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big interrupts refactor
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2022-03-30 13:22:41 -07:00 |
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Kip Macsai-Goren
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56a0542405
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made machine timer bit of IP registers unwriteable so it can only change when the interrupt actually changes
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2022-03-29 02:26:42 +00:00 |
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Ross Thompson
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61c714ebe6
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I think this version of csri matches what is required in the spec. ExtIntS should not be written into the SEIP register bit.
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2022-03-25 13:10:31 -05:00 |
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bbracker
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4b376e2834
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1st attempt at multiple channel PLIC
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2022-03-24 17:08:10 -07:00 |
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Ross Thompson
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849707f161
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Switched csri IP_REGW to use assignements rather than always_comb as this is incompatible with forcing.
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2022-03-22 22:04:06 -05:00 |
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David Harris
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d3034c4f01
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Mostly removed N_SUPPORTED
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2022-02-15 19:50:44 +00:00 |
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Ross Thompson
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e2343699d1
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Factored out InstrValidNotFlushedM from each csr*.sv to csr.sv
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2022-01-20 16:39:54 -06:00 |
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Ross Thompson
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a5f773220e
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Updated CSR modules to prevent writting the registers when flushing. This only effects architecture writes not side effect writes.
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2022-01-18 17:19:33 -06:00 |
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David Harris
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120fb7863f
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Reformatted MIT license to 95 characters
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2022-01-07 12:58:40 +00:00 |
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David Harris
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c1d6550ccb
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Removed generate statements
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2022-01-05 14:35:25 +00:00 |
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David Harris
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b36ace221e
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Renamed wally-pipelined to pipelined
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2022-01-04 19:47:41 +00:00 |
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