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Author SHA1 Message Date
David Harris
d27779f4c0 Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-04-07 21:57:18 -07:00
David Harris
4a2f641348 Waived coverage on BTB memory with byte write enables tied high 2023-04-07 21:56:49 -07:00
David Harris
495f2ed274 Improved RAS predictor coverage by eliminating unreachable StallM term 2023-04-07 21:37:12 -07:00
Ross Thompson
a36a8ef6f5
Merge pull request #219 from davidharrishmc/dev 
Spill logic coverage and fdivsqrt cleanup
 2023-04-07 23:30:52 -05:00
David Harris
5119222c2f Commented WFI non-flush in writeback stage of hazard unit 2023-04-07 21:27:13 -07:00
David Harris
a9b7bd101e Added vm64check tests to cover IMMU vm64 2023-04-07 21:14:52 -07:00
David Harris
25f394ce97 Fixed csrwrites.S to agree with ImperasDV. Now coverage tests pass iter-elf 2023-04-07 21:11:01 -07:00
David Harris
5c6d9f87a0 Fixed priv.S to initialize stimecmp and agree with ImperasDV 2023-04-07 20:44:01 -07:00
David Harris
7ad8d7f774 Bug fix: MTIME & MTIMEH registers are unimplemented and should fault when accessed 2023-04-07 20:43:28 -07:00
David Harris
8b4016582b Fixed WALLY-init-lib to return correctly even from traps from compressed instructions 2023-04-07 20:24:33 -07:00
David Harris
982ade31c5 Fixed enabling machine timer interrupt 2023-04-06 22:18:33 -07:00
David Harris
c9887cb182 vm64 tests 2023-04-06 21:42:47 -07:00
David Harris
c24e81c57f Division cleanup 2023-04-06 21:42:34 -07:00
David Harris
ce931d1fc5 Simplified integer division preprocessing in fdivsqrt 2023-04-06 16:43:28 -07:00
David Harris
f810ad3cec Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-04-06 14:07:59 -07:00
David Harris
1569bfbb98 Removed redundant stall signal to get spill coverage 2023-04-06 14:07:50 -07:00
Ross Thompson
87a1d12c3b Merge branch 'main' of github.com:ross144/cvw 2023-04-06 15:33:24 -05:00
Ross Thompson
b57566e632 Added Jacob's ILA script. 2023-04-06 15:32:36 -05:00
Ross Thompson
fe922c8fac Fixed syntax error. 2023-04-06 15:10:55 -05:00
Ross Thompson
270b3371f1 Added note about strange vivado behavior not inferring block ram. 2023-04-06 15:09:35 -05:00
Ross Thompson
d121364997 Similifed the no byte write enabled version of the sram model. 2023-04-06 14:18:41 -05:00
Kevin Thomas
1931859c45 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-04-06 12:38:41 -05:00
David Harris
fddbd79209
Update dvtestplan.md 2023-04-06 09:29:47 -07:00
David Harris
6431e358ca
Create dvtestplan.md 2023-04-06 09:23:09 -07:00
David Harris
4448c238c4
Merge pull request #214 from eroom1966/main 
Add in configuration for B extension
 2023-04-06 09:08:20 -07:00
Lee Moore
a20528e43c
Merge branch 'openhwgroup:main' into main 2023-04-06 16:31:49 +01:00
eroom1966
430763a1d1 add support into configuration for Zb(a,b,c,s) 2023-04-06 16:30:14 +01:00
David Harris
2a3711546f
Merge pull request #213 from eroom1966/main 
fix break to simulation testbench
 2023-04-06 06:54:59 -07:00
eroom1966
319a1b9161 fix break to simulation testbench 2023-04-06 14:45:41 +01:00
David Harris
52dcd63d1e
Merge pull request #211 from ross144/main 
Fixes the issue introduced by the fix for issue 203
 2023-04-05 21:50:32 -07:00
Ross Thompson
1478115faf Fixed wally64/32priv test hangup. 
The fix for the issue 203 had a lingering bug which did not suppress a bus access if the hptw short circuits on a pma/p fault.
 2023-04-05 23:13:45 -05:00
Kevin Thomas
5d71960385 Merge branch 'main' of https://github.com/kjprime/cvw 2023-04-05 17:44:54 -05:00
Kevin Thomas
0b317c4823
Merge branch 'openhwgroup:main' into main 2023-04-05 17:44:47 -05:00
Kevin Thomas
e70a081924 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-04-05 17:43:43 -05:00
Ross Thompson
f2c26ff886
Merge pull request #206 from AlecVercruysse/coverage2 
i$ coverage improvements
 2023-04-05 17:29:35 -05:00
David Harris
b3cf1b45fa
Merge pull request #210 from SydRiley/main 
Starting to extend fpu conditional coverage, reformatting ifu test cases.
 2023-04-05 14:56:16 -07:00
Alec Vercruysse
2a3d9f8c89 Update ram1p1rwe (ce & we) coverage exlusion explanation 2023-04-05 14:54:58 -07:00
Sydeny
d264d3274c Starting to extend fpu conditional coverage, reformating ifu test cases 2023-04-05 14:10:15 -07:00
Kevin Thomas
29dec429a0 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-04-05 15:33:10 -05:00
Kevin Thomas
c4a9bb4269 Formating white space 2023-04-05 15:30:55 -05:00
David Harris
7963bfdbe5
Merge pull request #205 from kbox13/my-single-change 
Increase LSU Coverage
 2023-04-05 13:16:04 -07:00
Kevin Thomas
7345927cb1 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-04-05 15:04:12 -05:00
David Harris
af58afd054
Merge pull request #208 from ross144/main 
Fixes Issue 203
 2023-04-05 13:03:30 -07:00
Ross Thompson
90c2156164
Merge pull request #207 from AlecVercruysse/cachesim 
Cache Simulator
 2023-04-05 14:59:52 -05:00
Ross Thompson
d1ac175e27 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-04-05 14:55:12 -05:00
Limnanthes Serafini
5bae4801bb
*.out removal 2023-04-05 12:50:26 -07:00
Limnanthes Serafini
69eecac989
*.out removal 2023-04-05 12:50:10 -07:00
Limnanthes Serafini
6f53531e26
*.out removal 2023-04-05 12:49:57 -07:00
Alec Vercruysse
61e19c2ddf Make CacheWay flush and dirty logic dependent on !READ_ONLY_CACHE 
To increase coverage. Read-only caches do not have flushes since
they do not have dirty bits.
 2023-04-05 11:48:18 -07:00
Alec Vercruysse
d3a988c96c make Cache Flush Logic dependent on !READ_ONLY_CACHE 
read-only caches do not have flush logic since they do not have to
deal with dirty bits.
 2023-04-05 11:48:18 -07:00