Ross Thompson
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91fcca9d17
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Merged together bram1p1rw with sram1p1rw as sram1p1rw.
Fixed a major issue with the real SRAM implemenation.
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2022-09-21 12:20:00 -05:00 |
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Ross Thompson
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b2f4d4aaa7
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Added chip enables to sram.
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2022-09-20 10:49:14 -05:00 |
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David Harris
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3959902c5b
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Adding decoding for dtim. Added rv32ic_wally32periph test, which should hang until decoder overrides bus
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2022-08-27 05:31:56 -07:00 |
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David Harris
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921a49921b
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Set correct size of IROM/DTIM and allow FLEN>XLEN with DTIM
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2022-08-26 21:05:20 -07:00 |
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David Harris
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8cbdbb1c38
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lsu simplification
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2022-08-25 18:52:42 -07:00 |
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David Harris
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a3828420c0
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Replaced dtim with rom-based IROM in IFU. Moved cache control signals out of DTIM and IROM
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2022-08-25 04:06:27 -07:00 |
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David Harris
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fe3147806d
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removed simpleram and modified dtim to use bram1p1rw
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2022-08-25 03:39:57 -07:00 |
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Ross Thompson
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b650d7e05a
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Renamed RAM to UNCORE_RAM.
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2022-08-24 18:09:07 -05:00 |
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Ross Thompson
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cd0da2e3b3
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Updated the names of the *WriteDataM inside the LSU to more meaningful names.
Moved the FWriteDataMux so that the bus and dtim both get fpu stores.
Modified the PMA to disallow double sized reads when XLEN=32.
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2022-08-23 10:34:39 -05:00 |
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Ross Thompson
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839bede656
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Converted over to the blockram/sram memories. Now I just need to cleanup. But before the cleanup I wan to make sure the FPGA synthesizes with these changes and actually keeps the preload.
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2022-03-30 11:04:15 -05:00 |
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Ross Thompson
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ee4b38dce3
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dtim writes are supressed on non cacheable operation.
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2022-03-12 00:46:11 -06:00 |
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Ross Thompson
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9dce2a0679
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Towards allowing dtim + bus.
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2022-03-11 14:58:21 -06:00 |
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Ross Thompson
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6d914def08
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Name cleanup.
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2022-03-10 18:44:50 -06:00 |
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Ross Thompson
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63b1ea88c9
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Signal name cleanup.
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2022-03-10 18:26:58 -06:00 |
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Ross Thompson
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396c97fc36
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Byte write enables are passing all configs now.
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2022-03-10 17:26:32 -06:00 |
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David Harris
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c61cd55c5c
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Merged TIM and regular testbenches. RV32e now working and back in regression.
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2022-02-08 12:18:13 +00:00 |
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Ross Thompson
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86bac2a083
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partial ifu cleanup.
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2022-01-31 16:08:53 -06:00 |
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Ross Thompson
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e4ee630a3e
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cleanup.
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2022-01-31 13:29:04 -06:00 |
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Ross Thompson
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9cd502d0af
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Encapsulated dtim.
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2022-01-31 11:23:55 -06:00 |
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