David Harris
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eb9787609e
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testgen-PIPELINE python startup
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2021-03-25 13:12:18 -04:00 |
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Shriya Nadgauda
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21989ee615
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adding PIPELINE tests
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2021-03-25 13:07:25 -04:00 |
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Jarred Allen
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ce6f102fc5
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Clean up some stuff
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2021-03-25 13:04:54 -04:00 |
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Jarred Allen
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128278ea27
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Working for all of rv64i now, but not compressed instructions
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2021-03-25 13:02:26 -04:00 |
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Jarred Allen
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602271ff7b
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rv64i linear control flow now working
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2021-03-25 13:02:26 -04:00 |
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Jarred Allen
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ba95557c44
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More progress on icache controller
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2021-03-25 13:01:11 -04:00 |
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Jarred Allen
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ad0d77e9e1
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Begin rewrite of icache module to use a direct-mapped scheme
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2021-03-25 13:01:10 -04:00 |
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Jarred Allen
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ebd6b931c6
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Fix bug in cache line
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2021-03-25 12:59:30 -04:00 |
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Jarred Allen
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b774d35c34
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Output NOP instead of BAD when reset
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2021-03-25 12:42:48 -04:00 |
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Jarred Allen
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4b92a595ab
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Merge branch 'main' into cache
Conflicts:
wally-pipelined/src/uncore/dtim.sv
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2021-03-25 12:10:26 -04:00 |
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Teo Ene
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51291949d8
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Config file for ppa experiments
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2021-03-25 10:23:21 -05:00 |
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David Harris
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a8abd47fbc
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Added PPA README
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2021-03-25 11:21:31 -04:00 |
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Thomas Fleming
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e3900bd0fa
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Finish finite state machines for page table walker
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2021-03-25 02:48:40 -04:00 |
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Thomas Fleming
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7367052e76
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Add vscode and pycache folders to .gitignore
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2021-03-25 02:37:50 -04:00 |
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Thomas Fleming
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b5003b093a
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2021-03-25 02:35:21 -04:00 |
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bbracker
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a3788eb218
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added 1 tick delay to dtim flops
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2021-03-25 02:23:30 -04:00 |
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bbracker
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b5fa410e15
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added 1 tick delay on tim reads
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2021-03-25 02:15:28 -04:00 |
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Jarred Allen
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682050a33b
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Merge branch 'main' into cache
Conflicts:
wally-pipelined/src/ifu/ifu.sv
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2021-03-25 00:51:12 -04:00 |
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bbracker
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67b27cd2f5
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instrfault direspecting stalls bugfix
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2021-03-25 00:44:35 -04:00 |
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bbracker
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02e924e55a
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instrfaults not respecting stalls bugfix
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2021-03-25 00:16:26 -04:00 |
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bbracker
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1e3f683a9d
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upgraded gpio bus interface
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2021-03-25 00:15:02 -04:00 |
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bbracker
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717257d9ac
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gitignore FunctionRadix.addr
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2021-03-25 00:13:46 -04:00 |
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bbracker
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e98dd420bc
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future work comment about suspicious-looking verilog in csri.sv
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2021-03-25 00:10:44 -04:00 |
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Thomas Fleming
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b1d849c822
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Add all PMP addr registers
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2021-03-24 21:58:33 -04:00 |
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Teo Ene
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f5b70c8ab8
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Manual assembly hack to prevent RV64IM coremark from EBREAKing early
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2021-03-24 18:05:34 -05:00 |
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Teo Ene
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a3aa103dc7
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Fix typo from last commit
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2021-03-24 17:09:58 -05:00 |
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Teo Ene
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4427b5ec01
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2021-03-24 17:04:48 -05:00 |
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Teo Ene
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e43849b82c
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Updated coremark_bare testbench for IM
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2021-03-24 17:04:43 -05:00 |
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Katherine Parry
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18cb1f4873
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fixed various bugs in the FMA
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2021-03-24 21:51:17 +00:00 |
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Teo Ene
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385ce9a8f9
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Added BPTYPE to coremark_bare config
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2021-03-24 16:38:29 -05:00 |
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Ross Thompson
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a99c0502e5
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Fixed bugs with the csr interacting with StallW. StallW is required to pervent updating a csr. Now have a working branch predictor and performance counters to track the number of commited branches and mispredictions.
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2021-03-24 15:56:55 -05:00 |
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Ross Thompson
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11109e5a88
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Updated the function radix to have a new name FunctionName and it now pervents false transisions from the current function name when the PCD is flushed.
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2021-03-24 13:03:43 -05:00 |
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Domenico Ottolia
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d67e28bf50
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re-organize privileged tests to be in rv64p to rv32p folders
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2021-03-24 13:51:25 -04:00 |
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Jarred Allen
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c1fe16b70b
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Give some cache mem inputs a better name
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2021-03-24 12:31:50 -04:00 |
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Ross Thompson
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d74b6eb69c
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Updated the .gitignore to reject all the extra compiled objects for the branchmarks.
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2021-03-24 10:30:19 -05:00 |
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Ross Thompson
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efa8ad4e17
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Edited sieve to work with wally. It was using the time of day to compute runspeed; however this functionality does not yet work in the wally software stack.
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2021-03-24 09:22:21 -05:00 |
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Jarred Allen
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a51257abca
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Fix compile errors from const not actually being constant (why does Verilog do this)
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2021-03-24 00:58:56 -04:00 |
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Ross Thompson
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1c6e37120e
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Fixed RAS errors. Still some room for improvement with the BTB and RAS.
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2021-03-23 23:00:44 -05:00 |
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Jarred Allen
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4410944049
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Merge branch 'main' into cache
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2021-03-23 23:35:36 -04:00 |
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Ross Thompson
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84ad1353e4
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Fixed a bunch of bugs with the RAS.
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2021-03-23 21:49:16 -05:00 |
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Katherine Parry
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56dc8de009
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fixed various bugs in the FMA
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2021-03-24 01:35:32 +00:00 |
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Ross Thompson
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4fb7a1e0a6
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Fixed the valid bit issue. Now the branch predictor is actually predicting instructions.
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2021-03-23 20:20:23 -05:00 |
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Ross Thompson
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49348d734b
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fixed issue with BTB's valid bit not updating. There is still a problem is valid not ocurring in the correct clock cycle.
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2021-03-23 20:06:45 -05:00 |
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Ross Thompson
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95dbc5f1fa
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fixed a whole bunch of bugs with the branch predictor. Still an issue with how PCNextF is not updated because the CPU is stalled.
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2021-03-23 16:53:48 -05:00 |
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Jarred Allen
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d6ecc3ede0
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Begin work on direct-mapped cache
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2021-03-23 17:03:02 -04:00 |
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Teo Ene
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ef3d2dda48
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Added BOOTTIM to InstrAccessFaultF calculation in uncore/imem
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2021-03-23 15:21:13 -05:00 |
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Ross Thompson
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174557ae89
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Simulation definitely shows the branch predictor counters and branch predictor don't work. :(
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2021-03-23 14:04:58 -05:00 |
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Ross Thompson
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5edc90b1c2
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added a whole bunch of interseting test code for branches which does not work.
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2021-03-23 13:54:59 -05:00 |
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Ross Thompson
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6a050219d4
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updated the branch predictor config.
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2021-03-23 13:54:59 -05:00 |
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Ross Thompson
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9e61481414
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Added first benchmark.
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2021-03-23 13:54:59 -05:00 |
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