12 Commits

Author	SHA1	Message	Date
Domenico Ottolia	0c307d2db1	Fix synthesis warnings for privileged unit (replace 'initial' settings)	2021-04-20 17:57:56 -04:00
Thomas Fleming	fdb20ee1cf	Implement sfence.vma and fix tlb writing	2021-04-01 15:55:05 -04:00
Noah Boorstin	bc1a0c6ee7	change ifndef to generate/if	2021-03-18 12:50:19 -04:00
Thomas Fleming	be6ee84d87	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2021-03-05 15:46:51 -05:00
Thomas Fleming	7e11317a2d	Export SATP_REGW from csrs to MMU modules	2021-03-05 01:22:53 -05:00
Noah Boorstin	f48af209c4	busybear: make CSRs only weird for us	2021-03-05 00:46:32 +00:00
David Harris	015b632eb1	Cleaned out unused signals	2021-02-26 09:17:36 -05:00
kaveh pezeshki	c7863d58cd	merged with main to integrate with AHB	2021-02-26 05:37:10 -08:00
Noah Boorstin	5835641c6c	busybear testbench: check (almost) all the CSRs	2021-02-16 20:03:24 -05:00
Noah Boorstin	14cde0d59c	Change CSR reset and available bits to conform to OVPsim ... Now actually keeping perfectly in line with OVP for the first 100k instrs. Yay.	2021-02-04 22:03:45 +00:00
David Harris	9d7e242596	Moved fpu to temporary location to fix compile and cleaned up interface formatting	2021-02-01 23:44:41 -05:00
David Harris	396cea1ea7	Reorganized src hierarchically	2021-01-30 11:50:37 -05:00