Ross Thompson
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2773048bd4
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Name cleanup.
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2023-02-28 17:48:58 -06:00 |
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Ross Thompson
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8af61c0cc0
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Name changes to reflect diagrams.
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2023-02-28 15:37:25 -06:00 |
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Ross Thompson
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44361f0a34
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Merge branch 'main' of https://github.com/openhwgroup/cvw
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2023-02-27 09:48:03 -06:00 |
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David Harris
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5c8fee127b
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Added support for ZMMUL
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2023-02-27 07:29:53 -08:00 |
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Ross Thompson
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a81cc883e9
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Signal name changes.
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2023-02-27 00:39:19 -06:00 |
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David Harris
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d2fd34efe6
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Renamed DAPageFault to UpdateDA
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2023-02-26 17:51:45 -08:00 |
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Ross Thompson
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bb276da6eb
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Merge branch 'main' of https://github.com/openhwgroup/cvw into main
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2023-02-26 12:06:06 -06:00 |
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David Harris
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4579a9d0c2
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Renamed HPTW_WRITES_SUPPORTED to SVADU_SUPPORTED
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2023-02-26 09:38:32 -08:00 |
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Ross Thompson
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e549bec060
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Renamed signals to match new figures.
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2023-02-24 19:51:47 -06:00 |
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David Harris
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bc4410e686
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Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
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2023-02-21 09:58:18 -08:00 |
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David Harris
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0b9fd8a4b3
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Fixed Issue #106: fld rasies load access fault instead of illegal instruction. The IEU controller had considered all fp loads and stores to be legal regardless of whether the FPU is enabled or the type is supported. Merged illegal instruction detection from both units into the Decode stage, saving two bits of pipeline register as well.
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2023-02-21 09:32:17 -08:00 |
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Ross Thompson
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1982c66b72
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Simiplified BTB.
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2023-02-20 15:39:42 -06:00 |
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Ross Thompson
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9c4da7381f
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Experimental branch prediction optimization.
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2023-02-10 15:45:56 -06:00 |
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Ross Thompson
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c229f0064e
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Modified branch predictor to use InstrValidE and InstrValidD rather than the more complex InstrClassE | WrongClassE logic.
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2023-02-10 10:33:10 -06:00 |
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David Harris
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99d179dd3e
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Removed pipelined level of hierarchy
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2023-02-02 14:14:11 -08:00 |
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