bbracker
8d65d50085
separated buildroot debugging from buildroot logging
2021-07-17 14:52:34 -04:00
bbracker
335afb14e7
testvector unlinker for dev purposes
2021-07-14 11:05:34 -04:00
bbracker
28887bb3d5
needed to create a directory for gdb script
2021-07-13 19:39:57 -04:00
bbracker
3565580f40
updated buildroot make procedure to incorporate configs more robustly
2021-07-13 12:40:14 -04:00
bbracker
1f52a2f938
organize/update buildroot scripts for new image
2021-07-09 17:03:47 -04:00
bbracker
44a48cf28d
organize linux-testgen folder, add readme to describe Buildroot process, add Buildroot config source files
2021-07-08 19:18:11 -04:00
bbracker
74833dc68c
split intermediate GDB output file into smaller files for better debug experience
2021-06-26 07:18:26 -04:00
bbracker
2d9c91096b
make linux testgen be nohup-friendly and make parser account for lr/sc memory accesses
2021-06-24 08:35:00 -04:00
bbracker
9b27cd6fb7
added slack notifier for long sims
2021-06-22 08:31:41 -04:00
bracker
26512348b0
gitignore merge
2021-06-18 21:12:05 -05:00
bracker
34f17b90ea
handle tera usernames more gracefully
2021-06-18 21:11:14 -05:00
bbracker
1781ae9c93
on-Tera solution for sym linking to linux testvectors
2021-06-18 22:01:18 -04:00
bracker
cd7d403f92
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-06-18 20:41:01 -05:00
bracker
0addf4a297
script support for copying large files from tera
2021-06-18 20:40:19 -05:00
bbracker
6625f74a85
still not sure if QEMU workaround is correct, but here is all linux progress so far
2021-06-17 00:50:02 -04:00
bbracker
2feb9309bb
script for running make and logging output
2021-05-17 22:12:18 -04:00
Ross Thompson
6e803b724e
Merge branch 'tests' into icache-almost-working
2021-04-25 21:25:36 -05:00
Noah Boorstin
0fa32ae5d6
buildroot parser: more updates
...
5 -> 23 instructions!
2021-04-17 17:44:46 -04:00
Ross Thompson
a64a37d702
Merge of main with the new icache and the branch predictor. I believe there is a bug in the icache with unaligned memory access. The second part of the access is incorrectly relying on the PCF being the address of the next two bytes of the instruction. However this is not always the case as the branch predictor can get the wrong target address. The icache needs to generate the +2 address internally.
2021-03-30 23:18:20 -05:00
Noah Boorstin
d02c88dab5
busybear: stop NOPing out atomics
...
and bump regression to check for 800k instrs, up from 200k
2021-03-25 13:29:56 -04:00
Thomas Fleming
7367052e76
Add vscode and pycache folders to .gitignore
2021-03-25 02:37:50 -04:00
bbracker
717257d9ac
gitignore FunctionRadix.addr
2021-03-25 00:13:46 -04:00
Ross Thompson
f92f766573
Added debug option to disable the function radix if not needed.
...
Function radix slows the simulation by 70 to 76 s (8.5%) for the rv64i tests.
2021-03-10 15:17:02 -06:00
Noah Boorstin
1858c32e9d
add .nfs* files to gitignore
2021-02-28 20:48:01 +00:00
Jarred Allen
8dcb4b2d57
Add the regression logs and new regression byproducts to the gitignore
2021-02-02 10:43:41 -05:00
Noah Boorstin
206747b8b2
Busybear test now processes first 100 instrs correctly!
...
- changed test parser to recognize lw in addition to lw
also, added temporary questa files (wlft*) to .gitignore
2021-01-28 01:19:27 -05:00
Noah Boorstin
8104b93900
load instructions from file line by line
2021-01-22 14:11:17 -05:00
Noah Boorstin
40f0b1e328
More testbench setup work
...
- Copy bare-bones testbench from E85
- have testbench instantiate a wallypipelinedhart so we can simulate memory/peripherals easier
- Create .gitignore for vsim files
- Make PC reset a macro, change to 0x1000 to conform to the bootloader
I don't know a good way to put the linux register trace file we're generating on git,
since its both nontrivial to make and way to big to keep in a git repo
for now it lives in /mnt/scratch/riscv_testbench/
2021-01-21 17:55:05 -05:00
