Katherine Parry
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c3d07b2c46
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generating all testfloat vectors
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2022-04-04 17:17:12 +00:00 |
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Ross Thompson
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67ff8f27f4
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Can now support the following memory and bus configurations.
1. dtim/irom only
2. bus only
3. dtim/irom + bus
4. caches + bus
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2022-03-11 15:18:56 -06:00 |
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bbracker
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202bd2f8f8
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change UART PLIC IRQ mapping from 4 to 10 to match virt model; move WALLY-PERIPH tests to wally arch tests
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2022-02-22 03:46:08 +00:00 |
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Ross Thompson
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0bd533473c
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New config option to enable hptw writes to PTE in memory to update Access and Dirty bits.
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2022-02-17 17:19:41 -06:00 |
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Ross Thompson
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d21be9d998
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Added config to allow using the save/restore or replay implementation to handle sram clocked read delay.
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2022-02-04 23:49:07 -06:00 |
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David Harris
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38bbe23d14
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More config file cleanup; 32ic tests broken
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2022-02-03 01:08:34 +00:00 |
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David Harris
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da8819d64b
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changed DMEM and IMEM configurations to support BUS/TIM/CACHE
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2022-02-03 00:41:09 +00:00 |
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David Harris
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68a6b4af3d
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Removed Busybear and Buildroot Configuration
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2022-02-02 20:32:22 +00:00 |
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David Harris
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4ba37d5cc0
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Config file & wally-riscv-arch-test cleanup
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2022-02-02 16:35:52 +00:00 |
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David Harris
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748375c82f
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Updated configs to fix GPIO address to match FU540
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2022-01-26 18:16:34 +00:00 |
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Ross Thompson
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a973681a90
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Added support for logic memory in the IFU and LSU. This disables the bus interface. Peripherals do not work. Also requires using testbench-harvard.sv. I hope to merge this testbench with the main testbench.sv soon.
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2022-01-13 22:21:43 -06:00 |
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Ross Thompson
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aad28366d7
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Partial local dtim in lsu configuration.
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2022-01-13 17:50:31 -06:00 |
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Ross Thompson
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06168e67e4
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Switched block for line in caches.
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2022-01-04 22:08:18 -06:00 |
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David Harris
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b36ace221e
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Renamed wally-pipelined to pipelined
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2022-01-04 19:47:41 +00:00 |
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