Ross Thompson
|
56cc04316c
|
Fixed a very subtle bug in the trap handler. It was possible to select the wrong cause if an interrupt was pending, but it was supressed by Committed and another exception triggered.
|
2022-10-02 16:21:21 -05:00 |
|
Ross Thompson
|
638e506d0b
|
Hmm. the icache and ifu didn't have a CommittedF signals going back to the privileged unit. They probably should. If an interrupt occurred during the middle of an instruction fetch icache miss I think it would corrupt the icache.
|
2022-09-28 17:39:51 -05:00 |
|
David Harris
|
113258a0d0
|
Cleaned up fcvt selection control to IEU and FPUIllegalInst signals
|
2022-08-23 12:17:19 -07:00 |
|
David Harris
|
c7ec9282fe
|
Provided sfencevmaM to hazard unit and renamed TLBFlush signals to sfencevma going into LSU/IFU. Preparing for SFENCE.VMA to flush the pipeline, but that is not yet working.
|
2022-06-02 14:18:55 +00:00 |
|
David Harris
|
aa7b0616e4
|
../src/privileged/csrc.sv
|
2022-05-31 21:12:17 +00:00 |
|
David Harris
|
788fe406b5
|
Moved delegation logic from privmode to trap to simplify interface
|
2022-05-31 14:58:11 +00:00 |
|
Ross Thompson
|
b853c4ba47
|
Updated fpga debugger.
|
2022-05-17 23:04:01 -05:00 |
|
David Harris
|
48e89485dd
|
Cause simplification
|
2022-05-12 23:47:21 +00:00 |
|
David Harris
|
9651ced9bb
|
Cause simplification
|
2022-05-12 23:39:10 +00:00 |
|
David Harris
|
2f283d9654
|
Cause simplification
|
2022-05-12 23:37:40 +00:00 |
|
David Harris
|
f5f1870077
|
Cause simplification
|
2022-05-12 23:33:35 +00:00 |
|
David Harris
|
5b7cccbc4b
|
Cause simplification
|
2022-05-12 23:33:22 +00:00 |
|
David Harris
|
581d841653
|
Cause simplification
|
2022-05-12 23:29:35 +00:00 |
|
David Harris
|
2a3f545e0c
|
Cause simplification
|
2022-05-12 23:27:02 +00:00 |
|
David Harris
|
c2b9fc0d8e
|
trap/csr cleanup
|
2022-05-12 22:26:21 +00:00 |
|
David Harris
|
292d1f33da
|
More trap/csr simplification
|
2022-05-12 22:06:03 +00:00 |
|
David Harris
|
662fffa830
|
More trap/csr simplification
|
2022-05-12 22:04:20 +00:00 |
|
David Harris
|
16b86c199c
|
More trap/csr simplification
|
2022-05-12 22:00:23 +00:00 |
|
David Harris
|
5f358a37c6
|
More trap/csr simplification
|
2022-05-12 21:55:50 +00:00 |
|
David Harris
|
21ac969c7d
|
Simplifying trap/csr interface
|
2022-05-12 21:50:15 +00:00 |
|
David Harris
|
072c464dc1
|
Simplified MTVAL logic
|
2022-05-12 21:36:13 +00:00 |
|
David Harris
|
14f9f41d2d
|
Partitioned privileged pipeline registers into module
|
2022-05-12 20:45:45 +00:00 |
|
David Harris
|
78448c7053
|
privileged cleanup
|
2022-05-12 20:21:33 +00:00 |
|
David Harris
|
dd61afb7dc
|
Formatting cleanup
|
2022-05-12 18:37:47 +00:00 |
|
David Harris
|
fde8375fbd
|
Moved Breakpoint and Ecall fault logic into privdec
|
2022-05-12 16:45:53 +00:00 |
|
David Harris
|
2ceed15bd5
|
Moved TLB Flush logic into privdec
|
2022-05-12 16:41:52 +00:00 |
|
David Harris
|
1e5d94bbab
|
Moved WFI timeout into privdec
|
2022-05-12 16:22:39 +00:00 |
|
David Harris
|
39ceb3a550
|
Partitioned privilege mode fsm into new module
|
2022-05-12 16:16:42 +00:00 |
|
David Harris
|
5670f77de2
|
More unused signal cleanup
|
2022-05-12 15:21:09 +00:00 |
|
David Harris
|
4edf9b6355
|
More unused signal cleanup
|
2022-05-12 15:15:30 +00:00 |
|
David Harris
|
1aa3e65bae
|
Removed more unused signals, simplified csri state
|
2022-05-12 15:10:10 +00:00 |
|
David Harris
|
e2e63ca9a8
|
Clean up unused signals
|
2022-05-12 14:49:58 +00:00 |
|
David Harris
|
545d46acb9
|
Simplifed mstatus.TSR handling
|
2022-05-12 14:09:52 +00:00 |
|
David Harris
|
1e7401daa0
|
Fixed typo in csrm
|
2022-05-12 06:55:39 -07:00 |
|
David Harris
|
9999f69922
|
Added MCONFIGPTR CSR hardwired to 0
|
2022-05-12 04:31:45 +00:00 |
|
David Harris
|
8166fd772e
|
Added M prefix for MTimerInt and MSwInt to distinguish from future supervisor SwInt
|
2022-05-11 15:08:33 +00:00 |
|
David Harris
|
137b411bea
|
Removed M suffix from interrupts because they are generated asynchronously to pipeline
|
2022-05-11 14:41:55 +00:00 |
|
David Harris
|
4f1b0fdc64
|
Preliminary support for big endian modes. Regression passes but no big endian tests written yet.
|
2022-05-08 06:46:35 +00:00 |
|
David Harris
|
1a5bfcf078
|
Fixed bug in delegated interrupts not being taken
|
2022-05-08 04:50:27 +00:00 |
|
David Harris
|
a516f89f22
|
WFI terminates when an interrupt is pending even if interrupts are globally disabled
|
2022-05-08 04:30:46 +00:00 |
|
David Harris
|
7f42ff06d2
|
SFENCE.VMA should be illegal in user mode
|
2022-05-05 15:15:02 +00:00 |
|
David Harris
|
f436e93fc5
|
SFENCE.VMA should be illegal in user mode
|
2022-05-05 14:59:52 +00:00 |
|
David Harris
|
9b7aab122e
|
wally32priv and wally64priv now passing WALLY-status-tw. Fixed privileged.sv to produce the correct EPC on timeouts
|
2022-05-05 14:37:21 +00:00 |
|
David Harris
|
1a7599ce94
|
Changed WFI to stall pipeline in memory stage
|
2022-05-05 02:03:44 +00:00 |
|
David Harris
|
4b91fddc0a
|
Illegal instruction fault when running FPU instruction with STATUS_FS = 0
|
2022-05-03 18:32:01 +00:00 |
|
David Harris
|
1166c40059
|
FPU generates illegal instruction if MSTATUS.FS = 00
|
2022-05-03 11:56:31 +00:00 |
|
Kip Macsai-Goren
|
33875b20b5
|
fixed initial value, timing on fs bits changing after floating point instruction
|
2022-04-25 19:17:29 +00:00 |
|
David Harris
|
0957b7040d
|
Restored MPRV behavior per spec
|
2022-04-25 14:52:18 +00:00 |
|
David Harris
|
1a8369b02b
|
Added dummy mstatus byte endianness fields tied to 0, mstatush register, removed UIE and UPIE depricated fields
|
2022-04-25 14:49:00 +00:00 |
|
David Harris
|
142636173e
|
Added MTINST hardwired to 0, and added timeout of U-mode WFI
|
2022-04-24 20:00:02 +00:00 |
|