kipmacsaigoren
|
f3579032bd
|
Cleaned up priority thermometer verilog. passses regression, ideally shortens critical path through pmp's
|
2021-07-23 11:57:58 -05:00 |
|
Kip Macsai-Goren
|
2614df627e
|
added changes to priority encoders from synthesis branch (correctly this time I hope)
|
2021-07-19 15:06:14 -04:00 |
|
David Harris
|
74b6d13195
|
Fixed missing stall in InstrRet counter
|
2021-07-08 20:08:04 -04:00 |
|
David Harris
|
2bab3f769b
|
Renamed tlb ReadLines to Matches
|
2021-07-07 06:32:26 -04:00 |
|
David Harris
|
d58cad89a8
|
Replaced muxing of upper address bits with disregarding their match. Moved WriteEnables gate into tlblru to eliminate WriteLines
|
2021-07-06 10:38:30 -04:00 |
|
David Harris
|
80666f0a71
|
Added ASID & Global PTE handling to TLB CAM
|
2021-07-04 17:52:00 -04:00 |
|
David Harris
|
07ef67e537
|
Restructured TLB Read as AND-OR operation with one-hot match/read line
|
2021-07-04 17:01:22 -04:00 |
|
David Harris
|
8337d6df68
|
Reorganized TLB to use one-hot read/write select signals to eliminate decoders and encoders
|
2021-07-04 16:33:13 -04:00 |
|
Kip Macsai-Goren
|
49515245d9
|
remove redundant decodes, fixed mmu logic ins/outs
|
2021-06-07 19:23:30 -04:00 |
|
Kip Macsai-Goren
|
1e174a8244
|
got rid of some underscores in filenames, modules
|
2021-06-07 18:54:05 -04:00 |
|