17 Commits

Author	SHA1	Message	Date
David Harris	d24bece3a8	Lint cleanup	2021-10-23 09:58:52 -07:00
David Harris	b3bded9e6c	Added more pipeline stage suffixes to divider	2021-10-02 22:54:01 -04:00
David Harris	42d573be57	SRT Division unsigned passing Imperas tests	2021-09-30 12:17:24 -04:00
bbracker	34dbad967d	ah merge; I checked and this does pass all of regression except lints	2021-06-25 07:37:06 -04:00
bbracker	192171826b	changed SC M-to-E fowarding to W-to-E forwarding to improve critical path	2021-06-25 07:18:38 -04:00
Katherine Parry	7e3483b283	FPU forwarding reworked pt.1	2021-06-24 18:39:18 -04:00
bbracker	2155a4e485	Revert "fixed forwarding" ... This reverts commit 86e369df52.	2021-06-24 17:39:37 -04:00
bbracker	86e369df52	fixed forwarding	2021-06-24 11:20:21 -04:00
Katherine Parry	1459d840ed	All compare instructions pass imperas tests	2021-05-27 15:23:28 -04:00
Katherine Parry	90d5fdba04	FMV.X.D imperas test passes	2021-05-24 14:44:30 -04:00
James E. Stine	cff08adc3a	Added some updates to divider - still not working all the time. Still a bug with signals within muldiv - specificaly MultDivE being modified during Execute stage. Seems to be triggered by ahblite signal.	2021-04-02 06:27:37 -05:00
ushakya22	6b9ae41302	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-03-30 15:25:07 -04:00
David Harris	cf03afa880	Eliminated flushing pipeline on CSR reads	2021-02-26 17:00:07 -05:00
David Harris	d00d42cf9a	Merged bus into main	2021-02-25 00:28:41 -05:00
David Harris	8dec69c2ce	Added MUL	2021-02-15 22:27:35 -05:00
David Harris	3551cc859b	Data memory bus integration	2021-02-07 23:21:55 -05:00
David Harris	c23afbda3a	Moved LoadStall generation to IEU	2021-02-02 13:42:23 -05:00