Xavi/cvw
1
0
Fork 0
forked from Github_Repos/cvw
Code Issues Pull Requests Packages Projects Releases Wiki Activity
3,682 Commits 14 Branches 1 Tag 31 MiB
06f7f9b147
Commit Graph

55 Commits

Author SHA1 Message Date
Katherine Parry
254ebf478e added fld in rv32 - needs testing 2022-06-20 22:53:13 +00:00
Madeleine Masser-Frye
ab7c936788 remove run deletion with wally synthesis 2022-06-17 19:45:38 +00:00
DTowersM
919c1818a8 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-06-13 23:34:35 +00:00
DTowersM
1f4d56ba32 added back working coremark in benchmarks/riscv64-bcoremarkdirectory, experimental simplifications are in benchmarkscoremark/ but this doesn't currently work (some type of c bug) 2022-06-13 23:23:57 +00:00
Katherine Parry
31fd8772cf postprocessing unit created and passing all tests 2022-06-13 22:47:51 +00:00
Madeleine Masser-Frye
1bf1a6d3a5 update 2022-06-03 21:17:50 +00:00
Katherine Parry
4ed7933aa3 added unpackinput.sv 2022-05-31 16:18:50 +00:00
Madeleine Masser-Frye
8506d98bec added optimized area plotting 2022-05-30 18:54:02 +00:00
Katherine Parry
950a17bef5 fixed lint error 2022-05-28 10:20:13 -07:00
Madeleine Masser-Frye
ab0b0a0da4 fixed normalization vertical axes, added TechSpecs type 2022-05-28 04:57:18 +00:00
Katherine Parry
a0ff98042c unpacker adds 1 to denorm expoents 2022-05-27 14:37:10 -07:00
Katherine Parry
95b506c5e0 some optimizations in unpacker 2022-05-27 11:36:04 -07:00
cturek
4a4f153eef Set up the divider for on-the-fly conversion 2022-05-26 16:45:28 +00:00
Katherine Parry
f3b28b988b added fcvt.sv 2022-05-26 00:10:51 +00:00
cturek
51debfa186 Fixed exponent verification, added sign module and added sign tests 2022-05-25 23:36:21 +00:00
Katherine Parry
f35450207f single and double conversions pass all tests 2022-05-25 23:02:02 +00:00
Madeleine Masser-Frye
dbe4b4bafa added widths for csa in ppa 2022-05-22 23:23:02 +00:00
Katherine Parry
5d34db85b2 Fixed unpacker bug LT EQ LE pass testfloat 2022-05-20 17:19:50 +00:00
Madeleine Masser-Frye
8015b6af17 fixed dynamic energy units 2022-05-20 01:59:19 +00:00
Katherine Parry
738bbf6479 Added fp tests - doesnpass yet 2022-05-19 16:32:30 +00:00
mmasserfrye
a10b8e47af cleaned lint for ppa.sv 2022-05-12 20:20:05 +00:00
David Harris
f17501ed8c Removing unused signals 2022-05-12 14:36:15 +00:00
mmasserfrye
6cba6a92ba filled in ppa.sv, madzscript.py now synthesizes in parallel in puts results in csv 2022-05-12 07:22:06 +00:00
Ross Thompson
b3153bc71e Updated wally to point to riscv-arch-test tag 2.7.3 2022-04-16 15:32:43 -05:00
Katherine Parry
74e0db04ac fixed errors and warnings in rv32e 2022-04-07 17:21:20 +00:00
David Harris
c4f2c6b110 fpu compare simplification, minor cleanup 2022-03-29 17:11:28 +00:00
Katherine Parry
e3d01c875b FMA parameterized and FMA testbench reworked 2022-03-19 19:39:03 +00:00
David Harris
ff674b695c Moved Softfloat / TestFloat 2022-02-26 19:17:32 +00:00
James Stine
60e19e3b67 Added the 12T submodule to the project. 2022-02-03 19:26:41 -06:00
David Harris
96a0baade4 Removed soc_flow 2022-01-31 22:58:33 +00:00
David Harris
090533cfe9 Replaced || and && with | and & 2022-01-31 01:07:35 +00:00
David Harris
3016b46d65 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-01-31 00:59:49 +00:00
David Harris
71f7d66dbf gitmodules 2022-01-31 00:59:44 +00:00
James Stine
8fd975da74 Remove book_flow to add back later - will add synthDC back within 30m 2022-01-28 08:18:30 -06:00
David Harris
064a02de18 Added synthesis submodules 2022-01-27 14:31:34 +00:00
David Harris
3a7786877a Removed and restored embench-iot 2022-01-25 22:12:28 +00:00
David Harris
12e08d8055 Fixed sumtest reference output; added embench benchmark directory 2022-01-24 23:21:09 +00:00
David Harris
55b4423329 Added E extension, and downloaded riscv-dv and embench-iot to addins 2022-01-17 14:42:59 +00:00
David Harris
486cfdc3a5 Added C test cases 2022-01-11 21:01:48 +00:00
David Harris
0e023e29d8 Code cleanup 2022-01-07 04:07:04 +00:00
Katherine Parry
b3ebce0365 some FPU test fixes 2022-01-06 23:03:20 +00:00
David Harris
81b382e51e Switched riscv-arch-test to current hash 2021-12-29 18:52:52 +00:00
David Harris
f9ab193ca8 Added partially working MMU tests 2021-12-29 03:14:16 +00:00
David Harris
48bb534658 Started FIR test code and started incorporating Imperas tests 2021-12-25 22:39:51 +00:00
David Harris
787af4287e Removed riscv-isa-sim submodule from Wally; use it in /opt/riscv instead 2021-12-21 02:35:41 +00:00
David Harris
d9f569afe1 Added irscv-arch-test and rsicv-isa-sim 2021-12-15 12:38:35 -08:00
Ross Thompson
af9f97454d Cleaned up fpga synthesis script. 2021-12-13 18:26:54 -06:00
David Harris
55f3979b67 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-12-13 07:57:49 -08:00
kwan
8f79a12cbb priviledge .* removed, passed regression 2021-12-13 00:34:43 -08:00
David Harris
d936342c97 Refactoring ALU and datapath muxes 2021-12-08 12:33:53 -08:00