Ross Thompson
290430cda8
Moved the sub cache line read logic to lsu/ifu.
2022-02-04 20:42:53 -06:00
Ross Thompson
725852362e
Got separate module for the sub cache line read.
2022-02-04 20:23:09 -06:00
Ross Thompson
cdd599e340
Second optimization of save/restore.
2022-02-04 14:35:12 -06:00
Ross Thompson
459054900f
Optimization of cache save/restore.
2022-02-04 14:21:04 -06:00
Ross Thompson
7c1f7e335c
Working first cut of the cache changes moving the replay to a save/restore.
...
The current implementation is too expensive costing (tag+linelen)*numway flip flops and muxes.
2022-02-04 13:31:32 -06:00
David Harris
65f3bf4e0a
cacheway cleanup
2022-02-03 16:52:22 +00:00
David Harris
eef04eed84
cacheway cleanup
2022-02-03 16:33:01 +00:00
David Harris
a6708ed887
cache cleanup
2022-02-03 15:36:11 +00:00
David Harris
325724f556
LSU Cleanup
2022-01-15 01:11:17 +00:00
David Harris
120fb7863f
Reformatted MIT license to 95 characters
2022-01-07 12:58:40 +00:00
Ross Thompson
0fddceffa6
Modified the mmu to not mux the lower 12 bits of the physical address and instead directly
...
assign from the input non translated virtual address. Since the lower bits never change there is
no reason to place these lower bits on a longer critical path.
The cache and lsu were previously using the lower bits from the virtual address rather than
the physical address. This change will allow us to keep the shorter critical path and
reduce the complexity of the lsu, ifu, and cache drawings.
2022-01-06 23:19:09 -06:00
Ross Thompson
008ac20a43
Minor optimization to cache replacement.
2022-01-06 17:19:14 -06:00
Ross Thompson
e1db967417
Clean up of cachefsm.
2022-01-06 16:32:49 -06:00
Ross Thompson
365b2715ed
More name cleanup in cache.
2022-01-05 22:37:53 -06:00
Ross Thompson
77efcad15b
Changed names of address in caches.
...
Removed old cache files.
2022-01-05 22:19:36 -06:00
Ross Thompson
8d33bf0b4a
Slower but correct implementation of flush.
2022-01-05 16:57:22 -06:00
Ross Thompson
bd901cd125
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-01-05 14:15:27 -06:00
Ross Thompson
49eea2add5
Fixed bug with flush dirty not cleared in the correct cache line.
2022-01-05 14:14:01 -06:00
David Harris
f04856ee94
Removed more generate statements
2022-01-05 16:01:03 +00:00
Ross Thompson
f89c1d91dc
Renamed most signals inside cache.sv so they are agnostic to i or d.
2022-01-04 23:52:42 -06:00
Ross Thompson
9eda7c12bd
the i and d caches now share common verilog.
2022-01-04 23:40:37 -06:00
