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Moved Breakpoint and Ecall fault logic into privdec

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This commit is contained in:
David Harris 2022-05-12 16:45:53 +00:00
parent 2ceed15bd5
commit fde8375fbd
2 changed files with 12 additions and 10 deletions
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10
pipelined/src/privileged/privdec.sv
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@ -40,11 +40,13 @@ module privdec (
input logic STATUS_TSR, STATUS_TVM, STATUS_TW,
input logic [1:0] STATUS_FS,
output logic IllegalInstrFaultM, ITLBFlushF, DTLBFlushM,
output logic sretM, mretM, ecallM, ebreakM, wfiM, sfencevmaM);
output logic EcallFaultM, BreakpointFaultM,
output logic sretM, mretM, wfiM, sfencevmaM);
logic IllegalPrivilegedInstrM, IllegalOrDisabledFPUInstrM;
logic WFITimeoutM;
logic StallMQ;
logic ebreakM, ecallM;
///////////////////////////////////////////
// Decode privileged instructions
@ -68,6 +70,12 @@ module privdec (
assign WFITimeoutM = ((STATUS_TW & PrivilegeModeW != `M_MODE) | (`S_SUPPORTED & PrivilegeModeW == `U_MODE)) & WFICount[`WFI_TIMEOUT_BIT];
end else assign WFITimeoutM = 0;
///////////////////////////////////////////
// Extract exceptions by name and handle them
///////////////////////////////////////////
assign BreakpointFaultM = ebreakM; // could have other causes from a debugger
assign EcallFaultM = ecallM;
///////////////////////////////////////////
// sfence.vma causes TLB flushes
///////////////////////////////////////////

12
pipelined/src/privileged/privileged.sv
View File

@ -86,7 +86,7 @@ module privileged (
logic [`XLEN-1:0] MEDELEG_REGW;
logic [11:0] MIDELEG_REGW;
logic sretM, mretM, ecallM, ebreakM, sfencevmaM;
logic sretM, mretM, sfencevmaM;
logic IllegalCSRAccessM;
logic IllegalIEUInstrFaultE, IllegalIEUInstrFaultM;
logic IllegalFPUInstrM;
@ -116,8 +116,8 @@ module privileged (
privdec pmd(.clk, .reset, .StallM, .InstrM(InstrM[31:20]),
.PrivilegedM, .IllegalIEUInstrFaultM, .IllegalCSRAccessM, .IllegalFPUInstrM,
.PrivilegeModeW, .STATUS_TSR, .STATUS_TVM, .STATUS_TW, .STATUS_FS, .IllegalInstrFaultM,
.ITLBFlushF, .DTLBFlushM,
.sretM, .mretM, .ecallM, .ebreakM, .wfiM, .sfencevmaM);
.ITLBFlushF, .DTLBFlushM, .EcallFaultM, .BreakpointFaultM,
.sretM, .mretM, .wfiM, .sfencevmaM);
///////////////////////////////////////////
// Control and Status Registers
@ -149,12 +149,6 @@ module privileged (
.CSRReadValW,
.IllegalCSRAccessM, .BigEndianM);
///////////////////////////////////////////
// Extract exceptions by name and handle them
///////////////////////////////////////////
assign BreakpointFaultM = ebreakM; // could have other causes too
assign EcallFaultM = ecallM;
// A page fault might occur because of insufficient privilege during a TLB