diff --git a/pipelined/src/privileged/privdec.sv b/pipelined/src/privileged/privdec.sv
index 7bf96d6f..8271f332 100644
--- a/pipelined/src/privileged/privdec.sv
+++ b/pipelined/src/privileged/privdec.sv
@@ -40,11 +40,13 @@ module privdec (
   input  logic         STATUS_TSR, STATUS_TVM, STATUS_TW,
   input  logic [1:0]   STATUS_FS,
   output logic         IllegalInstrFaultM, ITLBFlushF, DTLBFlushM,
-  output logic         sretM, mretM, ecallM, ebreakM, wfiM, sfencevmaM);
+  output logic         EcallFaultM, BreakpointFaultM,
+  output logic         sretM, mretM, wfiM, sfencevmaM);
 
   logic IllegalPrivilegedInstrM, IllegalOrDisabledFPUInstrM;
   logic WFITimeoutM;
   logic       StallMQ;
+  logic       ebreakM, ecallM;
 
   ///////////////////////////////////////////
   // Decode privileged instructions
@@ -68,6 +70,12 @@ module privdec (
     assign WFITimeoutM = ((STATUS_TW & PrivilegeModeW != `M_MODE) | (`S_SUPPORTED & PrivilegeModeW == `U_MODE)) & WFICount[`WFI_TIMEOUT_BIT]; 
   end else assign WFITimeoutM = 0;
 
+  ///////////////////////////////////////////
+  // Extract exceptions by name and handle them 
+  ///////////////////////////////////////////
+  assign BreakpointFaultM = ebreakM; // could have other causes from a debugger
+  assign EcallFaultM = ecallM;
+
   ///////////////////////////////////////////
   // sfence.vma causes TLB flushes
   ///////////////////////////////////////////
diff --git a/pipelined/src/privileged/privileged.sv b/pipelined/src/privileged/privileged.sv
index 20803449..7ee6ebc4 100644
--- a/pipelined/src/privileged/privileged.sv
+++ b/pipelined/src/privileged/privileged.sv
@@ -86,7 +86,7 @@ module privileged (
   logic [`XLEN-1:0] MEDELEG_REGW;
   logic [11:0]      MIDELEG_REGW;
 
-  logic sretM, mretM, ecallM, ebreakM, sfencevmaM;
+  logic sretM, mretM, sfencevmaM;
   logic IllegalCSRAccessM;
   logic IllegalIEUInstrFaultE, IllegalIEUInstrFaultM;
   logic IllegalFPUInstrM;
@@ -116,8 +116,8 @@ module privileged (
    privdec pmd(.clk, .reset, .StallM, .InstrM(InstrM[31:20]), 
               .PrivilegedM, .IllegalIEUInstrFaultM, .IllegalCSRAccessM, .IllegalFPUInstrM, 
               .PrivilegeModeW, .STATUS_TSR, .STATUS_TVM, .STATUS_TW, .STATUS_FS, .IllegalInstrFaultM, 
-              .ITLBFlushF, .DTLBFlushM,
-              .sretM, .mretM, .ecallM, .ebreakM, .wfiM, .sfencevmaM);
+              .ITLBFlushF, .DTLBFlushM, .EcallFaultM, .BreakpointFaultM,
+              .sretM, .mretM, .wfiM, .sfencevmaM);
 
   ///////////////////////////////////////////
   // Control and Status Registers
@@ -149,12 +149,6 @@ module privileged (
           .CSRReadValW,
           .IllegalCSRAccessM, .BigEndianM);
 
-  ///////////////////////////////////////////
-  // Extract exceptions by name and handle them 
-  ///////////////////////////////////////////
-
-  assign BreakpointFaultM = ebreakM; // could have other causes too
-  assign EcallFaultM = ecallM;
 
 
   // A page fault might occur because of insufficient privilege during a TLB