From fc5eac6820034c7e272a7ed0a5cdb8f9aad96e91 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Sun, 10 Apr 2022 13:27:54 -0500 Subject: [PATCH] Modified the linux test bench to take a new parameter which can run simulation from 470M out to login prompt. This shouldn't break the regression test or checkpointing. --- pipelined/regression/wally-pipelined.do | 43 +++++++++++++++++++++++-- pipelined/testbench/testbench-linux.sv | 36 +++++++++++++++------ 2 files changed, 67 insertions(+), 12 deletions(-) diff --git a/pipelined/regression/wally-pipelined.do b/pipelined/regression/wally-pipelined.do index 73e7ef51..061dac9d 100644 --- a/pipelined/regression/wally-pipelined.do +++ b/pipelined/regression/wally-pipelined.do @@ -35,7 +35,7 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} { vlog -lint -work work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 # start and run simulation vopt +acc work_${1}_${2}.testbench -work work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=$4 -G INSTR_WAVEON=$5 -G CHECKPOINT=$6 -o testbenchopt - vsim -lib work_${1}_${2} testbenchopt -suppress 8852,12070,3084 + vsim -lib work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3829 #-- Run the Simulation run -all @@ -44,7 +44,28 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} { run -all exec ./slack-notifier/slack-notifier.py - } else { + +} elseif {$2 eq "buildroot-no-trace"} { + vlog -lint -work work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 + # start and run simulation + vopt +acc work_${1}_${2}.testbench -work work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=470350800 -G INSTR_WAVEON=470350800 -G CHECKPOINT=470350800 -G NO_IE_MTIME_CHECKPOINT=1 -o testbenchopt + vsim -lib work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3829 + + #-- Run the Simulation + echo "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!" + echo "Don't forget to change DEBUG_LEVEL = 0." + echo "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!" + run 100 ns + force -deposit testbench/dut/core/priv/priv/csr/csri/IE_REGW 16'h2aa + force -deposit testbench/dut/uncore/clint/clint/MTIMECMP 64'h1000 + run 1200 ms + #add log -recursive /* + #do linux-wave.do + #run -all + + exec ./slack-notifier/slack-notifier.py + +} else { vlog +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -suppress 7063 vopt +acc work.testbench -G TEST=$2 -G DEBUG=1 -o workopt @@ -67,3 +88,21 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} { view wave } + + +#elseif {$2 eq "buildroot-no-trace""} { +# vlog -lint -work work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 + # start and run simulation +# vopt +acc work_${1}_${2}.testbench -work work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=470350800 -G INSTR_WAVEON=470350800 -G CHECKPOINT=470350800 -G DEBUG_TRACE=0 -o testbenchopt +# vsim -lib work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3829 + + #-- Run the Simulation +# run 100 ns +# force -deposit testbench/dut/core/priv/priv/csr/csri/IE_REGW 16'h2aa +# force -deposit testbench/dut/uncore/clint/clint/MTIMECMP 64'h1000 +# add log -recursive /* +# do linux-wave.do +# run -all + +# exec ./slack-notifier/slack-notifier.py +#} diff --git a/pipelined/testbench/testbench-linux.sv b/pipelined/testbench/testbench-linux.sv index 8de0f90e..bcef7dfd 100644 --- a/pipelined/testbench/testbench-linux.sv +++ b/pipelined/testbench/testbench-linux.sv @@ -45,6 +45,7 @@ module testbench; parameter INSTR_WAVEON = 0; // # of instructions at which to turn on waves in graphical sim parameter CHECKPOINT = 0; parameter RISCV_DIR = "/opt/riscv"; + parameter NO_IE_MTIME_CHECKPOINT = 0; /////////////////////////////////////////////////////////////////////////////// ////////////////////////////////// HARDWARE /////////////////////////////////// @@ -76,7 +77,16 @@ module testbench; logic SDCCmdOut; logic SDCCmdOE; logic [3:0] SDCDatIn; + + logic probe; + + if (NO_IE_MTIME_CHECKPOINT) + assign probe = testbench.dut.core.PCM == 64'hffffffff80200c8c + & testbench.dut.core.InstrM != 32'h14021273 + & testbench.dut.core.InstrValidM; + else assign probe = 0; + assign GPIOPinsIn = 0; assign UARTSin = 1; wallypipelinedsoc dut(.clk, .reset, .reset_ext, @@ -316,10 +326,12 @@ module testbench; `INIT_CHECKPOINT_VAL(PC, [`XLEN-1:0]); `INIT_CHECKPOINT_VAL(MEDELEG, [`XLEN-1:0]); `INIT_CHECKPOINT_VAL(MIDELEG, [`XLEN-1:0]); - `INIT_CHECKPOINT_VAL(MIE, [11:0]); - `INIT_CHECKPOINT_VAL(MIP, [11:0]); - `INIT_CHECKPOINT_VAL(SIE, [11:0]); - `INIT_CHECKPOINT_VAL(SIP, [11:0]); + if(!NO_IE_MTIME_CHECKPOINT) begin + `INIT_CHECKPOINT_VAL(MIE, [11:0]); + `INIT_CHECKPOINT_VAL(MIP, [11:0]); + `INIT_CHECKPOINT_VAL(SIE, [11:0]); + `INIT_CHECKPOINT_VAL(SIP, [11:0]); + end `INIT_CHECKPOINT_VAL(MCAUSE, [`XLEN-1:0]); `INIT_CHECKPOINT_VAL(SCAUSE, [`XLEN-1:0]); `INIT_CHECKPOINT_VAL(MEPC, [`XLEN-1:0]); @@ -350,13 +362,13 @@ module testbench; `INIT_CHECKPOINT_VAL(UART_SCR, [7:0]); `INIT_CHECKPOINT_PACKED_ARRAY(PLIC_INT_PRIORITY, [2:0],`PLIC_NUM_SRC,1); `INIT_CHECKPOINT_PACKED_ARRAY(PLIC_INT_ENABLE, [`PLIC_NUM_SRC:1],1,0); - `INIT_CHECKPOINT_PACKED_ARRAY(PLIC_THRESHOLD, [2:0],1,0); + `INIT_CHECKPOINT_PACKED_ARRAY(PLIC_THRESHOLD,[ 2:0],1,0); integer memFile; integer readResult; initial begin force dut.core.priv.priv.SwIntM = 0; - force dut.core.priv.priv.TimerIntM = 0; + if(!NO_IE_MTIME_CHECKPOINT) force dut.core.priv.priv.TimerIntM = 0; force dut.core.priv.priv.MExtIntM = 0; $sformat(testvectorDir,"%s/linux-testvectors/",RISCV_DIR); $sformat(linuxImageDir,"%s/buildroot/output/images/",RISCV_DIR); @@ -515,7 +527,8 @@ module testbench; release dut.core.ieu.dp.ReadDataM; \ if(textM.substr(0,5) == "rdtime") begin \ //$display("%tns, %d instrs: Overwrite MTIME_CLINT on read of MTIME in memory stage.", $time, InstrCountW-1); \ - force dut.uncore.clint.clint.MTIME = ExpectedRegValueM; \ + if(!NO_IE_MTIME_CHECKPOINT) \ + force dut.uncore.clint.clint.MTIME = ExpectedRegValueM; \ end \ end \ end \ @@ -546,7 +559,8 @@ module testbench; MIPexpected = NextMIPexpected; //force dut.core.priv.priv.csr.csri.MIP_REGW = MIPexpected; //force dut.core.priv.priv.csr.csri.SIP_REGW = MIPexpected; - force dut.core.priv.priv.csr.csri.IP_REGW = MIPexpected; + if(!NO_IE_MTIME_CHECKPOINT) + force dut.core.priv.priv.csr.csri.IP_REGW = MIPexpected; end // $display("%tn: ExpectedCSRArrayM = %p",$time,ExpectedCSRArrayM); // $display("%tn: ExpectedCSRArrayValueM = %p",$time,ExpectedCSRArrayValueM); @@ -563,7 +577,8 @@ module testbench; MIPexpected = NextMIPexpected; //force dut.core.priv.priv.csr.csri.MIP_REGW = MIPexpected; //force dut.core.priv.priv.csr.csri.SIP_REGW = MIPexpected; - force dut.core.priv.priv.csr.csri.IP_REGW = MIPexpected; + if(!NO_IE_MTIME_CHECKPOINT) + force dut.core.priv.priv.csr.csri.IP_REGW = MIPexpected; $display("%tns: Finished Executing Delayed MIP. Current MEPC value is %x",$time,dut.core.priv.priv.csr.csrm.MEPC_REGW); RequestDelayedMIP = 0; end @@ -656,7 +671,8 @@ module testbench; if(~dut.core.StallW) begin if(textW.substr(0,5) == "rdtime") begin //$display("%tns, %d instrs: Releasing force of MTIME_CLINT.", $time, InstrCountW); - release dut.uncore.clint.clint.MTIME; + if(!NO_IE_MTIME_CHECKPOINT) + release dut.uncore.clint.clint.MTIME; end //if (ExpectedIEUAdrM == 'h10000005) begin //$display("%tns, %d instrs: releasing force of ReadDataM.", $time, InstrCountW);