diff --git a/wally-pipelined/src/ahblite.sv b/wally-pipelined/src/ahblite.sv
index 4266bc36..bbbbe454 100644
--- a/wally-pipelined/src/ahblite.sv
+++ b/wally-pipelined/src/ahblite.sv
@@ -44,6 +44,7 @@ module ahblite (
   input  logic             DReadM, DWriteM,
   input  logic [`XLEN-1:0] DWDataM,
   input  logic [1:0]       DSizeM,
+  // Return from bus
   output logic [`XLEN-1:0] DRData,
 //  output logic             DReady,
   // AHB-Lite external signals
diff --git a/wally-pipelined/src/wallypipelinedhart.sv b/wally-pipelined/src/wallypipelinedhart.sv
index 1f1f1510..2814f343 100644
--- a/wally-pipelined/src/wallypipelinedhart.sv
+++ b/wally-pipelined/src/wallypipelinedhart.sv
@@ -55,6 +55,7 @@ module wallypipelinedhart (
   // new signals that must connect through DP
   logic        CSRWriteM, PrivilegedM;
   logic [`XLEN-1:0] SrcAM;
+//  logic [31:0] InstrF;
   logic [31:0] InstrD, InstrM;
   logic [`XLEN-1:0] PCE, PCM, PCLinkW;
   logic [`XLEN-1:0] PCTargetE;
@@ -100,6 +101,7 @@ module wallypipelinedhart (
     .DSizeM(Funct3M[1:0]), .DRData(ReadDataM), //.DReady(), 
     .UnsignedLoadM(Funct3M[2]),
     .*);
+  //assign InstrF = ReadDataM[31:0];
 //  assign UnsignedLoadM = Funct3M[2]; // *** maybe move read extension to dcu
 
 /*