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Simplification to EBU.

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This commit is contained in:
Ross Thompson 2022-09-29 18:06:34 -05:00
parent 146ff6ff6a
commit f9c4b32bd5
2 changed files with 4 additions and 5 deletions
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3
pipelined/src/ebu/controllerinputstage.sv
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@ -40,7 +40,7 @@ module controllerinputstage
(input logic HCLK, (input logic HCLK,
input logic HRESETn, input logic HRESETn,
input logic Save, Restore, Disable, input logic Save, Restore, Disable,
output logic Request, Active, output logic Request,
// controller input // controller input
input logic HWRITEin, input logic HWRITEin,
input logic [2:0] HSIZEin, input logic [2:0] HSIZEin,
@ -73,7 +73,6 @@ module controllerinputstage
assign Request = HTRANSOut != 2'b00; assign Request = HTRANSOut != 2'b00;
assign HREADYOut = HREADYin & ~Disable; assign HREADYOut = HREADYin & ~Disable;
assign Active = Request & HREADYOut;
endmodule endmodule

6
pipelined/src/ebu/ebu.sv
View File

@ -109,7 +109,7 @@ module ebu
// input stage IFU // input stage IFU
controllerinputstage IFUInput(.HCLK, .HRESETn, .Save(save[0]), .Restore(restore[0]), .Disable(dis[0]), controllerinputstage IFUInput(.HCLK, .HRESETn, .Save(save[0]), .Restore(restore[0]), .Disable(dis[0]),
.Request(IFUReq), .Active(IFUActive), .Request(IFUReq),
.HWRITEin(1'b0), .HSIZEin(IFUHSIZE), .HBURSTin(IFUHBURST), .HTRANSin(IFUHTRANS), .HADDRin(IFUHADDR), .HWRITEin(1'b0), .HSIZEin(IFUHSIZE), .HBURSTin(IFUHBURST), .HTRANSin(IFUHTRANS), .HADDRin(IFUHADDR),
.HWRITEOut(IFUHWRITEOut), .HSIZEOut(IFUHSIZEOut), .HBURSTOut(IFUHBURSTOut), .HREADYOut(IFUHREADY), .HWRITEOut(IFUHWRITEOut), .HSIZEOut(IFUHSIZEOut), .HBURSTOut(IFUHBURSTOut), .HREADYOut(IFUHREADY),
.HTRANSOut(IFUHTRANSOut), .HADDROut(IFUHADDROut), .HREADYin(HREADY)); .HTRANSOut(IFUHTRANSOut), .HADDROut(IFUHADDROut), .HREADYin(HREADY));
@ -117,7 +117,7 @@ module ebu
// input stage LSU // input stage LSU
// LSU always has priority so there should never be a need to save and restore the address phase inputs. // LSU always has priority so there should never be a need to save and restore the address phase inputs.
controllerinputstage LSUInput(.HCLK, .HRESETn, .Save(save[1]), .Restore(restore[1]), .Disable(dis[1]), controllerinputstage LSUInput(.HCLK, .HRESETn, .Save(save[1]), .Restore(restore[1]), .Disable(dis[1]),
.Request(LSUReq), .Active(LSUActive), .Request(LSUReq),
.HWRITEin(LSUHWRITE), .HSIZEin(LSUHSIZE), .HBURSTin(LSUHBURST), .HTRANSin(LSUHTRANS), .HADDRin(LSUHADDR), .HREADYOut(LSUHREADY), .HWRITEin(LSUHWRITE), .HSIZEin(LSUHSIZE), .HBURSTin(LSUHBURST), .HTRANSin(LSUHTRANS), .HADDRin(LSUHADDR), .HREADYOut(LSUHREADY),
.HWRITEOut(LSUHWRITEOut), .HSIZEOut(LSUHSIZEOut), .HBURSTOut(LSUHBURSTOut), .HWRITEOut(LSUHWRITEOut), .HSIZEOut(LSUHSIZEOut), .HBURSTOut(LSUHBURSTOut),
.HTRANSOut(LSUHTRANSOut), .HADDROut(LSUHADDROut), .HREADYin(HREADY)); .HTRANSOut(LSUHTRANSOut), .HADDROut(LSUHADDROut), .HREADYin(HREADY));
@ -138,7 +138,7 @@ module ebu
// FSM decides if arbitration needed. Arbitration is held until the last beat of // FSM decides if arbitration needed. Arbitration is held until the last beat of
// a burst is completed. // a burst is completed.
assign both = LSUActive & IFUActive; assign both = LSUReq & IFUReq;
flopenl #(.TYPE(statetype)) busreg(HCLK, ~HRESETn, 1'b1, NextState, IDLE, CurrState); flopenl #(.TYPE(statetype)) busreg(HCLK, ~HRESETn, 1'b1, NextState, IDLE, CurrState);
always_comb always_comb
case (CurrState) case (CurrState)