From f7d040af1e044fdda7ea455dcaacd1118ed9f507 Mon Sep 17 00:00:00 2001 From: bbracker Date: Mon, 19 Jul 2021 17:11:42 -0400 Subject: [PATCH] make testbench ignore MIP because of timing imprecision and because QEMU maybe isn't getting MTIP right anyways --- wally-pipelined/testbench/testbench-linux.sv | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/wally-pipelined/testbench/testbench-linux.sv b/wally-pipelined/testbench/testbench-linux.sv index 686da43c..fe872e17 100644 --- a/wally-pipelined/testbench/testbench-linux.sv +++ b/wally-pipelined/testbench/testbench-linux.sv @@ -530,6 +530,7 @@ module testbench(); // Checker Macros // -------------- string MSTATUSstring = "MSTATUS"; // string variables seem to compare more reliably than string literals (they gave me a lot of hassle), but *** there's probably a better way to do this + string MIPstring = "MIP"; string SEPCstring = "SEPC"; string SCAUSEstring = "SCAUSE"; string SSTATUSstring = "SSTATUS"; @@ -539,7 +540,8 @@ module testbench(); string ``CSR``name = `"CSR`"; \ string expected``CSR``name; \ always @(``PATH``.``CSR``_REGW) begin \ - if ($time > 1 && (`BUILDROOT != 1 || ``CSR``name != SSTATUSstring)) begin \ + // MIP is not checked because QEMU bodges it (MTIP in particular), and even if QEMU reported it correctly, the timing would still be off \ + if ($time > 1 && (``CSR``name != MIPstring)) begin \ // This is some feeble hackery designed to control the order in which CSRs are checked \ // when multiple change at the same time. \ if (``CSR``name == SEPCstring) #1; \