diff --git a/wally-pipelined/testbench/testbench-busybear.sv b/wally-pipelined/testbench/testbench-busybear.sv
index dff525ec..5bdf6183 100644
--- a/wally-pipelined/testbench/testbench-busybear.sv
+++ b/wally-pipelined/testbench/testbench-busybear.sv
@@ -21,7 +21,7 @@ module testbench_busybear();
   assign DataAccessFaultM = 0;
    
   // instantiate processor and memories
-  wallypipelinedhart dut(.ALUResultM(DataAdrM), .*);
+  wallypipelinedhart dut(.*);
 
   // initialize test
   initial