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renamed ahbmulticontroller to ebu.

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This commit is contained in:
Ross Thompson 2022-09-26 14:37:18 -05:00
parent fd47cf05c3
commit f24b0feeed
2 changed files with 3 additions and 2 deletions
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3
pipelined/src/ebu/ahbmulticontroller.sv → pipelined/src/ebu/ebu.sv
View File

@ -36,7 +36,7 @@
`include "wally-config.vh" `include "wally-config.vh"
module ahbmulticontroller module ebu
( (
input logic clk, reset, input logic clk, reset,
// Signals from IFU // Signals from IFU
@ -113,6 +113,7 @@ module ahbmulticontroller
.HTRANSOut(IFUHTRANSOut), .HADDROut(IFUHADDROut), .HREADYin(HREADY)); .HTRANSOut(IFUHTRANSOut), .HADDROut(IFUHADDROut), .HREADYin(HREADY));
// input stage LSU // input stage LSU
// LSU always has priority so there should never be a need to save and restore the address phase inputs.
controllerinputstage LSUInput(.HCLK, .HRESETn, .Save(save[1]), .Restore(restore[1]), .Disable(dis[1]), controllerinputstage LSUInput(.HCLK, .HRESETn, .Save(save[1]), .Restore(restore[1]), .Disable(dis[1]),
.Request(LSUReq), .Active(LSUActive), .Request(LSUReq), .Active(LSUActive),
.HWRITEin(LSUHWRITE), .HSIZEin(LSUHSIZE), .HBURSTin(LSUHBURST), .HTRANSin(LSUHTRANS), .HADDRin(LSUHADDR), .HREADYOut(LSUHREADY), .HWRITEin(LSUHWRITE), .HSIZEin(LSUHSIZE), .HBURSTin(LSUHBURST), .HTRANSin(LSUHTRANS), .HADDRin(LSUHADDR), .HREADYOut(LSUHREADY),

2
pipelined/src/wally/wallypipelinedcore.sv
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@ -289,7 +289,7 @@ module wallypipelinedcore (
// *** Ross: please make EBU conditional when only supporting internal memories // *** Ross: please make EBU conditional when only supporting internal memories
if(`BUS) begin : ebu if(`BUS) begin : ebu
ahbmulticontroller ebu(// IFU connections ebu ebu(// IFU connections
.clk, .reset, .clk, .reset,
// IFU interface // IFU interface
.IFUHADDR, .IFUHADDR,