From f24b0feeedea8b4e854d9b0e999a1ce0cb3cc10b Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Mon, 26 Sep 2022 14:37:18 -0500 Subject: [PATCH] renamed ahbmulticontroller to ebu. --- pipelined/src/ebu/{ahbmulticontroller.sv => ebu.sv} | 3 ++- pipelined/src/wally/wallypipelinedcore.sv | 2 +- 2 files changed, 3 insertions(+), 2 deletions(-) rename pipelined/src/ebu/{ahbmulticontroller.sv => ebu.sv} (98%) diff --git a/pipelined/src/ebu/ahbmulticontroller.sv b/pipelined/src/ebu/ebu.sv similarity index 98% rename from pipelined/src/ebu/ahbmulticontroller.sv rename to pipelined/src/ebu/ebu.sv index 7c86e1e7..6def3a96 100644 --- a/pipelined/src/ebu/ahbmulticontroller.sv +++ b/pipelined/src/ebu/ebu.sv @@ -36,7 +36,7 @@ `include "wally-config.vh" -module ahbmulticontroller +module ebu ( input logic clk, reset, // Signals from IFU @@ -113,6 +113,7 @@ module ahbmulticontroller .HTRANSOut(IFUHTRANSOut), .HADDROut(IFUHADDROut), .HREADYin(HREADY)); // input stage LSU + // LSU always has priority so there should never be a need to save and restore the address phase inputs. controllerinputstage LSUInput(.HCLK, .HRESETn, .Save(save[1]), .Restore(restore[1]), .Disable(dis[1]), .Request(LSUReq), .Active(LSUActive), .HWRITEin(LSUHWRITE), .HSIZEin(LSUHSIZE), .HBURSTin(LSUHBURST), .HTRANSin(LSUHTRANS), .HADDRin(LSUHADDR), .HREADYOut(LSUHREADY), diff --git a/pipelined/src/wally/wallypipelinedcore.sv b/pipelined/src/wally/wallypipelinedcore.sv index 43b929ab..8be16a33 100644 --- a/pipelined/src/wally/wallypipelinedcore.sv +++ b/pipelined/src/wally/wallypipelinedcore.sv @@ -289,7 +289,7 @@ module wallypipelinedcore ( // *** Ross: please make EBU conditional when only supporting internal memories if(`BUS) begin : ebu - ahbmulticontroller ebu(// IFU connections + ebu ebu(// IFU connections .clk, .reset, // IFU interface .IFUHADDR,