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Fixed register timing failure on SpecialCaseM in fdivsqrt

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This commit is contained in:
David Harris 2022-12-29 21:09:23 -08:00
parent 872ff619e3
commit ef37070eee
1 changed files with 2 additions and 1 deletions
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pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv
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@ -69,7 +69,8 @@ module fdivsqrtfsm(
assign ISpecialCaseE = AZeroE | BZeroE; // *** why is AZeroE part of this. Should other special cases be considered? assign ISpecialCaseE = AZeroE | BZeroE; // *** why is AZeroE part of this. Should other special cases be considered?
assign SpecialCaseE = MDUE ? ISpecialCaseE : FSpecialCaseE; assign SpecialCaseE = MDUE ? ISpecialCaseE : FSpecialCaseE;
end else assign SpecialCaseE = FSpecialCaseE; end else assign SpecialCaseE = FSpecialCaseE;
flopenr #(1) SpecialCaseReg(clk, reset, ~StallM, SpecialCaseE, SpecialCaseM); // save SpecialCase for checking in fdivsqrtpostproc //flopenr #(1) SpecialCaseReg(clk, reset, ~StallM, SpecialCaseE, SpecialCaseM); // save SpecialCase for checking in fdivsqrtpostproc
flopenr #(1) SpecialCaseReg(clk, reset, IFDivStartE, SpecialCaseE, SpecialCaseM); // save SpecialCase for checking in fdivsqrtpostproc
// DIVN = `NF+3 // DIVN = `NF+3
// NS = NF + 1 // NS = NF + 1