forked from Github_Repos/cvw
Fixed register timing failure on SpecialCaseM in fdivsqrt
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@ -69,7 +69,8 @@ module fdivsqrtfsm(
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assign ISpecialCaseE = AZeroE | BZeroE; // *** why is AZeroE part of this. Should other special cases be considered?
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assign ISpecialCaseE = AZeroE | BZeroE; // *** why is AZeroE part of this. Should other special cases be considered?
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assign SpecialCaseE = MDUE ? ISpecialCaseE : FSpecialCaseE;
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assign SpecialCaseE = MDUE ? ISpecialCaseE : FSpecialCaseE;
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end else assign SpecialCaseE = FSpecialCaseE;
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end else assign SpecialCaseE = FSpecialCaseE;
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flopenr #(1) SpecialCaseReg(clk, reset, ~StallM, SpecialCaseE, SpecialCaseM); // save SpecialCase for checking in fdivsqrtpostproc
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//flopenr #(1) SpecialCaseReg(clk, reset, ~StallM, SpecialCaseE, SpecialCaseM); // save SpecialCase for checking in fdivsqrtpostproc
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flopenr #(1) SpecialCaseReg(clk, reset, IFDivStartE, SpecialCaseE, SpecialCaseM); // save SpecialCase for checking in fdivsqrtpostproc
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// DIVN = `NF+3
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// DIVN = `NF+3
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// NS = NF + 1
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// NS = NF + 1
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