From ef37070eee0217b60f0d539cda24e92bb4327b29 Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 29 Dec 2022 21:09:23 -0800 Subject: [PATCH] Fixed register timing failure on SpecialCaseM in fdivsqrt --- pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv index a5735ba3..c16abd9b 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv @@ -69,7 +69,8 @@ module fdivsqrtfsm( assign ISpecialCaseE = AZeroE | BZeroE; // *** why is AZeroE part of this. Should other special cases be considered? assign SpecialCaseE = MDUE ? ISpecialCaseE : FSpecialCaseE; end else assign SpecialCaseE = FSpecialCaseE; - flopenr #(1) SpecialCaseReg(clk, reset, ~StallM, SpecialCaseE, SpecialCaseM); // save SpecialCase for checking in fdivsqrtpostproc + //flopenr #(1) SpecialCaseReg(clk, reset, ~StallM, SpecialCaseE, SpecialCaseM); // save SpecialCase for checking in fdivsqrtpostproc + flopenr #(1) SpecialCaseReg(clk, reset, IFDivStartE, SpecialCaseE, SpecialCaseM); // save SpecialCase for checking in fdivsqrtpostproc // DIVN = `NF+3 // NS = NF + 1