dtim writes are supressed on non cacheable operation.

pipelined/src/ifu/ifu.sv

@@ -177,7 +177,7 @@ module ifu (
     dtim irom(.clk, .reset, .CPUBusy, .LSURWM(2'b10), .IEUAdrM(PCPF[31:0]), .IEUAdrE(PCNextFSpill),
               .TrapM(1'b0), .FinalWriteDataM(), .ByteMaskM('0),
               .ReadDataWordM(FinalInstrRawF), .BusStall, .LSUBusWrite(), .LSUBusRead(IFUBusRead),
-              .BusCommittedM(), .DCacheStallM(ICacheStallF), 
+              .BusCommittedM(), .DCacheStallM(ICacheStallF), .Cacheable(CacheableF),
               .DCacheCommittedM(), .DCacheMiss(ICacheMiss), .DCacheAccess(ICacheAccess));
     
   end 

pipelined/src/lsu/dtim.sv

@@ -38,6 +38,7 @@ module dtim(
   input logic               TrapM, 
   input logic [`XLEN-1:0]   FinalWriteDataM,
   input logic [`XLEN/8-1:0] ByteMaskM,
+  input logic               Cacheable,
   output logic [`XLEN-1:0]  ReadDataWordM,
   output logic              BusStall,
   output logic              LSUBusWrite,
@@ -51,7 +52,7 @@ module dtim(
   simpleram #(.BASE(`RAM_BASE), .RANGE(`RAM_RANGE)) ram (
       .clk, .ByteMask(ByteMaskM),
       .a(CPUBusy | LSURWM[0] | reset ? IEUAdrM[31:0] : IEUAdrE[31:0]), // move mux out; this shouldn't be needed when stails are handled differently ***
-      .we(LSURWM[0] & ~TrapM),  // have to ignore write if Trap.
+      .we(LSURWM[0] & Cacheable & ~TrapM),  // have to ignore write if Trap.
       .wd(FinalWriteDataM), .rd(ReadDataWordM));
 
   // since we have a local memory the bus connections are all disabled.

pipelined/src/lsu/lsu.sv

@@ -192,7 +192,7 @@ module lsu (
     // Merge SimpleRAM and SRAM1p1rw into one that is good for synthesis and RAM libraries and flops
     dtim dtim(.clk, .reset, .CPUBusy, .LSURWM, .IEUAdrM, .IEUAdrE, .TrapM, .FinalWriteDataM, 
               .ReadDataWordM, .BusStall, .LSUBusWrite,.LSUBusRead, .BusCommittedM,
-              .DCacheStallM, .DCacheCommittedM, .ByteMaskM,
+              .DCacheStallM, .DCacheCommittedM, .ByteMaskM, .Cacheable(CacheableM),
               .DCacheMiss, .DCacheAccess);
   end 
   if (`DBUS) begin : bus